VirtualBox

Changeset 104724 in vbox


Ignore:
Timestamp:
May 20, 2024 8:06:05 AM (10 months ago)
Author:
vboxsync
svn:sync-xref-src-repo-rev:
163285
Message:

ValidationKit/bootsectors: bugref:10658 SIMD FP testcase: Preparation for using the same test worker and inner worker code for other floating-point type variants.

File:
1 edited

Legend:

Unmodified
Added
Removed

  • trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-4.c32

    r104718 r104724  
    135135
    136136/**
    137  * YMM packed double precision floating-point register.
     137 * YMM packed double-precision floating-point register.
    138138 * @todo move to x86.h?
    139139 */
    140140typedef union X86YMMFLOATPDREG
    141141{
    142     /** Double precision packed floating point view. */
     142    /** Packed double-precision floating-point view. */
    143143    RTFLOAT64U  ar64[4];
    144     /** Single precision packed floating point view. */
    145     RTFLOAT32U  ar32[8];
    146144    /** 256-bit integer view. */
    147145    RTUINT256U  ymm;
    … …  
    156154
    157155/**
    158  * YMM scalar floating-point register.
     156 * YMM packed single-precision floating-point register.
    159157 * @todo move to x86.h?
    160158 */
    161 typedef union X86YMMSFLOATREG
    162 {
    163     /** Double precision scalar floating point view. */
     159typedef union X86YMMFLOATPSREG
     160{
     161    /** Packed single-precision floating-point view. */
     162    RTFLOAT32U  ar32[8];
     163    /** 256-bit integer view. */
     164    RTUINT256U  ymm;
     165} X86YMMFLOATPSREG;
     166# ifndef VBOX_FOR_DTRACE_LIB
     167AssertCompileSize(X86YMMFLOATPSREG, 32);
     168# endif
     169/** Pointer to a YMM packed single-precision floating-point register. */
     170typedef X86YMMFLOATPSREG BS3_FAR *PX86YMMFLOATPSREG;
     171/** Pointer to a const YMM single-precision packed floating-point register. */
     172typedef X86YMMFLOATPSREG const BS3_FAR *PCX86YMMFLOATPSREG;
     173
     174/**
     175 * YMM scalar quadruple-precision floating-point register.
     176 * @todo move to x86.h?
     177 */
     178typedef union X86YMMFLOATSQREG
     179{
     180    /** Scalar quadruple-precision floating point view. */
    164181    RTFLOAT128U ar128[2];
    165182    /** 256-bit integer view. */
    166183    RTUINT256U  ymm;
    167 } X86YMMSFLOATREG;
     184} X86YMMFLOATSQREG;
    168185# ifndef VBOX_FOR_DTRACE_LIB
    169 AssertCompileSize(X86YMMSFLOATREG, 32);
     186AssertCompileSize(X86YMMFLOATSQREG, 32);
    170187# endif
    171 /** Pointer to a YMM scalar floating-point register. */
    172 typedef X86YMMSFLOATREG *PX86YMMSFLOATREG;
    173 /** Pointer to a const YMM scalar floating-point register. */
    174 typedef X86YMMSFLOATREG const *PCX86YMMSFLOATREG;
     188/** Pointer to a YMM scalar quadruple-precision floating-point register. */
     189typedef X86YMMFLOATSQREG *PX86YMMFLOATSQREG;
     190/** Pointer to a const YMM scalar quadruple-precision floating-point register. */
     191typedef X86YMMFLOATSQREG const *PCX86YMMFLOATSQREG;
    175192
    176193
    … …  
    680697#endif /* BS3_SKIPIT_DO_SKIP */
    681698
     699/*
     700 * Test type #1.
     701 * Generic YMM registers.
     702 */
     703typedef struct BS3CPUINSTR4_TEST1_VALUES_T
     704{
     705    X86YMMREG           uSrc2;               /**< Second source operand. */
     706    X86YMMREG           uSrc1;               /**< uDstIn for SSE */
     707    X86YMMREG           uDstOut;             /**< Destination output. */
     708    uint32_t            fMxCsrMask;          /**< MXCSR exception mask to use. */
     709    bool                fDenormalsAreZero;   /**< Whether DAZ (Denormals-Are-Zero) is used. */
     710    bool                fFlushToZero;        /**< Whether Flush-To-Zero (FZ) is used. */
     711    uint32_t            fRoundingCtlMask;    /**< Rounding control mask (X86_MXCSR_RC_MASK) to use. */
     712    uint32_t            fExpectedMxCsrFlags; /**< Expected MXCSR exception flags. */
     713} BS3CPUINSTR4_TEST1_VALUES_T;
     714
     715/*
     716 * Test type #1.
     717 * Packed single-precision.
     718 */
     719typedef struct BS3CPUINSTR4_TEST1_VALUES_PS_T
     720{
     721    X86YMMFLOATPSREG    uSrc2;               /**< Second source operand. */
     722    X86YMMFLOATPSREG    uSrc1;               /**< uDstIn for SSE */
     723    X86YMMFLOATPSREG    uDstOut;             /**< Destination output. */
     724    uint32_t            fMxCsrMask;          /**< MXCSR exception mask to use. */
     725    bool                fDenormalsAreZero;   /**< Whether DAZ (Denormals-Are-Zero) is used. */
     726    bool                fFlushToZero;        /**< Whether Flush-To-Zero (FZ) is used. */
     727    uint32_t            fRoundingCtlMask;    /**< Rounding control mask (X86_MXCSR_RC_MASK) to use. */
     728    uint32_t            fExpectedMxCsrFlags; /**< Expected MXCSR exception flags. */
     729} BS3CPUINSTR4_TEST1_VALUES_PS_T;
     730AssertCompile(sizeof(BS3CPUINSTR4_TEST1_VALUES_PS_T) == sizeof(BS3CPUINSTR4_TEST1_VALUES_T));
     731AssertCompileMembersSameSizeAndOffset(BS3CPUINSTR4_TEST1_VALUES_PS_T, uSrc2,               BS3CPUINSTR4_TEST1_VALUES_T, uSrc2);
     732AssertCompileMembersSameSizeAndOffset(BS3CPUINSTR4_TEST1_VALUES_PS_T, uSrc1,               BS3CPUINSTR4_TEST1_VALUES_T, uSrc1);
     733AssertCompileMembersSameSizeAndOffset(BS3CPUINSTR4_TEST1_VALUES_PS_T, uDstOut,             BS3CPUINSTR4_TEST1_VALUES_T, uDstOut);
     734AssertCompileMembersSameSizeAndOffset(BS3CPUINSTR4_TEST1_VALUES_PS_T, fMxCsrMask,          BS3CPUINSTR4_TEST1_VALUES_T, fMxCsrMask);
     735AssertCompileMembersSameSizeAndOffset(BS3CPUINSTR4_TEST1_VALUES_PS_T, fDenormalsAreZero,   BS3CPUINSTR4_TEST1_VALUES_T, fDenormalsAreZero);
     736AssertCompileMembersSameSizeAndOffset(BS3CPUINSTR4_TEST1_VALUES_PS_T, fFlushToZero,        BS3CPUINSTR4_TEST1_VALUES_T, fFlushToZero);
     737AssertCompileMembersSameSizeAndOffset(BS3CPUINSTR4_TEST1_VALUES_PS_T, fRoundingCtlMask,    BS3CPUINSTR4_TEST1_VALUES_T, fRoundingCtlMask);
     738AssertCompileMembersSameSizeAndOffset(BS3CPUINSTR4_TEST1_VALUES_PS_T, fExpectedMxCsrFlags, BS3CPUINSTR4_TEST1_VALUES_T, fExpectedMxCsrFlags);
    682739
    683740/*
    … …  
    696753    uint32_t            fExpectedMxCsrFlags; /**< Expected MXCSR exception flags. */
    697754} BS3CPUINSTR4_TEST1_VALUES_PD_T;
     755AssertCompile(sizeof(BS3CPUINSTR4_TEST1_VALUES_PD_T) == sizeof(BS3CPUINSTR4_TEST1_VALUES_T));
     756AssertCompileMembersSameSizeAndOffset(BS3CPUINSTR4_TEST1_VALUES_PD_T, uSrc2,               BS3CPUINSTR4_TEST1_VALUES_T, uSrc2);
     757AssertCompileMembersSameSizeAndOffset(BS3CPUINSTR4_TEST1_VALUES_PD_T, uSrc1,               BS3CPUINSTR4_TEST1_VALUES_T, uSrc1);
     758AssertCompileMembersSameSizeAndOffset(BS3CPUINSTR4_TEST1_VALUES_PD_T, uDstOut,             BS3CPUINSTR4_TEST1_VALUES_T, uDstOut);
     759AssertCompileMembersSameSizeAndOffset(BS3CPUINSTR4_TEST1_VALUES_PD_T, fMxCsrMask,          BS3CPUINSTR4_TEST1_VALUES_T, fMxCsrMask);
     760AssertCompileMembersSameSizeAndOffset(BS3CPUINSTR4_TEST1_VALUES_PD_T, fDenormalsAreZero,   BS3CPUINSTR4_TEST1_VALUES_T, fDenormalsAreZero);
     761AssertCompileMembersSameSizeAndOffset(BS3CPUINSTR4_TEST1_VALUES_PD_T, fFlushToZero,        BS3CPUINSTR4_TEST1_VALUES_T, fFlushToZero);
     762AssertCompileMembersSameSizeAndOffset(BS3CPUINSTR4_TEST1_VALUES_PD_T, fRoundingCtlMask,    BS3CPUINSTR4_TEST1_VALUES_T, fRoundingCtlMask);
     763AssertCompileMembersSameSizeAndOffset(BS3CPUINSTR4_TEST1_VALUES_PD_T, fExpectedMxCsrFlags, BS3CPUINSTR4_TEST1_VALUES_T, fExpectedMxCsrFlags);
     764
     765/*
     766 * Test type #1.
     767 * Scalar quadruple-precision.
     768 */
     769typedef struct BS3CPUINSTR4_TEST1_VALUES_SQ_T
     770{
     771    X86YMMFLOATSQREG    uSrc2;               /**< Second source operand. */
     772    X86YMMFLOATSQREG    uSrc1;               /**< uDstIn for SSE */
     773    X86YMMFLOATSQREG    uDstOut;             /**< Destination output. */
     774    uint32_t            fMxCsrMask;          /**< MXCSR exception mask to use. */
     775    bool                fDenormalsAreZero;   /**< Whether DAZ (Denormals-Are-Zero) is used. */
     776    bool                fFlushToZero;        /**< Whether Flush-To-Zero (FZ) is used. */
     777    uint32_t            fRoundingCtlMask;    /**< Rounding control mask (X86_MXCSR_RC_MASK) to use. */
     778    uint32_t            fExpectedMxCsrFlags; /**< Expected MXCSR exception flags. */
     779} BS3CPUINSTR4_TEST1_VALUES_SQ_T;
     780AssertCompile(sizeof(BS3CPUINSTR4_TEST1_VALUES_SQ_T) == sizeof(BS3CPUINSTR4_TEST1_VALUES_T));
     781AssertCompileMembersSameSizeAndOffset(BS3CPUINSTR4_TEST1_VALUES_SQ_T, uSrc2,               BS3CPUINSTR4_TEST1_VALUES_T, uSrc2);
     782AssertCompileMembersSameSizeAndOffset(BS3CPUINSTR4_TEST1_VALUES_SQ_T, uSrc1,               BS3CPUINSTR4_TEST1_VALUES_T, uSrc1);
     783AssertCompileMembersSameSizeAndOffset(BS3CPUINSTR4_TEST1_VALUES_SQ_T, uDstOut,             BS3CPUINSTR4_TEST1_VALUES_T, uDstOut);
     784AssertCompileMembersSameSizeAndOffset(BS3CPUINSTR4_TEST1_VALUES_SQ_T, fMxCsrMask,          BS3CPUINSTR4_TEST1_VALUES_T, fMxCsrMask);
     785AssertCompileMembersSameSizeAndOffset(BS3CPUINSTR4_TEST1_VALUES_SQ_T, fDenormalsAreZero,   BS3CPUINSTR4_TEST1_VALUES_T, fDenormalsAreZero);
     786AssertCompileMembersSameSizeAndOffset(BS3CPUINSTR4_TEST1_VALUES_SQ_T, fFlushToZero,        BS3CPUINSTR4_TEST1_VALUES_T, fFlushToZero);
     787AssertCompileMembersSameSizeAndOffset(BS3CPUINSTR4_TEST1_VALUES_SQ_T, fRoundingCtlMask,    BS3CPUINSTR4_TEST1_VALUES_T, fRoundingCtlMask);
     788AssertCompileMembersSameSizeAndOffset(BS3CPUINSTR4_TEST1_VALUES_SQ_T, fExpectedMxCsrFlags, BS3CPUINSTR4_TEST1_VALUES_T, fExpectedMxCsrFlags);
    698789
    699790typedef struct BS3CPUINSTR4_TEST1_T
    … …  
    707798    uint8_t             iRegSrc2;            /**< Index of second source register, UINT8_MAX if N/A. */
    708799    uint8_t             cValues;             /**< Number of test values in @c paValues. */
    709     BS3CPUINSTR4_TEST1_VALUES_PD_T const BS3_FAR *paValues; /**< Test values. */
     800    BS3CPUINSTR4_TEST1_VALUES_T const BS3_FAR *paValues; /**< Test values. */
    710801} BS3CPUINSTR4_TEST1_T;
    711802
    … …  
    749840                                                   PCBS3CPUINSTRX_CONFIG_SAVED_T pSavedCfg)
    750841{
    751     BS3CPUINSTR4_TEST1_T const BS3_FAR           *pTest   = pTestCtx->pTest;
    752     BS3CPUINSTR4_TEST1_VALUES_PD_T const BS3_FAR *pValues = &pTestCtx->pTest->paValues[pTestCtx->iVal];
     842    BS3CPUINSTR4_TEST1_T const BS3_FAR        *pTest   = pTestCtx->pTest;
     843    BS3CPUINSTR4_TEST1_VALUES_T const BS3_FAR *pValues = &pTestCtx->pTest->paValues[pTestCtx->iVal];
    753844    PBS3TRAPFRAME    pTrapFrame     = pTestCtx->pTrapFrame;
    754845    PBS3REGCTX       pCtx           = pTestCtx->pCtx;
    … …  
    870961            char szGotBuf[BS3_FP_XCPT_NAMES_MAXLEN];
    871962            char szExpectBuf[BS3_FP_XCPT_NAMES_MAXLEN];
    872             bs3CpuInstr4GetXcptFlags(&szExpectBuf[0], sizeof(szExpectBuf),  pValues->fExpectedMxCsrFlags);
     963            bs3CpuInstr4GetXcptFlags(&szExpectBuf[0], sizeof(szExpectBuf), pValues->fExpectedMxCsrFlags);
    873964            bs3CpuInstr4GetXcptFlags(&szGotBuf[0], sizeof(szGotBuf),  fMxCsrXcptFlags);
    874965            Bs3TestFailedF("Expected floating-point xcpt flags%s, got%s", szExpectBuf, szGotBuf);
    … …  
    10191110                        for (iVal = 0; iVal < cValues; iVal++, idTestStep++, cRecompRuns++)
    10201111                        {
    1021                             uint16_t cErrors;
     1112                            uint16_t                 cErrors;
    10221113                            BS3CPUINSTR4_TEST1_CTX_T TestCtx;
    1023 
    10241114                            if (BS3_SKIPIT(bRing, iCfg, iTest, iVal, 0))
    10251115                                continue;
    … …  
    10301120                             * it outside the inner most loop is more optimal.
    10311121                             */
    1032                             TestCtx.pConfig             = &paConfigs[iCfg];
    1033                             TestCtx.pTest               = pTest;
    1034                             TestCtx.iVal                = iVal;
    1035                             TestCtx.pszMode             = pszMode;
    1036                             TestCtx.pTrapFrame          = &TrapFrame;
    1037                             TestCtx.pCtx                = &Ctx;
    1038                             TestCtx.pExtCtx             = pExtCtx;
    1039                             TestCtx.pExtCtxOut          = pExtCtxOut;
    1040                             TestCtx.puMemOp             = (uint8_t *)puMemOp;
    1041                             TestCtx.puMemOpAlias        = puMemOpAlias;
    1042                             TestCtx.cbMemOp             = cbMemOp;
    1043                             TestCtx.cbOperand           = cbOperand;
    1044                             TestCtx.bXcptExpect         = bXcptExpect;
    1045                             TestCtx.fSseInstr           = fSseInstr;
    1046                             TestCtx.idTestStep          = idTestStep;
     1122                            TestCtx.pConfig      = &paConfigs[iCfg];
     1123                            TestCtx.pTest        = pTest;
     1124                            TestCtx.iVal         = iVal;
     1125                            TestCtx.pszMode      = pszMode;
     1126                            TestCtx.pTrapFrame   = &TrapFrame;
     1127                            TestCtx.pCtx         = &Ctx;
     1128                            TestCtx.pExtCtx      = pExtCtx;
     1129                            TestCtx.pExtCtxOut   = pExtCtxOut;
     1130                            TestCtx.puMemOp      = (uint8_t *)puMemOp;
     1131                            TestCtx.puMemOpAlias = puMemOpAlias;
     1132                            TestCtx.cbMemOp      = cbMemOp;
     1133                            TestCtx.cbOperand    = cbOperand;
     1134                            TestCtx.bXcptExpect  = bXcptExpect;
     1135                            TestCtx.fSseInstr    = fSseInstr;
     1136                            TestCtx.idTestStep   = idTestStep;
    10471137                            cErrors = bs3CpuInstr4_WorkerTestType1_Inner(bMode, &TestCtx, &SavedCfg);
    1048 
    10491138                            if (cErrors != Bs3TestSubErrorCount())
    10501139                            {
    … …  
    11261215    static BS3CPUINSTR4_TEST1_T const s_aTests16[] =
    11271216    {
    1128         { bs3CpuInstrX_addpd_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues },
     1217        { bs3CpuInstrX_addpd_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE, 1, 1, 2, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
    11291218    };
    11301219    static BS3CPUINSTR4_TEST1_T const s_aTests32[] =
    11311220    {
    1132         { bs3CpuInstrX_addpd_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues },
     1221        { bs3CpuInstrX_addpd_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE, 1, 1, 2, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
    11331222    };
    11341223    static BS3CPUINSTR4_TEST1_T const s_aTests64[] =
    11351224    {
    1136         { bs3CpuInstrX_addpd_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues },
     1225        { bs3CpuInstrX_addpd_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE, 1, 1, 2, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
    11371226    };
    11381227
Note: See TracChangeset for help on using the changeset viewer.

© 2025 Oracle Support Privacy / Do Not Sell My Info Terms of Use Trademark Policy Automated Access Etiquette