Changeset 10473 in vbox

Timestamp:

Jul 10, 2008 3:02:53 PM (17 years ago)

Author:

vboxsync

svn:sync-xref-src-repo-rev:

33146

Message:

MMIO instruction emulation for OR, BT and XOR added.

Location:

trunk

Files:

• include/VBox/em.h (modified) (1 diff)
• src/VBox/VMM/IOM.cpp (modified) (1 diff)
• src/VBox/VMM/IOMInternal.h (modified) (1 diff)
• src/VBox/VMM/VMMAll/EMAll.cpp (modified) (1 diff)
• src/VBox/VMM/VMMAll/IOMAllMMIO.cpp (modified) (8 diffs)
• src/VBox/VMM/VMMR0/HWVMXR0.cpp (modified) (2 diffs)

trunk/include/VBox/em.h

@@ -78 +78 @@
 } EMSTATE;
 
+/*
+ * Callback handlers for instruction emulation functions.
+ */
+typedef DECLCALLBACK(uint32_t) PFN_EMULATE_PARAM2_UINT32(void *pvParam1, uint64_t val2);
+typedef DECLCALLBACK(uint32_t) PFN_EMULATE_PARAM2(void *pvParam1, size_t val2);
+typedef DECLCALLBACK(uint32_t) PFN_EMULATE_PARAM3(void *pvParam1, uint64_t val2, size_t val3);
+typedef DECLCALLBACK(int)      FNEMULATELOCKPARAM2(void *pvParam1, uint64_t val2, RTGCUINTREG32 *pf);
+typedef FNEMULATELOCKPARAM2 *PFNEMULATELOCKPARAM2;
+typedef DECLCALLBACK(int)      FNEMULATELOCKPARAM3(void *pvParam1, uint64_t val2, size_t cb, RTGCUINTREG32 *pf);
+typedef FNEMULATELOCKPARAM3 *PFNEMULATELOCKPARAM3;
 
 /**

trunk/src/VBox/VMM/IOM.cpp

@@ -132 +132 @@
         STAM_REG(pVM, &pVM->iom.s.StatGCInstCmp,          STAMTYPE_PROFILE, "/IOM/GC/Inst/CMP",            STAMUNIT_TICKS_PER_CALL, "Profiling of the CMP instruction emulation.");
         STAM_REG(pVM, &pVM->iom.s.StatGCInstAnd,          STAMTYPE_PROFILE, "/IOM/GC/Inst/AND",            STAMUNIT_TICKS_PER_CALL, "Profiling of the AND instruction emulation.");
+        STAM_REG(pVM, &pVM->iom.s.StatGCInstOr,           STAMTYPE_PROFILE, "/IOM/GC/Inst/OR",             STAMUNIT_TICKS_PER_CALL, "Profiling of the OR instruction emulation.");
+        STAM_REG(pVM, &pVM->iom.s.StatGCInstXor,          STAMTYPE_PROFILE, "/IOM/GC/Inst/XOR",            STAMUNIT_TICKS_PER_CALL, "Profiling of the XOR instruction emulation.");
+        STAM_REG(pVM, &pVM->iom.s.StatGCInstBt,           STAMTYPE_PROFILE, "/IOM/GC/Inst/BT",             STAMUNIT_TICKS_PER_CALL, "Profiling of the BT instruction emulation.");
         STAM_REG(pVM, &pVM->iom.s.StatGCInstTest,         STAMTYPE_PROFILE, "/IOM/GC/Inst/TEST",           STAMUNIT_TICKS_PER_CALL, "Profiling of the TEST instruction emulation.");
         STAM_REG(pVM, &pVM->iom.s.StatGCInstXchg,         STAMTYPE_PROFILE, "/IOM/GC/Inst/XCHG",           STAMUNIT_TICKS_PER_CALL, "Profiling of the XCHG instruction emulation.");

trunk/src/VBox/VMM/IOMInternal.h

@@ -390 +390 @@
     STAMPROFILE             StatGCInstCmp;
     STAMPROFILE             StatGCInstAnd;
+    STAMPROFILE             StatGCInstOr;
+    STAMPROFILE             StatGCInstXor;
+    STAMPROFILE             StatGCInstBt;
     STAMPROFILE             StatGCInstTest;
     STAMPROFILE             StatGCInstXchg;

trunk/src/VBox/VMM/VMMAll/EMAll.cpp

@@ -51 +51 @@
 *   Structures and Typedefs                                                    *
 *******************************************************************************/
-typedef DECLCALLBACK(uint32_t) PFN_EMULATE_PARAM2_UINT32(void *pvParam1, uint64_t val2);
-typedef DECLCALLBACK(uint32_t) PFN_EMULATE_PARAM2(void *pvParam1, size_t val2);
-typedef DECLCALLBACK(uint32_t) PFN_EMULATE_PARAM3(void *pvParam1, uint64_t val2, size_t val3);
-typedef DECLCALLBACK(int)      FNEMULATELOCKPARAM2(void *pvParam1, uint64_t val2, RTGCUINTREG32 *pf);
-typedef FNEMULATELOCKPARAM2 *PFNEMULATELOCKPARAM2;
-typedef DECLCALLBACK(int)      FNEMULATELOCKPARAM3(void *pvParam1, uint64_t val2, size_t cb, RTGCUINTREG32 *pf);
-typedef FNEMULATELOCKPARAM3 *PFNEMULATELOCKPARAM3;
 
 

trunk/src/VBox/VMM/VMMAll/IOMAllMMIO.cpp

@@ -748 +748 @@
  * AND [MMIO], reg|imm
  * AND reg, [MMIO]
+ * OR [MMIO], reg|imm
+ * OR reg, [MMIO]
  *
  * Restricted implementation.
@@ -759 +761 @@
  * @param   pCpu        Disassembler CPU state.
  * @param   pRange      Pointer MMIO range.
- */
-static int iomInterpretAND(PVM pVM, PCPUMCTXCORE pRegFrame, RTGCPHYS GCPhysFault, PDISCPUSTATE pCpu, PIOMMMIORANGE pRange)
+ * @param   pfnEmulate  Instruction emulation function.
+ */
+static int iomInterpretOrXorAnd(PVM pVM, PCPUMCTXCORE pRegFrame, RTGCPHYS GCPhysFault, PDISCPUSTATE pCpu, PIOMMMIORANGE pRange, PFN_EMULATE_PARAM3 pfnEmulate)
 {
     unsigned    cb = 0;
@@ -767 +770 @@
     bool        fAndWrite;
     int         rc;
+
+#ifdef LOG_ENABLED
+    const char *pszInstr;
+
+    if (pCpu->pCurInstr->opcode == OP_XOR)
+        pszInstr = "Xor";
+    else if (pCpu->pCurInstr->opcode == OP_OR)
+        pszInstr = "Or";
+    else if (pCpu->pCurInstr->opcode == OP_AND)
+        pszInstr = "And";
+    else
+        pszInstr = "OrXorAnd??";
+#endif
+
     if (iomGetRegImmData(pCpu, &pCpu->param1, pRegFrame, &uData1, &cb))
     {
@@ -793 +810 @@
     {
         /* Emulate AND and update guest flags. */
-        uint32_t eflags = EMEmulateAnd((uint32_t *)&uData1, uData2, cb);
+        uint32_t eflags = pfnEmulate((uint32_t *)&uData1, uData2, cb);
+
+        LogFlow(("iomInterpretOrXorAnd %s result %RX64\n", pszInstr, uData1));
+
         if (fAndWrite)
             /* Store result to MMIO. */
@@ -815 +835 @@
 }
 
-
-
 /**
  * TEST [MMIO], reg|imm
@@ -863 +881 @@
         pRegFrame->eflags.u32 = (pRegFrame->eflags.u32 & ~(X86_EFL_CF | X86_EFL_PF | X86_EFL_AF | X86_EFL_ZF | X86_EFL_SF | X86_EFL_OF))
                               | (eflags                &  (X86_EFL_CF | X86_EFL_PF | X86_EFL_AF | X86_EFL_ZF | X86_EFL_SF | X86_EFL_OF));
+        iomMMIOStatLength(pVM, cb);
+    }
+
+    return rc;
+}
+
+/**
+ * BT [MMIO], reg|imm
+ *
+ * Restricted implementation.
+ *
+ *
+ * @returns VBox status code.
+ *
+ * @param   pVM         The virtual machine (GC pointer ofcourse).
+ * @param   pRegFrame   Trap register frame.
+ * @param   GCPhysFault The GC physical address corresponding to pvFault.
+ * @param   pCpu        Disassembler CPU state.
+ * @param   pRange      Pointer MMIO range.
+ */
+static int iomInterpretBT(PVM pVM, PCPUMCTXCORE pRegFrame, RTGCPHYS GCPhysFault, PDISCPUSTATE pCpu, PIOMMMIORANGE pRange)
+{
+    Assert(pRange->CTXALLSUFF(pfnReadCallback) || !pRange->pfnReadCallbackR3);
+
+    uint64_t    uBit;
+    uint64_t    uData1;
+    int         rc;
+    unsigned    cb;
+
+    if (iomGetRegImmData(pCpu, &pCpu->param2, pRegFrame, &uBit, &cb))
+    {
+        /* bt [MMIO], reg|imm. */
+        rc = iomMMIODoRead(pVM, pRange, GCPhysFault, &uData1, cb);
+    }
+    else
+    {
+        AssertMsgFailed(("Disassember BT problem..\n"));
+        return VERR_IOM_MMIO_HANDLER_DISASM_ERROR;
+    }
+
+    if (rc == VINF_SUCCESS)
+    {
+        /* The size of the memory operand only matters here. */
+        cb = DISGetParamSize(pCpu, &pCpu->param1);
+
+        /* Find the bit inside the faulting address */
+        uBit &= (cb*8 - 1);
+
+        pRegFrame->eflags.Bits.u1CF = (uData1 >> uBit);
         iomMMIOStatLength(pVM, cb);
     }
@@ -1062 +1129 @@
         case OP_AND:
             STAM_PROFILE_START(&pVM->iom.s.StatGCInstAnd, g);
-            rc = iomInterpretAND(pVM, pCtxCore, GCPhysFault, &Cpu, pRange);
+            rc = iomInterpretOrXorAnd(pVM, pCtxCore, GCPhysFault, &Cpu, pRange, EMEmulateAnd);
             STAM_PROFILE_STOP(&pVM->iom.s.StatGCInstAnd, g);
+            break;
+
+        case OP_OR:
+            STAM_PROFILE_START(&pVM->iom.s.StatGCInstOr, k);
+            rc = iomInterpretOrXorAnd(pVM, pCtxCore, GCPhysFault, &Cpu, pRange, EMEmulateOr);
+            STAM_PROFILE_STOP(&pVM->iom.s.StatGCInstOr, k);
+            break;
+
+        case OP_XOR:
+            STAM_PROFILE_START(&pVM->iom.s.StatGCInstXor, m);
+            rc = iomInterpretOrXorAnd(pVM, pCtxCore, GCPhysFault, &Cpu, pRange, EMEmulateXor);
+            STAM_PROFILE_STOP(&pVM->iom.s.StatGCInstXor, m);
             break;
 
@@ -1071 +1150 @@
             rc = iomInterpretTEST(pVM, pCtxCore, GCPhysFault, &Cpu, pRange);
             STAM_PROFILE_STOP(&pVM->iom.s.StatGCInstTest, h);
+            break;
+
+        case OP_BT:
+            Assert(!(uErrorCode & X86_TRAP_PF_RW));
+            STAM_PROFILE_START(&pVM->iom.s.StatGCInstBt, l);
+            rc = iomInterpretBT(pVM, pCtxCore, GCPhysFault, &Cpu, pRange);
+            STAM_PROFILE_STOP(&pVM->iom.s.StatGCInstBt, l);
             break;
 

trunk/src/VBox/VMM/VMMR0/HWVMXR0.cpp

@@ -1186 +1186 @@
     /* Note the 32 bits exception for AMD (X86_CPUID_AMD_FEATURE_ECX_CR8L), but that appears missing in Intel CPUs */
     /* Note: we can't do this in LoadGuestState as PDMApicGetTPR can jump back to ring 3 (lock). */
+    /*
+     * @todo reduce overhead
+     */
     if (    pCtx->msrEFER & MSR_K6_EFER_LMA
         &&  pVM->hwaccm.s.vmx.pAPIC)
@@ -1410 +1413 @@
     pCtx->eflags.u32        = val;
 
-    /* Update the APIC with the cached TPR value. */
+    /* Update the APIC with the cached TPR value.
+     * @todo reduce overhead
+     */
     if (    pCtx->msrEFER & MSR_K6_EFER_LMA
         &&  pVM->hwaccm.s.vmx.pAPIC)