Changeset 104767 in vbox for trunk/src

Timestamp:

May 23, 2024 12:03:04 PM (8 months ago)

Author:

vboxsync

Message:

VMM/PGM,IOM,PDM: MMIO cleanups. bugref:10687

Location:

trunk/src/VBox/VMM

Files:

• VMMAll/PGMAllBth.h (modified) (2 diffs)
• VMMAll/PGMAllGst.h (modified) (7 diffs)
• VMMR3/IOMR3Mmio.cpp (modified) (6 diffs)
• VMMR3/PDMDevHlp.cpp (modified) (2 diffs)
• VMMR3/PDMDevHlpTracing.cpp (modified) (2 diffs)
• VMMR3/PGMPhys.cpp (modified) (7 diffs)

trunk/src/VBox/VMM/VMMAll/PGMAllBth.h

@@ -2312 +2312 @@
                 else /* MMIO or invalid page: emulated in #PF handler. */
                 {
-                    LogFlow(("PGM_GCPHYS_2_PTR %RGp failed with %Rrc\n", GCPhys, rc));
+                    LogFlow(("PGM_GCPHYS_2_PTR_V2 %RGp failed with %Rrc\n", GCPhys, rc));
                     Assert(!SHW_PTE_IS_P(pPTDst->a[(GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK]));
                 }
@@ -2409 +2409 @@
                 else
                 {
-                    LogFlow(("PGM_GCPHYS_2_PTR %RGp (big) failed with %Rrc\n", GCPhys, rc));
+                    LogFlow(("pgmPhysGetPageEx %RGp (big) failed with %Rrc\n", GCPhys, rc));
                     /** @todo must wipe the shadow page table entry in this
                      *        case. */

trunk/src/VBox/VMM/VMMAll/PGMAllGst.h

@@ -123 +123 @@
  * @param   pWalk       The page walk info.
  * @param   pGstWalk    The guest mode specific page walk info.
+ * @thread  EMT(pVCpu)
  */
 DECLINLINE(int) PGM_GST_NAME(Walk)(PVMCPUCC pVCpu, RTGCPTR GCPtr, PPGMPTWALK pWalk, PGSTPTWALK pGstWalk)
@@ -361 +362 @@
  * Gets effective Guest OS page information.
  *
- * When GCPtr is in a big page, the function will return as if it was a normal
- * 4KB page. If the need for distinguishing between big and normal page becomes
- * necessary at a later point, a PGMGstGetPage Ex() will be created for that
- * purpose.
- *
  * @returns VBox status code.
  * @param   pVCpu       The cross context virtual CPU structure.
  * @param   GCPtr       Guest Context virtual address of the page.
  * @param   pWalk       Where to store the page walk info.
+ * @thread  EMT(pVCpu)
  */
 PGM_GST_DECL(int, GetPage)(PVMCPUCC pVCpu, RTGCPTR GCPtr, PPGMPTWALK pWalk)
@@ -376 +373 @@
  || PGM_GST_TYPE == PGM_TYPE_PROT
 
-    RT_ZERO(*pWalk);
 # ifdef VBOX_WITH_NESTED_HWVIRT_VMX_EPT
     if (pVCpu->pgm.s.enmGuestSlatMode == PGMSLAT_EPT)
@@ -385 +381 @@
         if (RT_SUCCESS(rc))
         {
+            RT_ZERO(*pWalk);
             pWalk->fSucceeded = true;
             pWalk->GCPtr      = GCPtr;
@@ -399 +396 @@
      * Fake it.
      */
+    RT_ZERO(*pWalk);
     pWalk->fSucceeded = true;
     pWalk->GCPtr      = GCPtr;
@@ -427 +425 @@
                  ;
     else
-    {
         fFlags = (GstWalk.Pde.u & ~(GST_PTE_PG_MASK | X86_PDE4M_RW | X86_PDE4M_US | X86_PDE4M_PS))   /* NX not needed */
                | (pWalk->fEffective & (PGM_PTATTRS_W_MASK | PGM_PTATTRS_US_MASK | PGM_PTATTRS_PAT_MASK))
@@ -434 +431 @@
 # endif
                ;
-    }
 
     pWalk->GCPhys    &= ~(RTGCPHYS)GUEST_PAGE_OFFSET_MASK;

trunk/src/VBox/VMM/VMMR3/IOMR3Mmio.cpp

@@ -355 +355 @@
  * Worker for PDMDEVHLPR3::pfnMmioMap.
  */
-VMMR3_INT_DECL(int)  IOMR3MmioMap(PVM pVM, PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion, RTGCPHYS GCPhys)
+VMMR3_INT_DECL(int)  IOMR3MmioMap(PVM pVM, PVMCPU pVCpu, PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion, RTGCPHYS GCPhys)
 {
     /*
      * Validate input and state.
      */
+    VMCPU_ASSERT_EMT_RETURN(pVCpu, VERR_VM_THREAD_NOT_EMT);
     AssertPtrReturn(pDevIns, VERR_INVALID_HANDLE);
     AssertReturn(hRegion < pVM->iom.s.cMmioRegs, VERR_IOM_INVALID_MMIO_HANDLE);
@@ -408 +409 @@
                         /* Register with PGM before we shuffle the array: */
                         ASMAtomicWriteU64(&pRegEntry->GCPhysMapping, GCPhys);
-                        rc = PGMR3PhysMMIORegister(pVM, GCPhys, cbRegion, pVM->iom.s.hNewMmioHandlerType,
+                        rc = PGMR3PhysMmioRegister(pVM, pVCpu, GCPhys, cbRegion, pVM->iom.s.hNewMmioHandlerType,
                                                    hRegion, pRegEntry->pszDesc);
                         AssertRCReturnStmt(rc, ASMAtomicWriteU64(&pRegEntry->GCPhysMapping, NIL_RTGCPHYS); IOM_UNLOCK_EXCL(pVM), rc);
@@ -427 +428 @@
                         /* Register with PGM before we shuffle the array: */
                         ASMAtomicWriteU64(&pRegEntry->GCPhysMapping, GCPhys);
-                        rc = PGMR3PhysMMIORegister(pVM, GCPhys, cbRegion, pVM->iom.s.hNewMmioHandlerType,
+                        rc = PGMR3PhysMmioRegister(pVM, pVCpu, GCPhys, cbRegion, pVM->iom.s.hNewMmioHandlerType,
                                                    hRegion, pRegEntry->pszDesc);
                         AssertRCReturnStmt(rc, ASMAtomicWriteU64(&pRegEntry->GCPhysMapping, NIL_RTGCPHYS); IOM_UNLOCK_EXCL(pVM), rc);
@@ -454 +455 @@
             /* First entry in the lookup table: */
             ASMAtomicWriteU64(&pRegEntry->GCPhysMapping, GCPhys);
-            rc = PGMR3PhysMMIORegister(pVM, GCPhys, cbRegion, pVM->iom.s.hNewMmioHandlerType, hRegion, pRegEntry->pszDesc);
+            rc = PGMR3PhysMmioRegister(pVM, pVCpu, GCPhys, cbRegion, pVM->iom.s.hNewMmioHandlerType, hRegion, pRegEntry->pszDesc);
             AssertRCReturnStmt(rc, ASMAtomicWriteU64(&pRegEntry->GCPhysMapping, NIL_RTGCPHYS); IOM_UNLOCK_EXCL(pVM), rc);
 
@@ -507 +508 @@
  * Worker for PDMDEVHLPR3::pfnMmioUnmap.
  */
-VMMR3_INT_DECL(int)  IOMR3MmioUnmap(PVM pVM, PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion)
+VMMR3_INT_DECL(int) IOMR3MmioUnmap(PVM pVM, PVMCPU pVCpu, PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion)
 {
     /*
      * Validate input and state.
      */
+    VMCPU_ASSERT_EMT_RETURN(pVCpu, VERR_VM_THREAD_NOT_EMT);
     AssertPtrReturn(pDevIns, VERR_INVALID_HANDLE);
     AssertReturn(hRegion < pVM->iom.s.cMmioRegs, VERR_IOM_INVALID_MMIO_HANDLE);
@@ -570 +572 @@
                 pVM->iom.s.cMmioLookupEntries = cEntries - 1;
 
-                rc = PGMR3PhysMMIODeregister(pVM, GCPhys, pRegEntry->cbRegion);
+                rc = PGMR3PhysMmioDeregister(pVM, pVCpu, GCPhys, pRegEntry->cbRegion);
                 AssertRC(rc);
 

trunk/src/VBox/VMM/VMMR3/PDMDevHlp.cpp

@@ -218 +218 @@
     PDMDEV_ASSERT_DEVINS(pDevIns);
     LogFlow(("pdmR3DevHlp_MmioMap: caller='%s'/%d: hRegion=%#x GCPhys=%#RGp\n", pDevIns->pReg->szName, pDevIns->iInstance, hRegion, GCPhys));
-    PVM pVM = pDevIns->Internal.s.pVMR3;
-    VM_ASSERT_EMT_RETURN(pVM, VERR_VM_THREAD_NOT_EMT);
-
-    int rc = IOMR3MmioMap(pVM, pDevIns, hRegion, GCPhys);
+
+    PVM    const pVM   = pDevIns->Internal.s.pVMR3;
+    PVMCPU const pVCpu = VMMGetCpu(pVM);
+    AssertReturn(pVCpu, VERR_VM_THREAD_NOT_EMT);
+
+    int rc = IOMR3MmioMap(pVM, pVCpu, pDevIns, hRegion, GCPhys);
 
     LogFlow(("pdmR3DevHlp_MmioMap: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
@@ -233 +235 @@
     PDMDEV_ASSERT_DEVINS(pDevIns);
     LogFlow(("pdmR3DevHlp_MmioUnmap: caller='%s'/%d: hRegion=%#x\n", pDevIns->pReg->szName, pDevIns->iInstance, hRegion));
-    PVM pVM = pDevIns->Internal.s.pVMR3;
-    VM_ASSERT_EMT_RETURN(pVM, VERR_VM_THREAD_NOT_EMT);
-
-    int rc = IOMR3MmioUnmap(pVM, pDevIns, hRegion);
+
+    PVM    const pVM   = pDevIns->Internal.s.pVMR3;
+    PVMCPU const pVCpu = VMMGetCpu(pVM);
+    AssertReturn(pVCpu, VERR_VM_THREAD_NOT_EMT);
+
+    int rc = IOMR3MmioUnmap(pVM, pVCpu, pDevIns, hRegion);
 
     LogFlow(("pdmR3DevHlp_MmioUnmap: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));

trunk/src/VBox/VMM/VMMR3/PDMDevHlpTracing.cpp

@@ -306 +306 @@
     PDMDEV_ASSERT_DEVINS(pDevIns);
     LogFlow(("pdmR3DevHlp_MmioMap: caller='%s'/%d: hRegion=%#x GCPhys=%#RGp\n", pDevIns->pReg->szName, pDevIns->iInstance, hRegion, GCPhys));
-    PVM pVM = pDevIns->Internal.s.pVMR3;
-    VM_ASSERT_EMT_RETURN(pVM, VERR_VM_THREAD_NOT_EMT);
-
-    int rc = IOMR3MmioMap(pVM, pDevIns, hRegion, GCPhys);
+
+    PVM    const pVM   = pDevIns->Internal.s.pVMR3;
+    PVMCPU const pVCpu = VMMGetCpu(pVM);
+    AssertReturn(pVCpu, VERR_VM_THREAD_NOT_EMT);
+
+    int rc = IOMR3MmioMap(pVM, pVCpu, pDevIns, hRegion, GCPhys);
     DBGFTracerEvtMmioMap(pVM, pDevIns->Internal.s.hDbgfTraceEvtSrc, hRegion, GCPhys);
 
@@ -322 +324 @@
     PDMDEV_ASSERT_DEVINS(pDevIns);
     LogFlow(("pdmR3DevHlp_MmioUnmap: caller='%s'/%d: hRegion=%#x\n", pDevIns->pReg->szName, pDevIns->iInstance, hRegion));
-    PVM pVM = pDevIns->Internal.s.pVMR3;
-    VM_ASSERT_EMT_RETURN(pVM, VERR_VM_THREAD_NOT_EMT);
-
-    int rc = IOMR3MmioUnmap(pVM, pDevIns, hRegion);
+
+    PVM    const pVM   = pDevIns->Internal.s.pVMR3;
+    PVMCPU const pVCpu = VMMGetCpu(pVM);
+    AssertReturn(pVCpu, VERR_VM_THREAD_NOT_EMT);
+
+    int rc = IOMR3MmioUnmap(pVM, pVCpu, pDevIns, hRegion);
     DBGFTracerEvtMmioUnmap(pVM, pDevIns->Internal.s.hDbgfTraceEvtSrc, hRegion);
 

trunk/src/VBox/VMM/VMMR3/PGMPhys.cpp

@@ -2276 +2276 @@
  *
  * @param   pVM             The cross context VM structure.
+ * @param   pVCpu           The cross context virtual CPU structure of the calling EMT.
  * @param   GCPhys          The start of the MMIO region.
  * @param   cb              The size of the MMIO region.
@@ -2281 +2282 @@
  * @param   uUser           The user argument.
  * @param   pszDesc         The description of the MMIO region.
- */
-VMMR3DECL(int) PGMR3PhysMMIORegister(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb, PGMPHYSHANDLERTYPE hType,
-                                     uint64_t uUser, const char *pszDesc)
+ * @thread  EMT(pVCpu)
+ */
+VMMR3_INT_DECL(int) PGMR3PhysMmioRegister(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys, RTGCPHYS cb, PGMPHYSHANDLERTYPE hType,
+                                          uint64_t uUser, const char *pszDesc)
 {
     /*
      * Assert on some assumption.
      */
-    VM_ASSERT_EMT(pVM);
+    VMCPU_ASSERT_EMT(pVCpu);
     AssertReturn(!(cb & GUEST_PAGE_OFFSET_MASK), VERR_INVALID_PARAMETER);
     AssertReturn(!(GCPhys & GUEST_PAGE_OFFSET_MASK), VERR_INVALID_PARAMETER);
@@ -2363 +2365 @@
          *   care of this internally (not touch mapped mmio while changing the
          *   mapping). */
-        PVMCPU pVCpu = VMMGetCpu(pVM);
         pVCpu->pgm.s.fSyncFlags |= PGM_SYNC_CLEAR_PGM_POOL;
         VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
@@ -2375 +2376 @@
          * PGMHandlerPhysicalRegisterEx will do that for us.
          */
-        Log(("PGMR3PhysMMIORegister: Adding ad hoc MMIO range for %RGp-%RGp %s\n", GCPhys, GCPhysLast, pszDesc));
+        Log(("PGMR3PhysMmioRegister: Adding ad hoc MMIO range for %RGp-%RGp %s\n", GCPhys, GCPhysLast, pszDesc));
 
         /* Alloc. */
@@ -2469 +2470 @@
  * @returns VBox status code.
  * @param   pVM             The cross context VM structure.
+ * @param   pVCpu           The cross context virtual CPU structure of the calling EMT.
  * @param   GCPhys          The start of the MMIO region.
  * @param   cb              The size of the MMIO region.
- */
-VMMR3DECL(int) PGMR3PhysMMIODeregister(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb)
-{
-    VM_ASSERT_EMT(pVM);
+ * @thread  EMT(pVCpu)
+ */
+VMMR3_INT_DECL(int) PGMR3PhysMmioDeregister(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys, RTGCPHYS cb)
+{
+    VMCPU_ASSERT_EMT(pVCpu);
 
     int rc = PGM_LOCK(pVM);
@@ -2523 +2526 @@
                      * Ad-hoc range, unlink and free it.
                      */
-                    Log(("PGMR3PhysMMIODeregister: Freeing ad hoc MMIO range for %RGp-%RGp %s\n",
+                    Log(("PGMR3PhysMmioDeregister: Freeing ad hoc MMIO range for %RGp-%RGp %s\n",
                          GCPhys, GCPhysLast, pRam->pszDesc));
                     /** @todo check the ad-hoc flags? */
@@ -2600 +2603 @@
     /** @todo Not entirely SMP safe; assuming for now the guest takes care of
      *       this internally (not touch mapped mmio while changing the mapping). */
-    PVMCPU pVCpu = VMMGetCpu(pVM);
     pVCpu->pgm.s.fSyncFlags |= PGM_SYNC_CLEAR_PGM_POOL;
     VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);