Changeset 104767 in vbox for trunk/src/VBox/VMM/VMMR3
- Timestamp:
- May 23, 2024 12:03:04 PM (8 months ago)
- Location:
- trunk/src/VBox/VMM/VMMR3
- Files:
-
- 4 edited
Legend:
- Unmodified
- Added
- Removed
-
trunk/src/VBox/VMM/VMMR3/IOMR3Mmio.cpp
r98103 r104767 355 355 * Worker for PDMDEVHLPR3::pfnMmioMap. 356 356 */ 357 VMMR3_INT_DECL(int) IOMR3MmioMap(PVM pVM, P PDMDEVINS pDevIns, IOMMMIOHANDLE hRegion, RTGCPHYS GCPhys)357 VMMR3_INT_DECL(int) IOMR3MmioMap(PVM pVM, PVMCPU pVCpu, PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion, RTGCPHYS GCPhys) 358 358 { 359 359 /* 360 360 * Validate input and state. 361 361 */ 362 VMCPU_ASSERT_EMT_RETURN(pVCpu, VERR_VM_THREAD_NOT_EMT); 362 363 AssertPtrReturn(pDevIns, VERR_INVALID_HANDLE); 363 364 AssertReturn(hRegion < pVM->iom.s.cMmioRegs, VERR_IOM_INVALID_MMIO_HANDLE); … … 408 409 /* Register with PGM before we shuffle the array: */ 409 410 ASMAtomicWriteU64(&pRegEntry->GCPhysMapping, GCPhys); 410 rc = PGMR3PhysM MIORegister(pVM, GCPhys, cbRegion, pVM->iom.s.hNewMmioHandlerType,411 rc = PGMR3PhysMmioRegister(pVM, pVCpu, GCPhys, cbRegion, pVM->iom.s.hNewMmioHandlerType, 411 412 hRegion, pRegEntry->pszDesc); 412 413 AssertRCReturnStmt(rc, ASMAtomicWriteU64(&pRegEntry->GCPhysMapping, NIL_RTGCPHYS); IOM_UNLOCK_EXCL(pVM), rc); … … 427 428 /* Register with PGM before we shuffle the array: */ 428 429 ASMAtomicWriteU64(&pRegEntry->GCPhysMapping, GCPhys); 429 rc = PGMR3PhysM MIORegister(pVM, GCPhys, cbRegion, pVM->iom.s.hNewMmioHandlerType,430 rc = PGMR3PhysMmioRegister(pVM, pVCpu, GCPhys, cbRegion, pVM->iom.s.hNewMmioHandlerType, 430 431 hRegion, pRegEntry->pszDesc); 431 432 AssertRCReturnStmt(rc, ASMAtomicWriteU64(&pRegEntry->GCPhysMapping, NIL_RTGCPHYS); IOM_UNLOCK_EXCL(pVM), rc); … … 454 455 /* First entry in the lookup table: */ 455 456 ASMAtomicWriteU64(&pRegEntry->GCPhysMapping, GCPhys); 456 rc = PGMR3PhysM MIORegister(pVM, GCPhys, cbRegion, pVM->iom.s.hNewMmioHandlerType, hRegion, pRegEntry->pszDesc);457 rc = PGMR3PhysMmioRegister(pVM, pVCpu, GCPhys, cbRegion, pVM->iom.s.hNewMmioHandlerType, hRegion, pRegEntry->pszDesc); 457 458 AssertRCReturnStmt(rc, ASMAtomicWriteU64(&pRegEntry->GCPhysMapping, NIL_RTGCPHYS); IOM_UNLOCK_EXCL(pVM), rc); 458 459 … … 507 508 * Worker for PDMDEVHLPR3::pfnMmioUnmap. 508 509 */ 509 VMMR3_INT_DECL(int) IOMR3MmioUnmap(PVM pVM, PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion)510 VMMR3_INT_DECL(int) IOMR3MmioUnmap(PVM pVM, PVMCPU pVCpu, PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion) 510 511 { 511 512 /* 512 513 * Validate input and state. 513 514 */ 515 VMCPU_ASSERT_EMT_RETURN(pVCpu, VERR_VM_THREAD_NOT_EMT); 514 516 AssertPtrReturn(pDevIns, VERR_INVALID_HANDLE); 515 517 AssertReturn(hRegion < pVM->iom.s.cMmioRegs, VERR_IOM_INVALID_MMIO_HANDLE); … … 570 572 pVM->iom.s.cMmioLookupEntries = cEntries - 1; 571 573 572 rc = PGMR3PhysM MIODeregister(pVM, GCPhys, pRegEntry->cbRegion);574 rc = PGMR3PhysMmioDeregister(pVM, pVCpu, GCPhys, pRegEntry->cbRegion); 573 575 AssertRC(rc); 574 576 -
trunk/src/VBox/VMM/VMMR3/PDMDevHlp.cpp
r100399 r104767 218 218 PDMDEV_ASSERT_DEVINS(pDevIns); 219 219 LogFlow(("pdmR3DevHlp_MmioMap: caller='%s'/%d: hRegion=%#x GCPhys=%#RGp\n", pDevIns->pReg->szName, pDevIns->iInstance, hRegion, GCPhys)); 220 PVM pVM = pDevIns->Internal.s.pVMR3; 221 VM_ASSERT_EMT_RETURN(pVM, VERR_VM_THREAD_NOT_EMT); 222 223 int rc = IOMR3MmioMap(pVM, pDevIns, hRegion, GCPhys); 220 221 PVM const pVM = pDevIns->Internal.s.pVMR3; 222 PVMCPU const pVCpu = VMMGetCpu(pVM); 223 AssertReturn(pVCpu, VERR_VM_THREAD_NOT_EMT); 224 225 int rc = IOMR3MmioMap(pVM, pVCpu, pDevIns, hRegion, GCPhys); 224 226 225 227 LogFlow(("pdmR3DevHlp_MmioMap: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc)); … … 233 235 PDMDEV_ASSERT_DEVINS(pDevIns); 234 236 LogFlow(("pdmR3DevHlp_MmioUnmap: caller='%s'/%d: hRegion=%#x\n", pDevIns->pReg->szName, pDevIns->iInstance, hRegion)); 235 PVM pVM = pDevIns->Internal.s.pVMR3; 236 VM_ASSERT_EMT_RETURN(pVM, VERR_VM_THREAD_NOT_EMT); 237 238 int rc = IOMR3MmioUnmap(pVM, pDevIns, hRegion); 237 238 PVM const pVM = pDevIns->Internal.s.pVMR3; 239 PVMCPU const pVCpu = VMMGetCpu(pVM); 240 AssertReturn(pVCpu, VERR_VM_THREAD_NOT_EMT); 241 242 int rc = IOMR3MmioUnmap(pVM, pVCpu, pDevIns, hRegion); 239 243 240 244 LogFlow(("pdmR3DevHlp_MmioUnmap: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc)); -
trunk/src/VBox/VMM/VMMR3/PDMDevHlpTracing.cpp
r98103 r104767 306 306 PDMDEV_ASSERT_DEVINS(pDevIns); 307 307 LogFlow(("pdmR3DevHlp_MmioMap: caller='%s'/%d: hRegion=%#x GCPhys=%#RGp\n", pDevIns->pReg->szName, pDevIns->iInstance, hRegion, GCPhys)); 308 PVM pVM = pDevIns->Internal.s.pVMR3; 309 VM_ASSERT_EMT_RETURN(pVM, VERR_VM_THREAD_NOT_EMT); 310 311 int rc = IOMR3MmioMap(pVM, pDevIns, hRegion, GCPhys); 308 309 PVM const pVM = pDevIns->Internal.s.pVMR3; 310 PVMCPU const pVCpu = VMMGetCpu(pVM); 311 AssertReturn(pVCpu, VERR_VM_THREAD_NOT_EMT); 312 313 int rc = IOMR3MmioMap(pVM, pVCpu, pDevIns, hRegion, GCPhys); 312 314 DBGFTracerEvtMmioMap(pVM, pDevIns->Internal.s.hDbgfTraceEvtSrc, hRegion, GCPhys); 313 315 … … 322 324 PDMDEV_ASSERT_DEVINS(pDevIns); 323 325 LogFlow(("pdmR3DevHlp_MmioUnmap: caller='%s'/%d: hRegion=%#x\n", pDevIns->pReg->szName, pDevIns->iInstance, hRegion)); 324 PVM pVM = pDevIns->Internal.s.pVMR3; 325 VM_ASSERT_EMT_RETURN(pVM, VERR_VM_THREAD_NOT_EMT); 326 327 int rc = IOMR3MmioUnmap(pVM, pDevIns, hRegion); 326 327 PVM const pVM = pDevIns->Internal.s.pVMR3; 328 PVMCPU const pVCpu = VMMGetCpu(pVM); 329 AssertReturn(pVCpu, VERR_VM_THREAD_NOT_EMT); 330 331 int rc = IOMR3MmioUnmap(pVM, pVCpu, pDevIns, hRegion); 328 332 DBGFTracerEvtMmioUnmap(pVM, pDevIns->Internal.s.hDbgfTraceEvtSrc, hRegion); 329 333 -
trunk/src/VBox/VMM/VMMR3/PGMPhys.cpp
r103299 r104767 2276 2276 * 2277 2277 * @param pVM The cross context VM structure. 2278 * @param pVCpu The cross context virtual CPU structure of the calling EMT. 2278 2279 * @param GCPhys The start of the MMIO region. 2279 2280 * @param cb The size of the MMIO region. … … 2281 2282 * @param uUser The user argument. 2282 2283 * @param pszDesc The description of the MMIO region. 2283 */ 2284 VMMR3DECL(int) PGMR3PhysMMIORegister(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb, PGMPHYSHANDLERTYPE hType, 2285 uint64_t uUser, const char *pszDesc) 2284 * @thread EMT(pVCpu) 2285 */ 2286 VMMR3_INT_DECL(int) PGMR3PhysMmioRegister(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys, RTGCPHYS cb, PGMPHYSHANDLERTYPE hType, 2287 uint64_t uUser, const char *pszDesc) 2286 2288 { 2287 2289 /* 2288 2290 * Assert on some assumption. 2289 2291 */ 2290 VM _ASSERT_EMT(pVM);2292 VMCPU_ASSERT_EMT(pVCpu); 2291 2293 AssertReturn(!(cb & GUEST_PAGE_OFFSET_MASK), VERR_INVALID_PARAMETER); 2292 2294 AssertReturn(!(GCPhys & GUEST_PAGE_OFFSET_MASK), VERR_INVALID_PARAMETER); … … 2363 2365 * care of this internally (not touch mapped mmio while changing the 2364 2366 * mapping). */ 2365 PVMCPU pVCpu = VMMGetCpu(pVM);2366 2367 pVCpu->pgm.s.fSyncFlags |= PGM_SYNC_CLEAR_PGM_POOL; 2367 2368 VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3); … … 2375 2376 * PGMHandlerPhysicalRegisterEx will do that for us. 2376 2377 */ 2377 Log(("PGMR3PhysM MIORegister: Adding ad hoc MMIO range for %RGp-%RGp %s\n", GCPhys, GCPhysLast, pszDesc));2378 Log(("PGMR3PhysMmioRegister: Adding ad hoc MMIO range for %RGp-%RGp %s\n", GCPhys, GCPhysLast, pszDesc)); 2378 2379 2379 2380 /* Alloc. */ … … 2469 2470 * @returns VBox status code. 2470 2471 * @param pVM The cross context VM structure. 2472 * @param pVCpu The cross context virtual CPU structure of the calling EMT. 2471 2473 * @param GCPhys The start of the MMIO region. 2472 2474 * @param cb The size of the MMIO region. 2473 */ 2474 VMMR3DECL(int) PGMR3PhysMMIODeregister(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb) 2475 { 2476 VM_ASSERT_EMT(pVM); 2475 * @thread EMT(pVCpu) 2476 */ 2477 VMMR3_INT_DECL(int) PGMR3PhysMmioDeregister(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys, RTGCPHYS cb) 2478 { 2479 VMCPU_ASSERT_EMT(pVCpu); 2477 2480 2478 2481 int rc = PGM_LOCK(pVM); … … 2523 2526 * Ad-hoc range, unlink and free it. 2524 2527 */ 2525 Log(("PGMR3PhysM MIODeregister: Freeing ad hoc MMIO range for %RGp-%RGp %s\n",2528 Log(("PGMR3PhysMmioDeregister: Freeing ad hoc MMIO range for %RGp-%RGp %s\n", 2526 2529 GCPhys, GCPhysLast, pRam->pszDesc)); 2527 2530 /** @todo check the ad-hoc flags? */ … … 2600 2603 /** @todo Not entirely SMP safe; assuming for now the guest takes care of 2601 2604 * this internally (not touch mapped mmio while changing the mapping). */ 2602 PVMCPU pVCpu = VMMGetCpu(pVM);2603 2605 pVCpu->pgm.s.fSyncFlags |= PGM_SYNC_CLEAR_PGM_POOL; 2604 2606 VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
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