Changeset 10489 in vbox for trunk/src/VBox

Timestamp:

Jul 11, 2008 7:17:00 AM (16 years ago)

Author:

vboxsync

Message:

AMD-V: Always flush the TLB the first time a cpu is used.

Location:

trunk/src/VBox/VMM

Files:

• HWACCMInternal.h (modified) (1 diff)
• VMMR0/HWACCMR0.cpp (modified) (1 diff)
• VMMR0/HWSVMR0.cpp (modified) (2 diffs)

trunk/src/VBox/VMM/HWACCMInternal.h

@@ -138 +138 @@
     /* TLB flush count */
     uint32_t    cTLBFlushes;
+
+    /* Set the first time a cpu is used to make sure we start with a clean TLB. */
+    bool        fFlushTLB;
 
     bool        fConfigured;

trunk/src/VBox/VMM/VMMR0/HWACCMR0.cpp

@@ -574 +574 @@
     Assert(idCpu < RT_ELEMENTS(HWACCMR0Globals.aCpuInfo));
 
-    pCpu->idCpu = idCpu;
+    pCpu->idCpu     = idCpu;
+
+    /* Make sure we start with a clean TLB. */
+    pCpu->fFlushTLB = true;
 
     /* Should never happen */

trunk/src/VBox/VMM/VMMR0/HWSVMR0.cpp

@@ -894 +894 @@
         && !pVM->hwaccm.s.svm.fAlwaysFlushTLB)
     {
-        if (++pCpu->uCurrentASID >= pVM->hwaccm.s.svm.u32MaxASID)
-        {
+        if (    ++pCpu->uCurrentASID >= pVM->hwaccm.s.svm.u32MaxASID
+            ||  pCpu->fFlushTLB)
+        {
+            pCpu->fFlushTLB                  = false;
             pCpu->uCurrentASID               = 1;       /* start at 1; host uses 0 */
             pVMCB->ctrl.TLBCtrl.n.u1TLBFlush = 1;       /* wrap around; flush TLB */
@@ -907 +909 @@
     else
     {
+        Assert(!pCpu->fFlushTLB || pVM->hwaccm.s.svm.fAlwaysFlushTLB);
+
         /* We never increase uCurrentASID in the fAlwaysFlushTLB (erratum 170) case. */
         if (!pCpu->uCurrentASID)