Changeset 104935 in vbox for trunk/src/VBox/VMM

Timestamp:

Jun 15, 2024 1:40:08 AM (8 months ago)

Author:

vboxsync

Message:

VMM/PGM: Lockless pgmPhysGCPhys2R3Ptr variant for use in PGMGstQueryPage. bugref:10687

Location:

trunk/src/VBox/VMM

Files:

• VMMAll/PGMAllGst.h (modified) (3 diffs)
• VMMAll/PGMAllPhys.cpp (modified) (2 diffs)
• include/PGMInternal.h (modified) (1 diff)

trunk/src/VBox/VMM/VMMAll/PGMAllGst.h

@@ -643 +643 @@
         RTGCPHYS GCPhysPdpt = Pml4e.u & X86_PML4E_PG_MASK;
         PGM_GST_SLAT_WALK_FAST(pVCpu, GCPtr, GCPhysPdpt, false /*a_fFinal*/, GCPhysPdpt, pWalk);
-        rc = PGM_GCPHYS_2_PTR_BY_VMCPU(pVCpu, GCPhysPdpt, &pGstWalk->pPdpt);
+        rc = pgmPhysGCPhys2CCPtrLockless(pVCpu, GCPhysPdpt, (void **)&pGstWalk->pPdpt);
         if (RT_SUCCESS(rc)) { /* probable */ }
         else return PGM_GST_NAME(WalkFastReturnBadPhysAddr)(pVCpu, pWalk, 3, rc);
@@ -687 +687 @@
         RTGCPHYS GCPhysPd = Pdpe.u & X86_PDPE_PG_MASK;
         PGM_GST_SLAT_WALK_FAST(pVCpu, GCPtr, GCPhysPd, false /*a_fFinal*/, GCPhysPd, pWalk);
-        rc = PGM_GCPHYS_2_PTR_BY_VMCPU(pVCpu, GCPhysPd, &pGstWalk->pPd);
+        rc = pgmPhysGCPhys2CCPtrLockless(pVCpu, GCPhysPd, (void **)&pGstWalk->pPd);
         if (RT_SUCCESS(rc)) { /* probable */ }
         else return PGM_GST_NAME(WalkFastReturnBadPhysAddr)(pVCpu, pWalk, 2, rc);
@@ -791 +791 @@
         RTGCPHYS GCPhysPt = GST_GET_PDE_GCPHYS(Pde);
         PGM_GST_SLAT_WALK_FAST(pVCpu, GCPtr, GCPhysPt, false /*a_fFinal*/, GCPhysPt, pWalk);
-        rc = PGM_GCPHYS_2_PTR_BY_VMCPU(pVCpu, GCPhysPt, &pGstWalk->pPt);
+        rc = pgmPhysGCPhys2CCPtrLockless(pVCpu, GCPhysPt, (void **)&pGstWalk->pPt);
         if (RT_SUCCESS(rc)) { /* probable */ }
         else return PGM_GST_NAME(WalkFastReturnBadPhysAddr)(pVCpu, pWalk, 1, rc);

trunk/src/VBox/VMM/VMMAll/PGMAllPhys.cpp

@@ -3691 +3691 @@
 
     PGM_UNLOCK(pVM);
+    Assert(rc <= VINF_SUCCESS);
+    return rc;
+}
+
+
+/**
+ * Special lockless guest physical to current context pointer convertor.
+ *
+ * This is mainly for the page table walking and such.
+ */
+int pgmPhysGCPhys2CCPtrLockless(PVMCPUCC pVCpu, RTGCPHYS GCPhys, void **ppv)
+{
+    VMCPU_ASSERT_EMT(pVCpu);
+
+    /*
+     * Get the RAM range and page structure.
+     */
+    PVMCC const           pVM = pVCpu->CTX_SUFF(pVM);
+    PGMRAMRANGE volatile *pRam;
+    PGMPAGE volatile     *pPage;
+    int rc = pgmPhysGetPageAndRangeExLockless(pVM, pVCpu, GCPhys, &pPage, &pRam);
+    if (RT_SUCCESS(rc))
+    {
+        /*
+         * Now, make sure it's writable (typically it is).
+         */
+        if (RT_LIKELY(PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_ALLOCATED))
+        { /* likely, typically */ }
+        else
+        {
+            PGM_LOCK_VOID(pVM);
+            rc = pgmPhysPageMakeWritable(pVM, (PPGMPAGE)pPage, GCPhys);
+            if (RT_SUCCESS(rc))
+                rc = pgmPhysGetPageAndRangeExLockless(pVM, pVCpu, GCPhys, &pPage, &pRam);
+            PGM_UNLOCK(pVM);
+            if (RT_FAILURE(rc))
+                return rc;
+            AssertMsg(rc == VINF_SUCCESS || rc == VINF_PGM_SYNC_CR3 /* not returned */, ("%Rrc\n", rc));
+        }
+        Assert(PGM_PAGE_GET_HCPHYS(pPage) != 0);
+
+        /*
+         * Get the mapping address.
+         */
+        uint8_t *pb;
+#ifdef IN_RING3
+        if (PGM_IS_IN_NEM_MODE(pVM))
+            pb = &pRam->pbR3[(RTGCPHYS)(uintptr_t)(pPage - &pRam->aPages[0]) << GUEST_PAGE_SHIFT];
+        else
+#endif
+        {
+#ifdef IN_RING3
+            PPGMPAGEMAPTLBE pTlbe;
+            rc = pgmPhysPageQueryLocklessTlbeWithPage(pVCpu, (PPGMPAGE)pPage, GCPhys, &pTlbe);
+            AssertLogRelRCReturn(rc, rc);
+            pb = (uint8_t *)pTlbe->pv;
+            RT_NOREF(pVM);
+#else /** @todo a safe lockless page TLB in ring-0 needs the to ensure it gets the right invalidations. later. */
+            PGM_LOCK(pVM);
+            PPGMPAGEMAPTLBE pTlbe;
+            rc = pgmPhysPageQueryTlbeWithPage(pVM, (PPGMPAGE)pPage, GCPhys, &pTlbe);
+            AssertLogRelRCReturnStmt(rc, PGM_UNLOCK(pVM), rc);
+            pb = (uint8_t *)pTlbe->pv;
+            PGM_UNLOCK(pVM);
+            RT_NOREF(pVCpu);
+#endif
+        }
+        *ppv = (void *)((uintptr_t)pb | (uintptr_t)(GCPhys & GUEST_PAGE_OFFSET_MASK));
+        return VINF_SUCCESS;
+    }
     Assert(rc <= VINF_SUCCESS);
     return rc;
@@ -5435 +5505 @@
  * @param   pvUser          User argument to pass to pfnChecker.
  */
-VMM_INT_DECL(int) PGMPhysNemPageInfoChecker(PVMCC pVM, PVMCPUCC pVCpu, RTGCPHYS GCPhys, bool fMakeWritable, PPGMPHYSNEMPAGEINFO pInfo,
-                                            PFNPGMPHYSNEMCHECKPAGE pfnChecker, void *pvUser)
+VMM_INT_DECL(int) PGMPhysNemPageInfoChecker(PVMCC pVM, PVMCPUCC pVCpu, RTGCPHYS GCPhys, bool fMakeWritable,
+                                            PPGMPHYSNEMPAGEINFO pInfo, PFNPGMPHYSNEMCHECKPAGE pfnChecker, void *pvUser)
 {
     PGM_LOCK_VOID(pVM);

trunk/src/VBox/VMM/include/PGMInternal.h

@@ -3906 +3906 @@
 int             pgmPhysPageMapByPageID(PVMCC pVM, uint32_t idPage, RTHCPHYS HCPhys, void **ppv);
 int             pgmPhysGCPhys2R3Ptr(PVMCC pVM, RTGCPHYS GCPhys, PRTR3PTR pR3Ptr);
+int             pgmPhysGCPhys2CCPtrLockless(PVMCPUCC pVCpu, RTGCPHYS GCPhys, void **ppv);
 int             pgmPhysCr3ToHCPtr(PVM pVM, RTGCPHYS GCPhys, PRTR3PTR pR3Ptr);
 int             pgmPhysGCPhys2CCPtrInternalDepr(PVMCC pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void **ppv);