Changeset 104947 in vbox for trunk/src/VBox/VMM/include

Timestamp:

Jun 17, 2024 8:23:40 PM (5 months ago)

Author:

vboxsync

Message:

VMM/IEM,tstVMStructSize: Made the IEM TLB size more easily configurable. Include the IEM statistics in the tstVMStructSize testcase so it can be run to figure out the correct paddings. bugref:10687

Location:

trunk/src/VBox/VMM/include

Files:

• IEMInternal.h (modified) (5 diffs)
• IEMN8veRecompilerTlbLookup.h (modified) (3 diffs)

trunk/src/VBox/VMM/include/IEMInternal.h

@@ -261 +261 @@
 #ifndef RT_IN_ASSEMBLER /* ASM-NOINC-START - the rest of the file */
 
-# if !defined(IN_TSTVMSTRUCT) && !defined(DOXYGEN_RUNNING)
+# if !defined(IEM_WITHOUT_INSTRUCTION_STATS) && !defined(DOXYGEN_RUNNING)
 /** Instruction statistics.   */
 typedef struct IEMINSTRSTATS
@@ -517 +517 @@
                                      | IEMTLBE_F_PHYS_REV )
 
+/** The TLB size (power of two).
+ * We initially chose 256 because that way we can obtain the result directly
+ * from a 8-bit register without an additional AND instruction.
+ * See also @bugref{10687}. */
+#define IEMTLB_ENTRY_COUNT                      256
+#define IEMTLB_ENTRY_COUNT_AS_POWER_OF_TWO      8
+AssertCompile(RT_BIT_32(IEMTLB_ENTRY_COUNT_AS_POWER_OF_TWO) == IEMTLB_ENTRY_COUNT);
 
 /**
@@ -572 +579 @@
     uint32_t            au32Padding[6];
 
-    /** The TLB entries.
-     * We've choosen 256 because that way we can obtain the result directly from a
-     * 8-bit register without an additional AND instruction. */
-    IEMTLBENTRY         aEntries[256];
+    /** The TLB entries. */
+    IEMTLBENTRY         aEntries[IEMTLB_ENTRY_COUNT];
 } IEMTLB;
 AssertCompileSizeAlignment(IEMTLB, 64);
@@ -607 +612 @@
  * @param   a_uTag      Value returned by IEMTLB_CALC_TAG.
  */
-#define IEMTLB_TAG_TO_INDEX(a_uTag)         ( (uint8_t)(a_uTag) )
+#if IEMTLB_ENTRY_COUNT == 256
+# define IEMTLB_TAG_TO_INDEX(a_uTag)        ( (uint8_t)(a_uTag) )
+#else
+# define IEMTLB_TAG_TO_INDEX(a_uTag)        ( (a_uTag) & (IEMTLB_ENTRY_COUNT - 1U) )
+AssertCompile(RT_IS_POWER_OF_TWO(IEMTLB_ENTRY_COUNT));
+#endif
 /**
  * Converts a TLB tag value into a TLB index.
@@ -2164 +2174 @@
     uint32_t                aStatInts[256];
 
-#if defined(VBOX_WITH_STATISTICS) && !defined(IN_TSTVMSTRUCT) && !defined(DOXYGEN_RUNNING)
+#if defined(VBOX_WITH_STATISTICS) && !defined(DOXYGEN_RUNNING) && !defined(IEM_WITHOUT_INSTRUCTION_STATS)
     /** Instruction statistics for ring-0/raw-mode. */
     IEMINSTRSTATS           StatsRZ;

trunk/src/VBox/VMM/include/IEMN8veRecompilerTlbLookup.h

@@ -631 +631 @@
     AssertCompile(RTASSERT_OFFSET_OF(IEMTLB, uTlbPhysRev) < RTASSERT_OFFSET_OF(IEMTLB, aEntries));
     AssertCompile(RTASSERT_OFFSET_OF(VMCPUCC, iem.s.DataTlb.aEntries) < _64K);
-    AssertCompile(RTASSERT_OFFSET_OF(VMCPUCC, iem.s.CodeTlb.aEntries) < _64K); /* if larger do: ADD x3, x27, x3, LSL #y */
-    pCodeBuf[off++] = Armv8A64MkInstrMovZ(pTlbState->idxReg4, offVCpuTlb + RT_UOFFSETOF(IEMTLB, aEntries));
-    pCodeBuf[off++] = Armv8A64MkInstrAddReg(pTlbState->idxReg4, IEMNATIVE_REG_FIXED_PVMCPU, pTlbState->idxReg4);
+    if (offVCpuTlb + RT_UOFFSETOF(IEMTLB, aEntries) < _64K)
+    {
+        pCodeBuf[off++] = Armv8A64MkInstrMovZ(pTlbState->idxReg4, offVCpuTlb + RT_UOFFSETOF(IEMTLB, aEntries));
+        pCodeBuf[off++] = Armv8A64MkInstrAddReg(pTlbState->idxReg4, IEMNATIVE_REG_FIXED_PVMCPU, pTlbState->idxReg4);
+    }
+    else
+    {
+        AssertCompileMemberAlignment(VMCPUCC, iem.s.CodeTlb.aEntries, 64);
+        AssertCompileMemberAlignment(IEMTLB, aEntries, 64);
+        AssertCompile(RTASSERT_OFFSET_OF(VMCPUCC, iem.s.CodeTlb.aEntries) < _64K*64U);
+        pCodeBuf[off++] = Armv8A64MkInstrMovZ(pTlbState->idxReg4, (offVCpuTlb + RT_UOFFSETOF(IEMTLB, aEntries)) >> 6);
+        pCodeBuf[off++] = Armv8A64MkInstrAddReg(pTlbState->idxReg4, IEMNATIVE_REG_FIXED_PVMCPU, pTlbState->idxReg4,
+                                                true /*64Bit*/, false /*fSetFlags*/, 6 /*cShift*/, kArmv8A64InstrShift_Lsl);
+    }
     pCodeBuf[off++] = Armv8A64MkInstrLdPairGpr(pTlbState->idxReg3, pTlbState->idxReg5, pTlbState->idxReg4,
                                                (RT_OFFSETOF(IEMTLB, uTlbRevision) - RT_OFFSETOF(IEMTLB, aEntries)) / 8);
@@ -649 +660 @@
 # endif
 # if defined(RT_ARCH_AMD64)
+#  if IEMTLB_ENTRY_COUNT == 256
     /* movzx reg2, byte reg1 */
     off = iemNativeEmitLoadGprFromGpr8Ex(pCodeBuf, off, pTlbState->idxReg2, pTlbState->idxReg1);
+#  else
+    /* mov   reg2, reg1 */
+    off = iemNativeEmitLoadGprFromGpr32Ex(pCodeBuf, off, pTlbState->idxReg2, pTlbState->idxReg1);
+    /* and   reg2, IEMTLB_ENTRY_COUNT - 1U */
+    off = iemNativeEmitAndGpr32ByImmEx(pCodeBuf, off, pTlbState->idxReg2, IEMTLB_ENTRY_COUNT - 1U);
+#  endif
     /* shl   reg2, 5 ; reg2 *= sizeof(IEMTLBENTRY) */
     AssertCompileSize(IEMTLBENTRY, 32);
@@ -666 +684 @@
 
 # elif defined(RT_ARCH_ARM64)
-    /* reg2 = (reg1 & 0xff) << 5 */
-    pCodeBuf[off++] = Armv8A64MkInstrUbfiz(pTlbState->idxReg2, pTlbState->idxReg1, 5, 8);
+    /* reg2 = (reg1 & tlbmask) << 5 */
+    pCodeBuf[off++] = Armv8A64MkInstrUbfiz(pTlbState->idxReg2, pTlbState->idxReg1, 5, IEMTLB_ENTRY_COUNT_AS_POWER_OF_TWO);
 #  ifdef IEMNATIVE_WITH_TLB_LOOKUP_LOAD_STORE_PAIR
     /* reg2 += &pVCpu->iem.s.DataTlb.aEntries / CodeTlb.aEntries */