Changeset 104959 in vbox for trunk/src/VBox/ValidationKit/bootsectors

Timestamp:

Jun 19, 2024 6:54:05 AM (8 months ago)

Author:

vboxsync

Message:

ValidationKit/bootsectors: bugref:10658 SIMD FP testcase: [v]addss.

File:

• trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-4.c32 (modified) (1 diff)

trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-4.c32

@@ -2024 +2024 @@
               /*daz,fz,rc*/ X86_MXCSR_DAZ, X86_MXCSR_FZ, X86_MXCSR_RC_ZERO,
               /*flags    */ X86_MXCSR_OE | X86_MXCSR_PE, X86_MXCSR_OE | X86_MXCSR_PE },
-          /** @todo rest of OE, PE. */
+          { { /*src2     */ { BS3_FP32_NORMAL_SAFE_INT_MIN(0),                                          BS3_FP32_RAND_VAL_5(1), BS3_FP32_RAND_VAL_5(0), BS3_FP32_RAND_VAL_4(1), BS3_FP32_RAND_VAL_4(0), BS3_FP32_RAND_VAL_3(0), BS3_FP32_RAND_VAL_3(1), BS3_FP32_RAND_VAL_2(1) } },
+            { /*src1     */ { BS3_FP32_NORMAL_SAFE_INT_MAX(0),                                          BS3_FP32_RAND_VAL_0(1), BS3_FP32_RAND_VAL_1(0), BS3_FP32_RAND_VAL_2(1), BS3_FP32_RAND_VAL_3(0), BS3_FP32_RAND_VAL_4(0), BS3_FP32_RAND_VAL_5(1), BS3_FP32_RAND_VAL_6(0) } },
+            { /* =>      */ { BS3_FP32_VAL(0, BS3_FP32_FRACTION_NORMAL_MAX, BS3_FP32_EXP_SAFE_INT_MAX), BS3_FP32_RAND_VAL_0(1), BS3_FP32_RAND_VAL_1(0), BS3_FP32_RAND_VAL_2(1), BS3_FP32_RAND_VAL_3(0), BS3_FP32_RAND_VAL_4(0), BS3_FP32_RAND_VAL_5(1), BS3_FP32_RAND_VAL_6(0) } },
+              /*mask     */ ~X86_MXCSR_XCPT_MASK,
+              /*daz,fz,rc*/ 0, 0, X86_MXCSR_RC_ZERO,
+              /*flags    */ X86_MXCSR_PE, X86_MXCSR_PE },
+          { { /*src2     */ { BS3_FP32_NORMAL_SAFE_INT_MIN(1),                                          BS3_FP32_RAND_VAL_7(1), BS3_FP32_RAND_VAL_6(0), BS3_FP32_RAND_VAL_5(1), BS3_FP32_RAND_VAL_4(0), BS3_FP32_RAND_VAL_3(0), BS3_FP32_RAND_VAL_2(1), BS3_FP32_RAND_VAL_1(1) } },
+            { /*src1     */ { BS3_FP32_NORMAL_SAFE_INT_MAX(1),                                          BS3_FP32_RAND_VAL_4(1), BS3_FP32_RAND_VAL_3(1), BS3_FP32_RAND_VAL_2(0), BS3_FP32_RAND_VAL_0(1), BS3_FP32_RAND_VAL_4(1), BS3_FP32_RAND_VAL_0(0), BS3_FP32_RAND_VAL_5(1) } },
+            { /* =>      */ { BS3_FP32_VAL(1, BS3_FP32_FRACTION_NORMAL_MAX, BS3_FP32_EXP_SAFE_INT_MAX), BS3_FP32_RAND_VAL_4(1), BS3_FP32_RAND_VAL_3(1), BS3_FP32_RAND_VAL_2(0), BS3_FP32_RAND_VAL_0(1), BS3_FP32_RAND_VAL_4(1), BS3_FP32_RAND_VAL_0(0), BS3_FP32_RAND_VAL_5(1) } },
+              /*mask     */ ~X86_MXCSR_XCPT_MASK,
+              /*daz,fz,rc*/ 0, 0, X86_MXCSR_RC_ZERO,
+              /*flags    */ X86_MXCSR_PE, X86_MXCSR_PE },
     };