Changeset 105035 in vbox for trunk/src/VBox/VMM

Timestamp:

Jun 26, 2024 7:48:07 PM (8 months ago)

Author:

vboxsync

Message:

VMM/IEM,bs3-cpu-weird-1: Made bs3CpuWeird1_PcWrapping run w/o asserting in the recompiler. bugref:10715

Location:

trunk/src/VBox/VMM

Files:

• VMMAll/IEMAllN8veRecompFuncs.h (modified) (1 diff)
• VMMAll/IEMAllN8veRecompiler.cpp (modified) (2 diffs)
• include/IEMMc.h (modified) (2 diffs)

trunk/src/VBox/VMM/VMMAll/IEMAllN8veRecompFuncs.h

@@ -414 +414 @@
          */
         if (   IEM_F_MODE_X86_IS_FLAT(pReNative->fExec)
-            || !(pTbOrg->fFlags & IEMTB_F_CS_LIM_CHECKS) )
+# if 0 /** @todo breaks on IP/EIP/RIP wraparound tests in bs3-cpu-weird-1. See also iemNativeHlpReturnBreakViaLookup. */
+            || !(pTbOrg->fFlags & IEMTB_F_CS_LIM_CHECKS)
+# endif
+           )
         {
             RTGCPHYS const GCPhysPcCurrent = iemNativeCallEntryToGCPhysPc(pTbOrg, pCallEntry);

trunk/src/VBox/VMM/VMMAll/IEMAllN8veRecompiler.cpp

@@ -182 +182 @@
             if (pVCpu->cpum.GstCtx.rflags.uBoth & CPUMCTX_INHIBIT_NMI)
                 fAssertFlags |= IEMTB_F_INHIBIT_NMI;
+#  if 1 /** @todo breaks on IP/EIP/RIP wraparound tests in bs3-cpu-weird-1. */
+            Assert(IEM_F_MODE_X86_IS_FLAT(fFlags));
+#  else
             if (!IEM_F_MODE_X86_IS_FLAT(fFlags))
             {
@@ -188 +191 @@
                     fAssertFlags |= IEMTB_F_CS_LIM_CHECKS;
             }
+#  endif
             Assert(!(fFlags & ~(IEMTB_F_KEY_MASK | IEMTB_F_TYPE_MASK)));
             AssertMsg(fFlags == fAssertFlags, ("fFlags=%#RX32 fAssertFlags=%#RX32 cs:rip=%04x:%#010RX64\n",

trunk/src/VBox/VMM/include/IEMMc.h

@@ -2659 +2659 @@
  */
 #ifdef VBOX_STRICT
-#define IEM_MC_CALL_CIMPL_HLP_RET(a_fFlags, a_CallExpr) \
+# define IEM_MC_CALL_CIMPL_HLP_RET(a_fFlags, a_CallExpr) \
     do { \
         uint8_t      const cbInstr     = IEM_GET_INSTR_LEN(pVCpu); /* may be flushed */ \
@@ -2669 +2669 @@
         if (rcStrictHlp == VINF_SUCCESS) \
         { \
+            uint64_t const fRipMask = (pVCpu->iem.s.fExec & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_64BIT ? UINT64_MAX : UINT32_MAX; \
             AssertMsg(   ((a_fFlags) & IEM_CIMPL_F_BRANCH_ANY) \
-                      || (   uRipBefore + cbInstr == pVCpu->cpum.GstCtx.rip \
-                          && uCsBefore            == pVCpu->cpum.GstCtx.cs.Sel) \
+                      || (   ((uRipBefore + cbInstr) & fRipMask) == pVCpu->cpum.GstCtx.rip \
+                          && uCsBefore  == pVCpu->cpum.GstCtx.cs.Sel) \
                       || (   ((a_fFlags) & IEM_CIMPL_F_REP) \
                           && uRipBefore == pVCpu->cpum.GstCtx.rip \
                           && uCsBefore  == pVCpu->cpum.GstCtx.cs.Sel), \
                       ("CS:RIP=%04x:%08RX64 + %x -> %04x:%08RX64, expected %04x:%08RX64\n", uCsBefore, uRipBefore, cbInstr, \
-                       pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip, uCsBefore, uRipBefore + cbInstr)); \
+                       pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip, uCsBefore, (uRipBefore + cbInstr) & fRipMask)); \
             if ((a_fFlags) & IEM_CIMPL_F_RFLAGS) \
             { /* No need to check fEflBefore */ Assert(!((a_fFlags) & IEM_CIMPL_F_STATUS_FLAGS)); } \