Changeset 105050 in vbox

Timestamp:

Jun 27, 2024 9:16:20 AM (9 months ago)

Author:

vboxsync

svn:sync-xref-src-repo-rev:

163668

Message:

ValidationKit/bootsectors: bugref:10658 SIMD FP testcase: [v]subpd.

File:

• trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-4.c32 (modified) (1 diff)

trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-4.c32

@@ -2534 +2534 @@
               /*daz,fz,rc*/ 0, X86_MXCSR_FZ, X86_MXCSR_RC_ZERO,
               /*flags    */ X86_MXCSR_IE, X86_MXCSR_IE },
-    /** @todo Overflow, Precision; Normals; Denormals; Underflow, Precision; Rounding,
+    /*
+     * Overflow, Precision.
+     */
+    /*12*/{ { /*src2     */ { BS3_FP64_NORMAL_MIN(1), BS3_FP64_ZERO(0), BS3_FP64_NORMAL_MIN(1), BS3_FP64_NORMAL_MIN(0) } },
+            { /*src1     */ { BS3_FP64_NORMAL_MAX(0), BS3_FP64_ZERO(0), BS3_FP64_NORMAL_MAX(0), BS3_FP64_NORMAL_MAX(0) } },
+            { /* =>      */ { BS3_FP64_ZERO(0),       BS3_FP64_ZERO(0), BS3_FP64_ZERO(0),       BS3_FP64_ZERO(0)       } },
+              /*mask     */ ~X86_MXCSR_XCPT_MASK,
+              /*daz,fz,rc*/ 0, 0, X86_MXCSR_RC_NEAREST,
+              /*flags    */ X86_MXCSR_PE, X86_MXCSR_PE },
+          { { /*src2     */ { BS3_FP64_ZERO(0), BS3_FP64_ZERO(0), BS3_FP64_NORMAL_MIN(1), BS3_FP64_NORMAL_MIN(0) } },
+            { /*src1     */ { BS3_FP64_ZERO(0), BS3_FP64_ZERO(0), BS3_FP64_NORMAL_MAX(0), BS3_FP64_NORMAL_MAX(0) } },
+            { /* =>      */ { BS3_FP64_ZERO(0), BS3_FP64_ZERO(0), BS3_FP64_ZERO(0),       BS3_FP64_ZERO(0)       } },
+              /*mask     */ ~X86_MXCSR_XCPT_MASK,
+              /*daz,fz,rc*/ 0, 0, X86_MXCSR_RC_NEAREST,
+              /*flags    */ 0, X86_MXCSR_PE },
+          { { /*src2     */ { BS3_FP64_NORMAL_MAX(0), BS3_FP64_NORMAL_MAX(0), BS3_FP64_NORMAL_MAX(1), BS3_FP64_NORMAL_MAX(1) } },
+            { /*src1     */ { BS3_FP64_NORMAL_MAX(1), BS3_FP64_NORMAL_MAX(1), BS3_FP64_NORMAL_MAX(0), BS3_FP64_NORMAL_MAX(1) } },
+            { /* =>      */ { BS3_FP64_NORMAL_MAX(1), BS3_FP64_NORMAL_MAX(1), BS3_FP64_NORMAL_MAX(0), BS3_FP64_ZERO(0)       } },
+              /*mask     */ X86_MXCSR_OM | X86_MXCSR_PM,
+              /*daz,fz,rc*/ 0, 0, X86_MXCSR_RC_ZERO,
+              /*flags    */ X86_MXCSR_OE | X86_MXCSR_PE, X86_MXCSR_OE | X86_MXCSR_PE },
+          { { /*src2     */ { BS3_FP64_NORMAL_MAX(0), BS3_FP64_ZERO(0), BS3_FP64_ZERO(0), BS3_FP64_NORMAL_MAX(0) } },
+            { /*src1     */ { BS3_FP64_NORMAL_MAX(1), BS3_FP64_ZERO(0), BS3_FP64_ZERO(0), BS3_FP64_NORMAL_MAX(1) } },
+            { /* =>      */ { BS3_FP64_INF(1),        BS3_FP64_ZERO(0), BS3_FP64_ZERO(0), BS3_FP64_INF(1)        } },
+              /*mask     */ X86_MXCSR_OM | X86_MXCSR_PM,
+              /*daz,fz,rc*/ X86_MXCSR_DAZ, X86_MXCSR_FZ, X86_MXCSR_RC_NEAREST,
+              /*flags    */ X86_MXCSR_OE | X86_MXCSR_PE, X86_MXCSR_OE | X86_MXCSR_PE },
+          { { /*src2     */ { BS3_FP64_NORMAL_MAX(0), BS3_FP64_NORMAL_MIN(1), BS3_FP64_VAL(1, 0, 2),  BS3_FP64_NORMAL_MIN(1) } },
+            { /*src1     */ { BS3_FP64_NORMAL_MAX(1), BS3_FP64_NORMAL_MAX(0), BS3_FP64_NORMAL_MIN(1), BS3_FP64_NORMAL_MIN(1) } },
+            { /* =>      */ { BS3_FP64_INF(1),        BS3_FP64_NORMAL_MAX(0), BS3_FP64_NORMAL_MIN(0), BS3_FP64_ZERO(0),      } },
+              /*mask     */ X86_MXCSR_OM | X86_MXCSR_PM,
+              /*daz,fz,rc*/ X86_MXCSR_DAZ, X86_MXCSR_FZ, X86_MXCSR_RC_NEAREST,
+              /*flags    */ X86_MXCSR_OE | X86_MXCSR_PE, X86_MXCSR_OE | X86_MXCSR_PE },
+          { { /*src2     */ { BS3_FP64_VAL(1, 0, 2),  BS3_FP64_NORMAL_MAX(0), BS3_FP64_NORMAL_MAX(0), BS3_FP64_VAL(1, 0, 2)  } },
+            { /*src1     */ { BS3_FP64_NORMAL_MIN(1), BS3_FP64_NORMAL_MAX(1), BS3_FP64_NORMAL_MAX(1), BS3_FP64_NORMAL_MIN(1) } },
+            { /* =>      */ { BS3_FP64_NORMAL_MIN(0), BS3_FP64_NORMAL_MAX(1), BS3_FP64_NORMAL_MAX(1), BS3_FP64_NORMAL_MIN(0) } },
+              /*mask     */ X86_MXCSR_OM | X86_MXCSR_PM,
+              /*daz,fz,rc*/ X86_MXCSR_DAZ, X86_MXCSR_FZ, X86_MXCSR_RC_ZERO,
+              /*flags    */ X86_MXCSR_OE | X86_MXCSR_PE, X86_MXCSR_OE | X86_MXCSR_PE },
+          { { /*src2     */ { BS3_FP64_ZERO(0), BS3_FP64_ZERO(0), BS3_FP64_NORMAL_MIN(0), BS3_FP64_NORMAL_MAX(0) } },
+            { /*src1     */ { BS3_FP64_ZERO(0), BS3_FP64_ZERO(0), BS3_FP64_NORMAL_MIN(0), BS3_FP64_NORMAL_MAX(1) } },
+            { /* =>      */ { BS3_FP64_ZERO(0), BS3_FP64_ZERO(0), BS3_FP64_ZERO(0),       BS3_FP64_NORMAL_MAX(1) } },
+              /*mask     */ X86_MXCSR_XCPT_MASK,
+              /*daz,fz,rc*/ 0, 0, X86_MXCSR_RC_ZERO,
+              /*flags    */ 0, X86_MXCSR_OE | X86_MXCSR_PE },
+          { { /*src2     */ { BS3_FP64_NORMAL_MIN(0), BS3_FP64_NORMAL_MIN(0), BS3_FP64_NORMAL_MIN(1), BS3_FP64_NORMAL_MIN(0) } },
+            { /*src1     */ { BS3_FP64_NORMAL_MAX(0), BS3_FP64_NORMAL_MAX(0), BS3_FP64_NORMAL_MAX(1), BS3_FP64_NORMAL_MAX(0) } },
+            { /* =>      */ { BS3_FP64_ZERO(0),       BS3_FP64_ZERO(0),       BS3_FP64_ZERO(0),       BS3_FP64_ZERO(0)       } },
+              /*mask     */ ~(X86_MXCSR_OM | X86_MXCSR_PM),
+              /*daz,fz,rc*/ 0, 0, X86_MXCSR_RC_ZERO,
+              /*flags    */ X86_MXCSR_PE, X86_MXCSR_PE },
+          { { /*src2     */ { BS3_FP64_NORMAL_SAFE_INT_MIN(0), BS3_FP64_NORMAL_MAX(0), BS3_FP64_NORMAL_SAFE_INT_MAX(1), BS3_FP64_NORMAL_SAFE_INT_MAX(1) } },
+            { /*src1     */ { BS3_FP64_NORMAL_SAFE_INT_MAX(0), BS3_FP64_NORMAL_MAX(1), BS3_FP64_NORMAL_SAFE_INT_MAX(1), BS3_FP64_NORMAL_SAFE_INT_MAX(1) } },
+            { /* =>      */ { BS3_FP64_ZERO(0),                BS3_FP64_ZERO(0),       BS3_FP64_ZERO(0),                BS3_FP64_ZERO(0)                } },
+              /*mask     */ ~X86_MXCSR_XCPT_MASK,
+              /*daz,fz,rc*/ 0, 0, X86_MXCSR_RC_ZERO,
+              /*flags    */ X86_MXCSR_OE |  X86_MXCSR_PE, X86_MXCSR_OE | X86_MXCSR_PE },
+    /** @todo Normals; Denormals; Underflow, Precision; Rounding,
      *        FZ etc. */
     };