VirtualBox

Changeset 105072 in vbox for trunk/include


Ignore:
Timestamp:
Jun 28, 2024 12:03:20 PM (7 months ago)
Author:
vboxsync
Message:

VMM/IEM,DBGF,bs3-cpu-weird-1: Early data breakpoint support, mostly untested except for the ring transition tests in bs3-cpu-weird-1. bugref:10715

Location:
trunk/include
Files:
5 edited

Legend:

Unmodified
Added
Removed

  • trunk/include/VBox/vmm/cpumctx-x86-amd64.h

    r102374 r105072  
    10331033#define CPUMCTX_DBG_HIT_DR3             RT_BIT_32(CPUMCTX_DBG_HIT_DR3_BIT)
    10341034#define CPUMCTX_DBG_HIT_DR3_BIT         (6 + CPUMX86EFLAGS_HW_BITS)
     1035/** Silent guest DRx breakpoint (presistent Intel errata fun). */
     1036#define CPUMCTX_DBG_HIT_DRX_SILENT      RT_BIT_32(CPUMCTX_DBG_HIT_DRX_SILENT_BIT)
     1037#define CPUMCTX_DBG_HIT_DRX_SILENT_BIT  (7 + CPUMX86EFLAGS_HW_BITS)
    10351038/** Shift for the CPUMCTX_DBG_HIT_DRx bits. */
    10361039#define CPUMCTX_DBG_HIT_DRX_SHIFT       CPUMCTX_DBG_HIT_DR0_BIT
    1037 /** Mask of all guest pending DR0-DR3 breakpoint indicators. */
    1038 #define CPUMCTX_DBG_HIT_DRX_MASK        (CPUMCTX_DBG_HIT_DR0 | CPUMCTX_DBG_HIT_DR1 | CPUMCTX_DBG_HIT_DR2 | CPUMCTX_DBG_HIT_DR3)
     1040/** Mask of all guest pending DR0-DR3 indicators (excluding the silent). */
     1041#define CPUMCTX_DBG_HIT_DRX_MASK_NONSILENT (CPUMCTX_DBG_HIT_DR0 | CPUMCTX_DBG_HIT_DR1 | CPUMCTX_DBG_HIT_DR2 | CPUMCTX_DBG_HIT_DR3)
     1042/** Mask of all guest pending DR0-DR3 + silent breakpoint indicators. */
     1043#define CPUMCTX_DBG_HIT_DRX_MASK        (CPUMCTX_DBG_HIT_DRX_MASK_NONSILENT | CPUMCTX_DBG_HIT_DRX_SILENT)
    10391044/** DBGF event/breakpoint pending. */
    10401045#define CPUMCTX_DBG_DBGF_EVENT          RT_BIT_32(CPUMCTX_DBG_DBGF_EVENT_BIT)
    1041 #define CPUMCTX_DBG_DBGF_EVENT_BIT      (7 + CPUMX86EFLAGS_HW_BITS)
     1046#define CPUMCTX_DBG_DBGF_EVENT_BIT      (8 + CPUMX86EFLAGS_HW_BITS)
    10421047/** DBGF event/breakpoint pending. */
    10431048#define CPUMCTX_DBG_DBGF_BP             RT_BIT_32(CPUMCTX_DBG_DBGF_BP_BIT)
    1044 #define CPUMCTX_DBG_DBGF_BP_BIT         (8 + CPUMX86EFLAGS_HW_BITS)
     1049#define CPUMCTX_DBG_DBGF_BP_BIT         (9 + CPUMX86EFLAGS_HW_BITS)
    10451050/** Mask of all DBGF indicators. */
    10461051#define CPUMCTX_DBG_DBGF_MASK           (CPUMCTX_DBG_DBGF_EVENT | CPUMCTX_DBG_DBGF_BP)

  • trunk/include/VBox/vmm/dbgf.h

    r102092 r105072  
    11221122VMM_INT_DECL(bool)          DBGFBpIsInt3Armed(PVM pVM);
    11231123VMM_INT_DECL(bool)          DBGFIsStepping(PVMCPU pVCpu);
    1124 VMM_INT_DECL(VBOXSTRICTRC)  DBGFBpCheckInstruction(PVMCC pVM, PVMCPUCC pVCpu, RTGCPTR GCPtrPC);
     1124VMM_INT_DECL(VBOXSTRICTRC)  DBGFBpCheckInstruction(PVMCC pVM, PVMCPUCC pVCpu, RTGCPTR GCPtrPC, bool fCheckGuest);
     1125VMM_INT_DECL(uint32_t)      DBGFBpCheckDataRead(PVMCC pVM, PVMCPUCC pVCpu, RTGCPTR GCPtrAccess, uint32_t cbAccess, bool fSysAccess);
     1126VMM_INT_DECL(uint32_t)      DBGFBpCheckDataWrite(PVMCC pVM, PVMCPUCC pVCpu, RTGCPTR GCPtrAccess, uint32_t cbAccess, bool fSysAccess);
    11251127VMM_INT_DECL(VBOXSTRICTRC)  DBGFBpCheckIo(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, RTIOPORT uIoPort, uint8_t cbValue);
    11261128VMM_INT_DECL(uint32_t)      DBGFBpCheckIo2(PVMCC pVM, PVMCPUCC pVCpu, RTIOPORT uIoPort, uint8_t cbValue);

  • trunk/include/VBox/vmm/vm.h

    r105036 r105072  
    159159        struct IEMCPU       s;
    160160#endif
    161         uint8_t             padding[146240]; /* multiple of 64 */
     161        uint8_t             padding[146368]; /* multiple of 64 */
    162162    } iem;
    163163
    … …  
    316316
    317317    /** Align the following members on page boundary. */
    318     uint8_t                 abAlignment2[1976];
     318    uint8_t                 abAlignment2[1848];
    319319
    320320    /** PGM part. */

  • trunk/include/VBox/vmm/vm.mac

    r105036 r105072  
    5858
    5959    alignb 64
    60     .iem                    resb 146240
     60    .iem                    resb 146368
    6161
    6262    alignb 64

  • trunk/include/iprt/x86.h

    r104994 r105072  
    12631263
    12641264#ifndef VBOX_FOR_DTRACE_LIB
    1265 /** Checks the RW and LEN fields are set up for an instruction breakpoint.
     1265/** Checks if the RW and LEN fields are set up for an instruction breakpoint.
    12661266 * @note This does not check if it's enabled. */
    12671267# define X86_DR7_IS_EO_CFG(a_uDR7, a_iBp)   ( ((a_uDR7) & (UINT32_C(0x000f0000) << ((a_iBp) * 4))) == 0 )
    … …  
    12701270# define X86_DR7_IS_EO_ENABLED(a_uDR7, a_iBp) \
    12711271    ( ((a_uDR7) & (UINT32_C(0x03) << ((a_iBp) * 2))) != 0 && X86_DR7_IS_EO_CFG(a_uDR7, a_iBp) )
    1272 /** Checks if there are any instruction fetch breakpoint types configured in the
    1273  * RW and LEN registers.
     1272/** Checks if there are any instruction fetch breakpoint types configured in
     1273 * the RW and LEN registers and enabled in the Lx/Gx bits.
    12741274 * @sa X86_DR7_IS_EO_CFG, X86_DR7_IS_EO_ENABLED */
    12751275# define X86_DR7_ANY_EO_ENABLED(a_uDR7) \
    … …  
    12781278     || (((a_uDR7) & UINT32_C(0x30)) != 0 && ((a_uDR7) & UINT32_C(0x0f000000)) == 0) \
    12791279     || (((a_uDR7) & UINT32_C(0xc0)) != 0 && ((a_uDR7) & UINT32_C(0xf0000000)) == 0) )
     1280
     1281/** Checks if the RW field is set up for a read-write data breakpoint.
     1282 * @note This does not check if it's enabled. */
     1283# define X86_DR7_IS_RW_CFG(a_uDR7, a_iBp)   ( ~((a_uDR7) & (UINT32_C(0x00030000) << ((a_iBp) * 4))) == 0)
     1284
     1285/** Checks if there are any read-write data breakpoint types configured in the
     1286 * RW registers and enabled in the Lx/Gx bits.
     1287 *
     1288 * @note We don't consider the LEN registers here, even if qword isn't
     1289 *       techincally valid for older processors - see
     1290 *       @sdmv3{645,18.2.4,Debug Control Register (DR7)} for details.
     1291 */
     1292# define X86_DR7_ANY_RW_ENABLED(a_uDR7) \
     1293    (   (((a_uDR7) & UINT32_C(0x03)) != 0 && ((a_uDR7) & UINT32_C(0x00030000)) == UINT32_C(0x00030000)) \
     1294     || (((a_uDR7) & UINT32_C(0x0c)) != 0 && ((a_uDR7) & UINT32_C(0x00300000)) == UINT32_C(0x00300000)) \
     1295     || (((a_uDR7) & UINT32_C(0x30)) != 0 && ((a_uDR7) & UINT32_C(0x03000000)) == UINT32_C(0x03000000)) \
     1296     || (((a_uDR7) & UINT32_C(0xc0)) != 0 && ((a_uDR7) & UINT32_C(0x30000000)) == UINT32_C(0x30000000)) )
     1297
     1298/** Checks if the RW field is set up for a write-only or read-write data
     1299 *  breakpoint.
     1300 * @note This does not check if it's enabled. */
     1301# define X86_DR7_IS_W_CFG(a_uDR7, a_iBp)   ( ((a_uDR7) & (UINT32_C(0x00010000) << ((a_iBp) * 4))) != 0)
     1302
     1303/** Checks if there are any read-write or write-only data breakpoint types
     1304 * configured in the the RW registers and enabled in the Lx/Gx bits.
     1305 *
     1306 * @note We don't consider the LEN registers here, even if qword isn't
     1307 *       techincally valid for older processors - see
     1308 *       @sdmv3{645,18.2.4,Debug Control Register (DR7)} for details.
     1309 */
     1310# define X86_DR7_ANY_W_ENABLED(a_uDR7) \
     1311    (   (((a_uDR7) & UINT32_C(0x03)) != 0 && ((a_uDR7) & UINT32_C(0x00010000)) != 0) \
     1312     || (((a_uDR7) & UINT32_C(0x0c)) != 0 && ((a_uDR7) & UINT32_C(0x00100000)) != 0) \
     1313     || (((a_uDR7) & UINT32_C(0x30)) != 0 && ((a_uDR7) & UINT32_C(0x01000000)) != 0) \
     1314     || (((a_uDR7) & UINT32_C(0xc0)) != 0 && ((a_uDR7) & UINT32_C(0x10000000)) != 0) )
    12801315
    12811316/** Checks if there are any I/O breakpoint types configured in the RW
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