VirtualBox

Ignore:
Timestamp:
Jul 3, 2024 7:20:03 AM (10 months ago)
Author:
vboxsync
svn:sync-xref-src-repo-rev:
163736
Message:

ValidationKit/bootsectors: bugref:10658 SIMD FP testcase: [v]haddps.

Location:
trunk/src/VBox/ValidationKit/bootsectors
Files:
2 edited

Legend:

Unmodified
Added
Removed

  • TabularUnified trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-4-template.mac

    r105079 r105106  
    200200
    201201;
     202;; [v]haddps
     203;
     204EMIT_INSTR_PLUS_ICEBP       haddps, XMM1, XMM2
     205EMIT_INSTR_PLUS_ICEBP       haddps, XMM1, FSxBX
     206EMIT_INSTR_PLUS_ICEBP_C64   haddps, XMM8, XMM9
     207EMIT_INSTR_PLUS_ICEBP_C64   haddps, XMM8, FSxBX
     208
     209EMIT_INSTR_PLUS_ICEBP       vhaddps, XMM1, XMM2, XMM3
     210EMIT_INSTR_PLUS_ICEBP       vhaddps, XMM1, XMM2, FSxBX
     211EMIT_INSTR_PLUS_ICEBP_C64   vhaddps, XMM8, XMM9, XMM10
     212EMIT_INSTR_PLUS_ICEBP_C64   vhaddps, XMM8, XMM9, FSxBX
     213
     214EMIT_INSTR_PLUS_ICEBP       vhaddps, YMM1, YMM2, YMM3
     215EMIT_INSTR_PLUS_ICEBP       vhaddps, YMM1, YMM2, FSxBX
     216EMIT_INSTR_PLUS_ICEBP_C64   vhaddps, YMM8, YMM9, YMM10
     217EMIT_INSTR_PLUS_ICEBP_C64   vhaddps, YMM8, YMM9, FSxBX
     218
     219;
    202220;; [v]subps
    203221;

  • TabularUnified trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-4.c32

    r105093 r105106  
    21892189
    21902190/*
     2191 * [V]HADDPS.
     2192 */
     2193BS3_DECL_FAR(uint8_t) bs3CpuInstr4_v_haddps(uint8_t bMode)
     2194{
     2195    static BS3CPUINSTR4_TEST1_VALUES_PS_T const s_aValues[] =
     2196    {
     2197    /*
     2198     * Zero.
     2199     */
     2200    /* 0*/{ { /*src2     */ { BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0) } },
     2201            { /*src1     */ { BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0) } },
     2202            { /* =>      */ { BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0) } },
     2203              /*mask     */ X86_MXCSR_XCPT_MASK,
     2204              /*daz,fz,rc*/ 0, 0, X86_MXCSR_RC_NEAREST,
     2205              /*flags    */ 0, 0 },
     2206          { { /*src2     */ { BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0) } },
     2207            { /*src1     */ { BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0) } },
     2208            { /* =>      */ { BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0) } },
     2209              /*mask     */ ~X86_MXCSR_XCPT_MASK,
     2210              /*daz,fz,rc*/ 0, 0, X86_MXCSR_RC_NEAREST,
     2211              /*flags    */ 0, 0 },
     2212          { { /*src2     */ { BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0) } },
     2213            { /*src1     */ { BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0) } },
     2214            { /* =>      */ { BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0) } },
     2215              /*mask     */ ~X86_MXCSR_XCPT_MASK,
     2216              /*daz,fz,rc*/ X86_MXCSR_DAZ, X86_MXCSR_FZ, X86_MXCSR_RC_UP,
     2217              /*flags    */ 0, 0 },
     2218          { { /*src2     */ { BS3_FP32_ZERO(1), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(1) } },
     2219            { /*src1     */ { BS3_FP32_ZERO(1), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(1) } },
     2220            { /* =>      */ { BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0) } },
     2221              /*mask     */ ~X86_MXCSR_XCPT_MASK,
     2222              /*daz,fz,rc*/ X86_MXCSR_DAZ, 0, X86_MXCSR_RC_ZERO,
     2223              /*flags    */ 0, 0 },
     2224          { { /*src2     */ { BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(1), BS3_FP32_ZERO(0), BS3_FP32_ZERO(1), BS3_FP32_ZERO(0), BS3_FP32_ZERO(1), BS3_FP32_ZERO(1) } },
     2225            { /*src1     */ { BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(1), BS3_FP32_ZERO(0), BS3_FP32_ZERO(1), BS3_FP32_ZERO(0), BS3_FP32_ZERO(1), BS3_FP32_ZERO(1) } },
     2226            { /* =>      */ { BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(0), BS3_FP32_ZERO(1), BS3_FP32_ZERO(0), BS3_FP32_ZERO(1) } },
     2227              /*mask     */ ~X86_MXCSR_XCPT_MASK,
     2228              /*daz,fz,rc*/ 0, X86_MXCSR_FZ, X86_MXCSR_RC_ZERO,
     2229              /*flags    */ 0, 0 },
     2230          { { /*src2     */ { BS3_FP32_ZERO(0), BS3_FP32_ZERO(1), BS3_FP32_ZERO(0), BS3_FP32_ZERO(1), BS3_FP32_ZERO(0), BS3_FP32_ZERO(1), BS3_FP32_ZERO(0), BS3_FP32_ZERO(1) } },
     2231            { /*src1     */ { BS3_FP32_ZERO(0), BS3_FP32_ZERO(1), BS3_FP32_ZERO(0), BS3_FP32_ZERO(1), BS3_FP32_ZERO(0), BS3_FP32_ZERO(1), BS3_FP32_ZERO(0), BS3_FP32_ZERO(1) } },
     2232            { /* =>      */ { BS3_FP32_ZERO(1), BS3_FP32_ZERO(1), BS3_FP32_ZERO(1), BS3_FP32_ZERO(1), BS3_FP32_ZERO(1), BS3_FP32_ZERO(1), BS3_FP32_ZERO(1), BS3_FP32_ZERO(1) } },
     2233              /*mask     */ X86_MXCSR_XCPT_MASK,
     2234              /*daz,fz,rc*/ X86_MXCSR_DAZ, X86_MXCSR_FZ, X86_MXCSR_RC_DOWN,
     2235              /*flags    */ 0, 0 },
     2236    /** @todo Infinity; Overflow, precision; Denormals; Normals; etc.   */
     2237    };
     2238
     2239    static BS3CPUINSTR4_TEST1_T const s_aTests16[] =
     2240    {
     2241        { bs3CpuInstr4_haddps_XMM1_XMM2_icebp_c16,  255, RM_REG, T_SSE, 1, 1, 2,   RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
     2242        { bs3CpuInstr4_haddps_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE, 1, 1, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
     2243
     2244        { bs3CpuInstr4_vhaddps_XMM1_XMM2_XMM3_icebp_c16,  255, RM_REG, T_AVX_128, 1, 2, 3,   RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
     2245        { bs3CpuInstr4_vhaddps_XMM1_XMM2_FSxBX_icebp_c16, 255, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
     2246
     2247        { bs3CpuInstr4_vhaddps_YMM1_YMM2_YMM3_icebp_c16,  255, RM_REG, T_AVX_256, 1, 2, 3,   RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
     2248        { bs3CpuInstr4_vhaddps_YMM1_YMM2_FSxBX_icebp_c16, 255, RM_MEM, T_AVX_256, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
     2249    };
     2250    static BS3CPUINSTR4_TEST1_T const s_aTests32[] =
     2251    {
     2252        { bs3CpuInstr4_haddps_XMM1_XMM2_icebp_c32,  255, RM_REG, T_SSE, 1, 1, 2,   RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
     2253        { bs3CpuInstr4_haddps_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE, 1, 1, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
     2254
     2255        { bs3CpuInstr4_vhaddps_XMM1_XMM2_XMM3_icebp_c32,  255, RM_REG, T_AVX_128, 1, 2, 3,   RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
     2256        { bs3CpuInstr4_vhaddps_XMM1_XMM2_FSxBX_icebp_c32, 255, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
     2257
     2258        { bs3CpuInstr4_vhaddps_YMM1_YMM2_YMM3_icebp_c32,  255, RM_REG, T_AVX_256, 1, 2, 3,   RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
     2259        { bs3CpuInstr4_vhaddps_YMM1_YMM2_FSxBX_icebp_c32, 255, RM_MEM, T_AVX_256, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
     2260    };
     2261    static BS3CPUINSTR4_TEST1_T const s_aTests64[] =
     2262    {
     2263        { bs3CpuInstr4_haddps_XMM1_XMM2_icebp_c64,  255, RM_REG, T_SSE, 1, 1, 2,   RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
     2264        { bs3CpuInstr4_haddps_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE, 1, 1, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
     2265
     2266        { bs3CpuInstr4_vhaddps_XMM1_XMM2_XMM3_icebp_c64,  255, RM_REG, T_AVX_128, 1, 2, 3,   RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
     2267        { bs3CpuInstr4_vhaddps_XMM1_XMM2_FSxBX_icebp_c64, 255, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
     2268
     2269        { bs3CpuInstr4_vhaddps_YMM1_YMM2_YMM3_icebp_c64,  255, RM_REG, T_AVX_256, 1, 2, 3,   RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
     2270        { bs3CpuInstr4_vhaddps_YMM1_YMM2_FSxBX_icebp_c64, 255, RM_MEM, T_AVX_256, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
     2271
     2272        { bs3CpuInstr4_haddps_XMM8_XMM9_icebp_c64,  255, RM_REG, T_SSE, 8, 8, 9,   RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
     2273        { bs3CpuInstr4_haddps_XMM8_FSxBX_icebp_c64, 255, RM_MEM, T_SSE, 8, 8, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
     2274
     2275        { bs3CpuInstr4_vhaddps_YMM8_YMM9_YMM10_icebp_c64, 255, RM_REG, T_AVX_256, 8, 9, 10,  RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
     2276        { bs3CpuInstr4_vhaddps_YMM8_YMM9_FSxBX_icebp_c64, 255, RM_MEM, T_AVX_256, 8, 9, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
     2277    };
     2278
     2279    static BS3CPUINSTR4_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR4_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64);
     2280    unsigned const                         iTest       = BS3CPUINSTR4_TEST_MODES_INDEX(bMode);
     2281    return bs3CpuInstr4_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests,
     2282                                        g_aXcptConfig2, RT_ELEMENTS(g_aXcptConfig2));
     2283}
     2284
     2285
     2286/*
    21912287 * [V]SUBPS.
    21922288 */
    … …  
    29993095#endif
    30003096#if defined(ALL_TESTS)
    3001         { "[v]addps",       bs3CpuInstr4_v_addps, 0 },
    3002         { "[v]addpd",       bs3CpuInstr4_v_addpd, 0 },
    3003         { "[v]addss",       bs3CpuInstr4_v_addss, 0 },
    3004         { "[v]subps",       bs3CpuInstr4_v_subps, 0 },
    3005         { "[v]subpd",       bs3CpuInstr4_v_subpd, 0 },
    3006         { "[v]subss",       bs3CpuInstr4_v_subss, 0 },
     3097        { "[v]addps",       bs3CpuInstr4_v_addps,  0 },
     3098        { "[v]addpd",       bs3CpuInstr4_v_addpd,  0 },
     3099        { "[v]addss",       bs3CpuInstr4_v_addss,  0 },
     3100        { "[v]haddps",      bs3CpuInstr4_v_haddps, 0 },
     3101        { "[v]subps",       bs3CpuInstr4_v_subps,  0 },
     3102        { "[v]subpd",       bs3CpuInstr4_v_subpd,  0 },
     3103        { "[v]subss",       bs3CpuInstr4_v_subss,  0 },
    30073104#endif
    30083105    };
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