Changeset 105172 in vbox for trunk/include
- Timestamp:
- Jul 7, 2024 12:59:59 PM (7 months ago)
- File:
-
- 1 edited
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trunk/include/iprt/armv8.h
r105171 r105172 4820 4820 } ARMV8INSTRVECARITHSZ; 4821 4821 4822 /** 4823 * A64: Encodes ADD/SUB (vector, register). 4824 * 4825 * @returns The encoded instruction. 4826 * @param fSub Flag whther this is an addition (false) or subtraction (true) instruction. 4822 4823 /** Armv8 vector arithmetic operation. */ 4824 typedef enum 4825 { 4826 kArmv8VecInstrArithOp_Add = RT_BIT_32(15), /**< ADD */ 4827 kArmv8VecInstrArithOp_Sub = RT_BIT_32(29) | RT_BIT_32(15), /**< SUB */ 4828 kArmv8VecInstrArithOp_UnsignSat_Add = RT_BIT_32(29) | RT_BIT_32(11), /**< UQADD */ 4829 kArmv8VecInstrArithOp_UnsignSat_Sub = RT_BIT_32(29) | RT_BIT_32(13) | RT_BIT_32(11), /**< UQSUB */ 4830 kArmv8VecInstrArithOp_SignSat_Add = RT_BIT_32(11), /**< SQADD */ 4831 kArmv8VecInstrArithOp_SignSat_Sub = RT_BIT_32(13) | RT_BIT_32(11), /**< SQSUB */ 4832 kArmv8VecInstrArithOp_Mul = RT_BIT_32(15) | RT_BIT_32(12) | RT_BIT_32(11) /**< MUL */ 4833 } ARMV8INSTRVECARITHOP; 4834 4835 4836 /** 4837 * A64: Encodes an arithmetic operation (vector, register). 4838 * 4839 * @returns The encoded instruction. 4840 * @param enmOp The operation to encode. 4827 4841 * @param iVecRegDst The vector register to put the result into. 4828 4842 * @param iVecRegSrc1 The first vector source register. … … 4832 4846 * or just the low 64-bit (false). 4833 4847 */ 4834 DECL_FORCE_INLINE(uint32_t) Armv8A64MkVecInstrA ddSub(bool fSub, uint32_t iVecRegDst, uint32_t iVecRegSrc1, uint32_t iVecRegSrc2,4835 ARMV8INSTRVECARITHSZ enmSz, bool f128Bit = true)4848 DECL_FORCE_INLINE(uint32_t) Armv8A64MkVecInstrArithOp(ARMV8INSTRVECARITHOP enmOp, uint32_t iVecRegDst, uint32_t iVecRegSrc1, uint32_t iVecRegSrc2, 4849 ARMV8INSTRVECARITHSZ enmSz, bool f128Bit = true) 4836 4850 { 4837 4851 Assert(iVecRegDst < 32); Assert(iVecRegSrc1 < 32); Assert(iVecRegSrc2 < 32); 4838 4852 4839 return UINT32_C(0x0e208400) 4853 return UINT32_C(0x0e200400) 4854 | (uint32_t)enmOp 4840 4855 | ((uint32_t)f128Bit << 30) 4841 | ((uint32_t)fSub << 29)4842 4856 | ((uint32_t)enmSz << 22) 4843 4857 | (iVecRegSrc2 << 16)
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