Changeset 105183 in vbox for trunk/src/VBox/VMM
- Timestamp:
- Jul 8, 2024 12:26:36 PM (7 months ago)
- Location:
- trunk/src/VBox/VMM
- Files:
-
- 7 edited
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VMMAll/IEMAllInstPython.py (modified) (3 diffs)
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VMMAll/IEMAllN8veLiveness.cpp (modified) (3 diffs)
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VMMAll/IEMAllN8vePython.py (modified) (2 diffs)
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VMMAll/IEMAllN8veRecompFuncs.h (modified) (5 diffs)
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VMMAll/IEMAllThrdPython.py (modified) (2 diffs)
-
include/IEMMc.h (modified) (3 diffs)
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testcase/tstIEMCheckMc.cpp (modified) (4 diffs)
Legend:
- Unmodified
- Added
- Removed
-
trunk/src/VBox/VMM/VMMAll/IEMAllInstPython.py
r104419 r105183 3134 3134 'IEM_MC_FETCH_YREG_U128': (McBlock.parseMcGeneric, False, False, g_fNativeSimd), 3135 3135 'IEM_MC_FETCH_YREG_U256': (McBlock.parseMcGeneric, False, False, g_fNativeSimd), 3136 'IEM_MC_FETCH_YREG_YMM': (McBlock.parseMcGeneric, False, False, g_fNativeSimd), 3136 3137 'IEM_MC_FETCH_YREG_U32': (McBlock.parseMcGeneric, False, False, g_fNativeSimd), 3137 3138 'IEM_MC_FETCH_YREG_U64': (McBlock.parseMcGeneric, False, False, g_fNativeSimd), … … 3295 3296 'IEM_MC_REF_XREG_R64_CONST': (McBlock.parseMcGeneric, False, False, g_fNativeSimd), 3296 3297 'IEM_MC_REF_XREG_U128': (McBlock.parseMcGeneric, False, False, True, ), 3298 'IEM_MC_REF_XREG_XMM': (McBlock.parseMcGeneric, False, False, True, ), 3297 3299 'IEM_MC_REF_XREG_U128_CONST': (McBlock.parseMcGeneric, False, False, True, ), 3298 3300 'IEM_MC_REF_XREG_U32_CONST': (McBlock.parseMcGeneric, False, False, g_fNativeSimd), … … 3384 3386 'IEM_MC_STORE_YREG_U128_ZX_VLMAX': (McBlock.parseMcGeneric, True, True, g_fNativeSimd), 3385 3387 'IEM_MC_STORE_YREG_U256_ZX_VLMAX': (McBlock.parseMcGeneric, True, True, g_fNativeSimd), 3388 'IEM_MC_STORE_YREG_YMM_ZX_VLMAX': (McBlock.parseMcGeneric, True, True, g_fNativeSimd), 3386 3389 'IEM_MC_STORE_YREG_U32_U256': (McBlock.parseMcGeneric, True, True, g_fNativeSimd), 3387 3390 'IEM_MC_STORE_YREG_U32_ZX_VLMAX': (McBlock.parseMcGeneric, True, True, g_fNativeSimd), -
trunk/src/VBox/VMM/VMMAll/IEMAllN8veLiveness.cpp
r104420 r105183 746 746 747 747 #define IEM_MC_REF_XREG_U128(a_pu128Dst, a_iXReg) NOP() 748 #define IEM_MC_REF_XREG_XMM(a_puXmmDst, a_iXReg) NOP() 748 749 #define IEM_MC_REF_XREG_U128_CONST(a_pu128Dst, a_iXReg) NOP() 749 750 #define IEM_MC_REF_XREG_XMM_CONST(a_pXmmDst, a_iXReg) NOP() … … 758 759 #define IEM_MC_FETCH_YREG_U128(a_u128Dst, a_iYRegSrc, a_iDQWord) NOP() 759 760 #define IEM_MC_FETCH_YREG_U256(a_u256Dst, a_iYRegSrc) NOP() 761 #define IEM_MC_FETCH_YREG_YMM(a_uYmmDst, a_iYRegSrc) NOP() 760 762 761 763 #define IEM_MC_STORE_YREG_U128(a_iYRegDst, a_iDQword, a_u128Value) NOP() … … 766 768 #define IEM_MC_STORE_YREG_U128_ZX_VLMAX(a_iYRegDst, a_u128Src) NOP() 767 769 #define IEM_MC_STORE_YREG_U256_ZX_VLMAX(a_iYRegDst, a_u256Src) NOP() 770 #define IEM_MC_STORE_YREG_YMM_ZX_VLMAX(a_iYRegDst, a_uYmmSrc) NOP() 768 771 769 772 #define IEM_MC_STORE_YREG_U32_U256(a_iYRegDst, a_iDwDst, a_u256Value, a_iDwSrc) NOP() -
trunk/src/VBox/VMM/VMMAll/IEMAllN8vePython.py
r104422 r105183 204 204 'IEM_MC_FETCH_MEM_FLAT_U8_ZX_U64': (None, True, True, True, ), 205 205 'IEM_MC_FETCH_MEM_FLAT_XMM_ALIGN_SSE': (None, True, True, g_fNativeSimd), 206 'IEM_MC_FETCH_MEM_FLAT_XMM_NO_AC': (None, True, True, g_fNativeSimd), 206 207 'IEM_MC_FETCH_MEM_FLAT_U128_AND_XREG_U128': (None, True, True, False, ), 207 208 'IEM_MC_FETCH_MEM_FLAT_XMM_ALIGN_SSE_AND_XREG_XMM': (None, True, True, False, ), … … 210 211 'IEM_MC_FETCH_MEM_FLAT_U128_AND_XREG_U128_AND_RAX_RDX_U64': (None, True, True, False, ), 211 212 'IEM_MC_FETCH_MEM_FLAT_U128_AND_XREG_U128_AND_EAX_EDX_U32_SX_U64': (None, True, True, False, ), 213 'IEM_MC_FETCH_MEM_FLAT_YMM_NO_AC': (None, True, True, g_fNativeSimd), 212 214 'IEM_MC_MEM_FLAT_MAP_D80_WO': (None, True, True, True, ), 213 215 'IEM_MC_MEM_FLAT_MAP_I16_WO': (None, True, True, True, ), -
trunk/src/VBox/VMM/VMMAll/IEMAllN8veRecompFuncs.h
r105035 r105183 5412 5412 #define IEM_MC_REF_XREG_U128(a_pu128Dst, a_iXReg) \ 5413 5413 off = iemNativeEmitRefXregXxx(pReNative, off, a_pu128Dst, a_iXReg, false /*fConst*/) 5414 5415 #define IEM_MC_REF_XREG_XMM(a_puXmmDst, a_iXReg) \ 5416 off = iemNativeEmitRefXregXxx(pReNative, off, a_puXmmDst, a_iXReg, false /*fConst*/) 5414 5417 5415 5418 #define IEM_MC_REF_XREG_U128_CONST(a_pu128Dst, a_iXReg) \ … … 7164 7167 (uintptr_t)iemNativeHlpMemFlatFetchDataU128NoAc, pCallEntry->idxInstr) 7165 7168 7169 #define IEM_MC_FETCH_MEM_FLAT_XMM_NO_AC(a_uXmmDst, a_GCPtrMem) \ 7170 off = iemNativeEmitMemFetchStoreDataCommon(pReNative, off, a_uXmmDst, UINT8_MAX, a_GCPtrMem, \ 7171 sizeof(X86XMMREG), sizeof(X86XMMREG) - 1, kIemNativeEmitMemOp_Fetch, \ 7172 (uintptr_t)iemNativeHlpMemFlatFetchDataU128NoAc, pCallEntry->idxInstr) 7173 7166 7174 /* 256-bit segmented: */ 7167 7175 #define IEM_MC_FETCH_MEM_U256(a_u256Dst, a_iSeg, a_GCPtrMem) \ … … 7196 7204 (sizeof(RTUINT256U) - 1U) | IEM_MEMMAP_F_ALIGN_GP, kIemNativeEmitMemOp_Fetch, \ 7197 7205 (uintptr_t)iemNativeHlpMemFlatFetchDataU256AlignedAvx, pCallEntry->idxInstr) 7206 7207 #define IEM_MC_FETCH_MEM_FLAT_YMM_NO_AC(a_uYmmDst, a_GCPtrMem) \ 7208 off = iemNativeEmitMemFetchStoreDataCommon(pReNative, off, a_uYmmDst, UINT8_MAX, a_GCPtrMem, \ 7209 sizeof(X86YMMREG), sizeof(X86YMMREG) - 1, kIemNativeEmitMemOp_Fetch, \ 7210 (uintptr_t)iemNativeHlpMemFlatFetchDataU256NoAc, pCallEntry->idxInstr) 7211 7198 7212 #endif 7199 7213 … … 9768 9782 off = iemNativeEmitSimdFetchYregU256(pReNative, off, a_u256Dst, a_iYRegSrc) 9769 9783 9770 9771 /** Emits code for IEM_MC_FETCH_YREG_U256. */ 9784 #define IEM_MC_FETCH_YREG_YMM(a_uYmmDst, a_iYRegSrc) \ 9785 off = iemNativeEmitSimdFetchYregU256(pReNative, off, a_uYmmDst, a_iYRegSrc) 9786 9787 /** Emits code for IEM_MC_FETCH_YREG_U256/IEM_MC_FETCH_YREG_YMM. */ 9772 9788 DECL_INLINE_THROW(uint32_t) 9773 9789 iemNativeEmitSimdFetchYregU256(PIEMRECOMPILERSTATE pReNative, uint32_t off, uint8_t idxDstVar, uint8_t iYRegSrc) … … 9793 9809 off = iemNativeEmitSimdStoreYregU256ZxVlmax(pReNative, off, a_iYRegDst, a_u256Src) 9794 9810 9795 9796 /** Emits code for IEM_MC_STORE_YREG_U256_ZX_VLMAX. */ 9811 #define IEM_MC_STORE_YREG_YMM_ZX_VLMAX(a_iYRegDst, a_uYmmSrc) \ 9812 off = iemNativeEmitSimdStoreYregU256ZxVlmax(pReNative, off, a_iYRegDst, a_uYmmSrc) 9813 9814 /** Emits code for IEM_MC_STORE_YREG_U256_ZX_VLMAX/IEM_MC_STORE_YREG_YMM_ZX_VLMAX. */ 9797 9815 DECL_INLINE_THROW(uint32_t) 9798 9816 iemNativeEmitSimdStoreYregU256ZxVlmax(PIEMRECOMPILERSTATE pReNative, uint32_t off, uint8_t iYRegDst, uint8_t idxSrcVar) -
trunk/src/VBox/VMM/VMMAll/IEMAllThrdPython.py
r104424 r105183 82 82 'RTUINT128U': ( 128, False, 'RTUINT128U', ), 83 83 'X86XMMREG': ( 128, False, 'X86XMMREG', ), 84 'X86YMMREG': ( 256, False, 'X86YMMREG', ), 84 85 'IEMMEDIAF2XMMSRC': ( 256, False, 'IEMMEDIAF2XMMSRC',), 85 86 'RTUINT256U': ( 256, False, 'RTUINT256U', ), … … 1836 1837 1837 1838 'IEM_MC_FETCH_YREG_U256': '__yreg256', 1839 'IEM_MC_FETCH_YREG_YMM': '__yreg256', 1838 1840 'IEM_MC_FETCH_YREG_U128': '__yreg128', 1839 1841 'IEM_MC_FETCH_YREG_U64': '__yreg64', -
trunk/src/VBox/VMM/include/IEMMc.h
r105035 r105183 633 633 #define IEM_MC_REF_XREG_U128(a_pu128Dst, a_iXReg) \ 634 634 (a_pu128Dst) = (&pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].uXmm) 635 #define IEM_MC_REF_XREG_XMM(a_pXmmDst, a_iXReg) \ 636 (a_pXmmDst) = (&pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)]) 635 637 #define IEM_MC_REF_XREG_U128_CONST(a_pu128Dst, a_iXReg) \ 636 638 (a_pu128Dst) = ((PCRTUINT128U)&pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].uXmm) … … 683 685 (a_u256Dst).au64[3] = pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegSrcTmp].au64[1]; \ 684 686 } while (0) 687 #define IEM_MC_FETCH_YREG_YMM(a_uYmmDst, a_iYRegSrc) \ 688 do { uintptr_t const iYRegSrcTmp = (a_iYRegSrc); \ 689 (a_uYmmDst).au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[0]; \ 690 (a_uYmmDst).au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[1]; \ 691 (a_uYmmDst).au64[2] = pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegSrcTmp].au64[0]; \ 692 (a_uYmmDst).au64[3] = pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegSrcTmp].au64[1]; \ 693 } while (0) 685 694 686 695 #define IEM_MC_STORE_YREG_U128(a_iYRegDst, a_iDQword, a_u128Value) \ … … 730 739 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = (a_u256Src).au64[2]; \ 731 740 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = (a_u256Src).au64[3]; \ 741 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \ 742 } while (0) 743 #define IEM_MC_STORE_YREG_YMM_ZX_VLMAX(a_iYRegDst, a_uYmmSrc) \ 744 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \ 745 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = (a_uYmmSrc).au64[0]; \ 746 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = (a_uYmmSrc).au64[1]; \ 747 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = (a_uYmmSrc).au64[2]; \ 748 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = (a_uYmmSrc).au64[3]; \ 732 749 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \ 733 750 } while (0) -
trunk/src/VBox/VMM/testcase/tstIEMCheckMc.cpp
r104784 r105183 843 843 #define IEM_MC_BROADCAST_XREG_U128_ZX_VLMAX(a_iXRegDst, a_u128Value) do {CHK_XREG_IDX(a_iXRegDst); CHK_VAR(a_u128Value); CHK_TYPE(RTUINT128U, a_u128Value); (void)fAvxWrite; (void)fMcBegin; } while (0) 844 844 #define IEM_MC_REF_XREG_U128(a_pu128Dst, a_iXReg) do { CHK_XREG_IDX(a_iXReg); CHK_VAR(a_pu128Dst); (a_pu128Dst) = (PRTUINT128U)((uintptr_t)0); CHK_PTYPE(PRTUINT128U, a_pu128Dst); (void)fSseWrite; (void)fMcBegin; } while (0) 845 #define IEM_MC_REF_XREG_XMM(a_pXmmDst, a_iXReg) do { CHK_XREG_IDX(a_iXReg); CHK_VAR(a_pXmmDst); (a_pXmmDst) = (PX86XMMREG)((uintptr_t)0); CHK_PTYPE(PX86XMMREG, a_pXmmDst); (void)fSseWrite; (void)fMcBegin; } while (0) 845 846 #define IEM_MC_REF_XREG_U128_CONST(a_pu128Dst, a_iXReg) do { CHK_XREG_IDX(a_iXReg); CHK_VAR(a_pu128Dst); (a_pu128Dst) = (PCRTUINT128U)((uintptr_t)0); CHK_PTYPE(PCRTUINT128U, a_pu128Dst); (void)fSseWrite; (void)fMcBegin; } while (0) 846 847 #define IEM_MC_REF_XREG_U32_CONST(a_pu32Dst, a_iXReg) do { CHK_XREG_IDX(a_iXReg); CHK_VAR(a_pu32Dst); (a_pu32Dst) = (uint32_t const *)((uintptr_t)0); CHK_PTYPE(uint32_t const *, a_pu32Dst); (void)fSseWrite; (void)fMcBegin; } while (0) … … 852 853 853 854 #define IEM_MC_FETCH_YREG_U256(a_u256Value, a_iYRegSrc) do { CHK_YREG_IDX(a_iYRegSrc); CHK_VAR(a_u256Value); (a_u256Value).au64[0] = (a_u256Value).au64[1] = (a_u256Value).au64[2] = (a_u256Value).au64[3] = 0; CHK_TYPE(RTUINT256U, a_u256Value); (void)fAvxRead; (void)fMcBegin; } while (0) 855 #define IEM_MC_FETCH_YREG_YMM(a_YmmValue, a_iYRegSrc) do { CHK_YREG_IDX(a_iYRegSrc); CHK_VAR(a_YmmValue); (a_YmmValue).au64[0] = (a_YmmValue).au64[1] = (a_YmmValue).au64[2] = (a_YmmValue).au64[3] = 0; CHK_TYPE(X86YMMREG, a_YmmValue); (void)fAvxRead; (void)fMcBegin; } while (0) 854 856 #define IEM_MC_FETCH_YREG_U128(a_u128Value, a_iYRegSrc, a_iDQWord) do { CHK_YREG_IDX(a_iYRegSrc); CHK_VAR(a_u128Value); (a_u128Value).au64[0] = (a_u128Value).au64[1] = 0; CHK_TYPE(RTUINT128U, a_u128Value); (void)fAvxRead; (void)fMcBegin; } while (0) 855 857 #define IEM_MC_FETCH_YREG_U64(a_u64Value, a_iYRegSrc, a_iQWord) do { CHK_YREG_IDX(a_iYRegSrc); CHK_VAR(a_u64Value); (a_u64Value) = UINT64_MAX; CHK_TYPE(uint64_t, a_u64Value); (void)fAvxRead; (void)fMcBegin; } while (0) … … 861 863 #define IEM_MC_STORE_YREG_U128_ZX_VLMAX(a_iYRegDst, a_u128Value) do { CHK_YREG_IDX(a_iYRegDst); CHK_VAR(a_u128Value); CHK_TYPE(RTUINT128U, a_u128Value); (void)fAvxWrite; (void)fMcBegin; } while (0) 862 864 #define IEM_MC_STORE_YREG_U256_ZX_VLMAX(a_iYRegDst, a_u256Value) do { CHK_YREG_IDX(a_iYRegDst); CHK_VAR(a_u256Value); CHK_TYPE(RTUINT256U, a_u256Value); (void)fAvxWrite; (void)fMcBegin; } while (0) 865 #define IEM_MC_STORE_YREG_YMM_ZX_VLMAX(a_iYRegDst, a_uYmmValue) do { CHK_YREG_IDX(a_iYRegDst); CHK_VAR(a_uYmmValue); CHK_TYPE(X86YMMREG, a_uYmmValue); (void)fAvxWrite; (void)fMcBegin; } while (0) 863 866 #define IEM_MC_STORE_YREG_U32_U256(a_iYRegDst, a_iDwDst, a_u256Value, a_iDwSrc) do { CHK_XREG_IDX(a_iYRegDst); CHK_VAR(a_u256Value); CHK_TYPE(RTUINT256U, a_u256Value); AssertCompile((a_iDwDst) < RT_ELEMENTS((a_u256Value).au32)); AssertCompile((a_iDwSrc) < RT_ELEMENTS((a_u256Value).au32)); (void)fAvxWrite; (void)fMcBegin; } while (0) 864 867 #define IEM_MC_STORE_YREG_U64_U256(a_iYRegDst, a_iQwDst, a_u256Value, a_iQwSrc) do { CHK_XREG_IDX(a_iYRegDst); CHK_VAR(a_u256Value); CHK_TYPE(RTUINT256U, a_u256Value); AssertCompile((a_iQwDst) < RT_ELEMENTS((a_u256Value).au64)); AssertCompile((a_iQwSrc) < RT_ELEMENTS((a_u256Value).au64)); (void)fAvxWrite; (void)fMcBegin; } while (0) … … 924 927 #define IEM_MC_FETCH_MEM_U256_NO_AC(a_u256Dst, a_iSeg, a_GCPtrMem) do { CHK_SEG_IDX(a_iSeg); CHK_GCPTR(a_GCPtrMem); CHK_VAR(a_GCPtrMem); CHK_VAR(a_u256Dst); CHK_TYPE(RTUINT256U, a_u256Dst); (void)fMcBegin; } while (0) 925 928 #define IEM_MC_FETCH_MEM_U256_ALIGN_AVX(a_u256Dst, a_iSeg, a_GCPtrMem) do { CHK_SEG_IDX(a_iSeg); CHK_GCPTR(a_GCPtrMem); CHK_VAR(a_GCPtrMem); CHK_VAR(a_u256Dst); CHK_TYPE(RTUINT256U, a_u256Dst); (void)fMcBegin; } while (0) 929 #define IEM_MC_FETCH_MEM_YMM_NO_AC(a_YmmDst, a_iSeg, a_GCPtrMem) do { CHK_SEG_IDX(a_iSeg); CHK_GCPTR(a_GCPtrMem); CHK_VAR(a_GCPtrMem); CHK_VAR(a_YmmDst); CHK_TYPE(X86YMMREG, a_YmmDst); (void)fMcBegin; } while (0) 926 930 927 931 # define IEM_MC_FETCH_MEM_U128_AND_XREG_U128(a_Dst, a_iXReg1, a_iSeg2, a_GCPtrMem2) \
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