Index: trunk/src/VBox/VMM/VMMAll/IEMAllAImplC.cpp
===================================================================
--- trunk/src/VBox/VMM/VMMAll/IEMAllAImplC.cpp	(revision 105218)
+++ trunk/src/VBox/VMM/VMMAll/IEMAllAImplC.cpp	(revision 105219)
@@ -16023,5 +16023,5 @@
 
 /**
- * ADDSD
+ * [V]ADDSD
  */
 #ifdef IEM_WITHOUT_ASSEMBLY
@@ -16032,4 +16032,11 @@
 }
 #endif
+
+
+IEM_DECL_IMPL_DEF(uint32_t, iemAImpl_vaddsd_u128_r64_fallback,(uint32_t uMxCsrIn, PX86XMMREG pResult, PCX86XMMREG puSrc1, PCRTFLOAT64U pr64Src2))
+{
+    pResult->ar64[1] = puSrc1->ar64[1];
+    return iemAImpl_addpd_u128_worker(&pResult->ar64[0], uMxCsrIn, &puSrc1->ar64[0], pr64Src2);
+}
 
 
Index: trunk/src/VBox/VMM/VMMAll/IEMAllInstVexMap1.cpp.h
===================================================================
--- trunk/src/VBox/VMM/VMMAll/IEMAllInstVexMap1.cpp.h	(revision 105218)
+++ trunk/src/VBox/VMM/VMMAll/IEMAllInstVexMap1.cpp.h	(revision 105219)
@@ -148,6 +148,6 @@
 
 /**
- * Common worker for scalar AVX/AVX2 instructions on the forms (addss,addsd,etc.):
- *     - vxxxs{s,d}    xmm0, xmm1, xmm2/mem32
+ * Common worker for scalar AVX/AVX2 instructions on the forms (addss,subss,etc.):
+ *     - vxxxss       xmm0, xmm1, xmm2/mem32
  *
  * Exceptions type 4. AVX cpuid check for 128-bit operation.
@@ -203,4 +203,69 @@
         IEM_MC_REF_XREG_XMM_CONST(puSrc1,   IEM_GET_EFFECTIVE_VVVV(pVCpu));
         IEM_MC_CALL_AVX_AIMPL_3(pfnU128, puDst, puSrc1, pr32Src2);
+        IEM_MC_MAYBE_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT();
+        IEM_MC_STORE_XREG_XMM(             IEM_GET_MODRM_REG(pVCpu, bRm), uDst);
+        IEM_MC_CLEAR_YREG_128_UP(          IEM_GET_MODRM_REG(pVCpu, bRm));
+        IEM_MC_ADVANCE_RIP_AND_FINISH();
+        IEM_MC_END();
+    }
+}
+
+
+/**
+ * Common worker for scalar AVX/AVX2 instructions on the forms (addsd,subsd,etc.):
+ *     - vxxxsd       xmm0, xmm1, xmm2/mem64
+ *
+ * Exceptions type 4. AVX cpuid check for 128-bit operation.
+ * Ignores VEX.L, from SDM:
+ *     Software should ensure VADDSD is encoded with VEX.L=0.
+ *     Encoding VADDSD with VEX.L=1 may encounter unpredictable behavior
+ *     across different processor generations.
+ */
+FNIEMOP_DEF_1(iemOpCommonAvx_Vx_Hx_R64, PFNIEMAIMPLFPAVXF3U128R64, pfnU128)
+{
+    uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
+    if (IEM_IS_MODRM_REG_MODE(bRm))
+    {
+        /*
+         * Register, register.
+         */
+        IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
+        IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx);
+        IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
+        IEM_MC_PREPARE_AVX_USAGE();
+
+        IEM_MC_LOCAL(X86XMMREG,             uDst);
+        IEM_MC_ARG_LOCAL_REF(PX86XMMREG,    puDst,  uDst,  0);
+        IEM_MC_ARG(PCX86XMMREG,             puSrc1,        1);
+        IEM_MC_REF_XREG_XMM_CONST(puSrc1,   IEM_GET_EFFECTIVE_VVVV(pVCpu));
+        IEM_MC_ARG(PCRTFLOAT64U,            pr64Src2,      2);
+        IEM_MC_REF_XREG_R64_CONST(pr64Src2, IEM_GET_MODRM_RM(pVCpu, bRm));
+        IEM_MC_CALL_AVX_AIMPL_3(pfnU128, puDst, puSrc1, pr64Src2);
+        IEM_MC_MAYBE_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT();
+        IEM_MC_STORE_XREG_XMM(             IEM_GET_MODRM_REG(pVCpu, bRm), uDst);
+        IEM_MC_CLEAR_YREG_128_UP(          IEM_GET_MODRM_REG(pVCpu, bRm));
+        IEM_MC_ADVANCE_RIP_AND_FINISH();
+        IEM_MC_END();
+    }
+    else
+    {
+        /*
+         * Register, memory.
+         */
+        IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
+        IEM_MC_LOCAL(RTGCPTR,                   GCPtrEffSrc);
+        IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
+        IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx);
+        IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
+        IEM_MC_PREPARE_AVX_USAGE();
+
+        IEM_MC_LOCAL(RTFLOAT64U,            r64Src2);
+        IEM_MC_ARG_LOCAL_REF(PCRTFLOAT64U,  pr64Src2, r64Src2,  2);
+        IEM_MC_FETCH_MEM_R64(r64Src2, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
+        IEM_MC_LOCAL(X86XMMREG,             uDst);
+        IEM_MC_ARG_LOCAL_REF(PX86XMMREG,    puDst,    uDst,     0);
+        IEM_MC_ARG(PCX86XMMREG,             puSrc1,             1);
+        IEM_MC_REF_XREG_XMM_CONST(puSrc1,   IEM_GET_EFFECTIVE_VVVV(pVCpu));
+        IEM_MC_CALL_AVX_AIMPL_3(pfnU128, puDst, puSrc1, pr64Src2);
         IEM_MC_MAYBE_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT();
         IEM_MC_STORE_XREG_XMM(             IEM_GET_MODRM_REG(pVCpu, bRm), uDst);
@@ -2921,5 +2986,11 @@
 
 /** Opcode VEX.F2.0F 0x58 - vaddsd Vsd, Hsd, Wsd */
-FNIEMOP_STUB(iemOp_vaddsd_Vsd_Hsd_Wsd);
+FNIEMOP_DEF(iemOp_vaddsd_Vsd_Hsd_Wsd)
+{
+    IEMOP_MNEMONIC3(VEX_RVM, VADDSD, vaddsd, Vpd, Hpd, Wsd, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, 0);
+    return FNIEMOP_CALL_1(iemOpCommonAvx_Vx_Hx_R64,
+                          IEM_SELECT_HOST_OR_FALLBACK(fAvx, iemAImpl_vaddsd_u128_r64, iemAImpl_vaddsd_u128_r64_fallback));
+}
+
 
 /** Opcode VEX.0F 0x59 - vmulps Vps, Hps, Wps */
