Changeset 105271 in vbox for trunk/src/VBox/VMM/VMMAll/IEMAllN8veRecompFuncs.h
- Timestamp:
- Jul 11, 2024 10:30:56 AM (5 months ago)
- File:
-
- 1 edited
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trunk/src/VBox/VMM/VMMAll/IEMAllN8veRecompFuncs.h
r105251 r105271 247 247 pReNative->fMc = 0; \ 248 248 pReNative->fCImpl = (a_fFlags); \ 249 return iemNativeEmitCImplCall0(pReNative, off, pCallEntry->idxInstr, a_fGstShwFlush, (uintptr_t)a_pfnCImpl, a_cbInstr) /** @todo not used ... */ 249 return iemNativeEmitCImplCall0(pReNative, off, pCallEntry->idxInstr, a_fGstShwFlush, (uintptr_t)a_pfnCImpl, \ 250 a_cbInstr) /** @todo not used ... */ 250 251 251 252 … … 319 320 #ifdef IEMNATIVE_WITH_LIVENESS_ANALYSIS 320 321 AssertMsg( pReNative->idxCurCall == 0 321 || IEMLIVENESS_STATE_IS_INPUT_EXPECTED(iemNativeLivenessGetStateByGstRegEx(&pReNative->paLivenessEntries[pReNative->idxCurCall - 1], IEMLIVENESSBIT_IDX_EFL_OTHER)), 322 ("Efl_Other - %u\n", iemNativeLivenessGetStateByGstRegEx(&pReNative->paLivenessEntries[pReNative->idxCurCall - 1], IEMLIVENESSBIT_IDX_EFL_OTHER))); 322 || IEMLIVENESS_STATE_IS_INPUT_EXPECTED(iemNativeLivenessGetStateByGstRegEx(&pReNative->paLivenessEntries[pReNative->idxCurCall - 1], 323 IEMLIVENESSBIT_IDX_EFL_OTHER)), 324 ("Efl_Other - %u\n", iemNativeLivenessGetStateByGstRegEx(&pReNative->paLivenessEntries[pReNative->idxCurCall - 1], 325 IEMLIVENESSBIT_IDX_EFL_OTHER))); 323 326 #endif 324 327 … … 334 337 off = iemNativeEmitTestAnyBitsInGprAndTbExitIfAnySet(pReNative, off, idxEflReg, 335 338 X86_EFL_TF | CPUMCTX_DBG_HIT_DRX_MASK | CPUMCTX_DBG_DBGF_MASK, 336 kIemNative ExitReason_ReturnWithFlags);339 kIemNativeLabelType_ReturnWithFlags); 337 340 off = iemNativeEmitAndGpr32ByImm(pReNative, off, idxEflReg, ~(uint32_t)(X86_EFL_RF | CPUMCTX_INHIBIT_SHADOW)); 338 341 off = iemNativeEmitStoreGprToVCpuU32(pReNative, off, idxEflReg, RT_UOFFSETOF(VMCPU, cpum.GstCtx.eflags)); … … 394 397 RT_UOFFSETOF(VMCPU, iem.s.ppTbLookupEntryR3)); 395 398 396 return iemNativeEmitTbExit(pReNative, off, kIemNative ExitReason_ReturnBreak);399 return iemNativeEmitTbExit(pReNative, off, kIemNativeLabelType_ReturnBreak); 397 400 398 401 #else … … 440 443 441 444 if (pReNative->idxLastCheckIrqCallNo != UINT32_MAX) 442 return iemNativeEmitTbExit(pReNative, off, kIemNative ExitReason_ReturnBreakViaLookup);443 return iemNativeEmitTbExit(pReNative, off, kIemNative ExitReason_ReturnBreakViaLookupWithIrq);445 return iemNativeEmitTbExit(pReNative, off, kIemNativeLabelType_ReturnBreakViaLookup); 446 return iemNativeEmitTbExit(pReNative, off, kIemNativeLabelType_ReturnBreakViaLookupWithIrq); 444 447 } 445 448 } 446 449 if (pReNative->idxLastCheckIrqCallNo != UINT32_MAX) 447 return iemNativeEmitTbExit(pReNative, off, kIemNative ExitReason_ReturnBreakViaLookupWithTlb);448 return iemNativeEmitTbExit(pReNative, off, kIemNative ExitReason_ReturnBreakViaLookupWithTlbAndIrq);450 return iemNativeEmitTbExit(pReNative, off, kIemNativeLabelType_ReturnBreakViaLookupWithTlb); 451 return iemNativeEmitTbExit(pReNative, off, kIemNativeLabelType_ReturnBreakViaLookupWithTlbAndIrq); 449 452 #endif 450 453 } … … 1594 1597 1595 1598 /********************************************************************************************************************************* 1596 * Emitters for changing PC/RIP/EIP/IP with a RETN (Iw) instruction (IEM_MC_RETN_AND_FINISH) (requires stack emmiters). *1599 * Emitters for changing PC/RIP/EIP/IP with a RETN (Iw) instruction (IEM_MC_RETN_AND_FINISH) (requires stack emmiters). * 1597 1600 *********************************************************************************************************************************/ 1598 1601 … … 1719 1722 : (uintptr_t)iemNativeHlpStackFetchU16; 1720 1723 uint8_t const idxRegRsp = iemNativeRegAllocTmpForGuestReg(pReNative, &off, IEMNATIVEGSTREG_GPR(X86_GREG_xSP), 1721 fFlat ? kIemNativeGstRegUse_ForUpdate : kIemNativeGstRegUse_Calculation, 1724 fFlat ? kIemNativeGstRegUse_ForUpdate 1725 : kIemNativeGstRegUse_Calculation, 1722 1726 true /*fNoVolatileRegs*/); 1723 1727 uint8_t const idxRegEffSp = fFlat ? idxRegRsp : iemNativeRegAllocTmp(pReNative, &off); 1724 1728 /** @todo can do a better job picking the register here. For cbMem >= 4 this 1725 1729 * will be the resulting register value. */ 1726 uint8_t const idxRegMemResult = iemNativeRegAllocTmp(pReNative, &off); /* pointer then value; arm64 SP += 2/4 helper too. 1730 uint8_t const idxRegMemResult = iemNativeRegAllocTmp(pReNative, &off); /* pointer then value; arm64 SP += 2/4 helper too. */ 1727 1731 1728 1732 uint32_t offFixupJumpToUseOtherBitSp = UINT32_MAX; … … 1956 1960 1957 1961 /* Allocate a temporary CR0 register. */ 1958 uint8_t const idxCr0Reg = iemNativeRegAllocTmpForGuestReg(pReNative, &off, kIemNativeGstReg_Cr0, kIemNativeGstRegUse_ReadOnly); 1962 uint8_t const idxCr0Reg = iemNativeRegAllocTmpForGuestReg(pReNative, &off, kIemNativeGstReg_Cr0, 1963 kIemNativeGstRegUse_ReadOnly); 1959 1964 1960 1965 /* … … 1963 1968 */ 1964 1969 /* Test and jump. */ 1965 off = iemNativeEmitTestAnyBitsInGprAndTbExitIfAnySet(pReNative, off, idxCr0Reg, X86_CR0_EM | X86_CR0_TS, kIemNativeExitReason_RaiseNm); 1970 off = iemNativeEmitTestAnyBitsInGprAndTbExitIfAnySet(pReNative, off, idxCr0Reg, X86_CR0_EM | X86_CR0_TS, 1971 kIemNativeLabelType_RaiseNm); 1966 1972 1967 1973 /* Free but don't flush the CR0 register. */ … … 2013 2019 2014 2020 /* Allocate a temporary CR0 register. */ 2015 uint8_t const idxCr0Reg = iemNativeRegAllocTmpForGuestReg(pReNative, &off, kIemNativeGstReg_Cr0, kIemNativeGstRegUse_Calculation); 2021 uint8_t const idxCr0Reg = iemNativeRegAllocTmpForGuestReg(pReNative, &off, kIemNativeGstReg_Cr0, 2022 kIemNativeGstRegUse_Calculation); 2016 2023 2017 2024 /* … … 2021 2028 off = iemNativeEmitAndGpr32ByImm(pReNative, off, idxCr0Reg, X86_CR0_MP | X86_CR0_TS); 2022 2029 /* Test and jump. */ 2023 off = iemNativeEmitTestIfGpr32EqualsImmAndTbExit(pReNative, off, idxCr0Reg, X86_CR0_MP | X86_CR0_TS, kIemNativeExitReason_RaiseNm); 2030 off = iemNativeEmitTestIfGpr32EqualsImmAndTbExit(pReNative, off, idxCr0Reg, X86_CR0_MP | X86_CR0_TS, 2031 kIemNativeLabelType_RaiseNm); 2024 2032 2025 2033 /* Free the CR0 register. */ … … 2065 2073 2066 2074 /* Allocate a temporary FSW register. */ 2067 uint8_t const idxFpuFswReg = iemNativeRegAllocTmpForGuestReg(pReNative, &off, kIemNativeGstReg_FpuFsw, kIemNativeGstRegUse_ReadOnly); 2075 uint8_t const idxFpuFswReg = iemNativeRegAllocTmpForGuestReg(pReNative, &off, kIemNativeGstReg_FpuFsw, 2076 kIemNativeGstRegUse_ReadOnly); 2068 2077 2069 2078 /* … … 2072 2081 */ 2073 2082 /* Test and jump. */ 2074 off = iemNativeEmitTestBitInGprAndTbExitIfSet(pReNative, off, idxFpuFswReg, X86_FSW_ES_BIT, kIemNative ExitReason_RaiseMf);2083 off = iemNativeEmitTestBitInGprAndTbExitIfSet(pReNative, off, idxFpuFswReg, X86_FSW_ES_BIT, kIemNativeLabelType_RaiseMf); 2075 2084 2076 2085 /* Free but don't flush the FSW register. */ … … 2136 2145 off = iemNativeEmitAndGpr32ByImmEx(pCodeBuf, off, idxTmpReg, X86_CR0_EM | X86_CR0_TS | X86_CR4_OSFXSR); 2137 2146 off = iemNativeEmitXorGpr32ByImmEx(pCodeBuf, off, idxTmpReg, X86_CR4_OSFXSR); 2138 off = iemNativeEmitJccTbExitEx(pReNative, pCodeBuf, off, kIemNative ExitReason_RaiseSseRelated, kIemNativeInstrCond_ne);2147 off = iemNativeEmitJccTbExitEx(pReNative, pCodeBuf, off, kIemNativeLabelType_RaiseSseRelated, kIemNativeInstrCond_ne); 2139 2148 2140 2149 #elif defined(RT_ARCH_ARM64) … … 2154 2163 /* -> idxTmpReg[0]=~OSFXSR; idxTmpReg[2]=EM; idxTmpReg[3]=TS; (the rest is zero) */ 2155 2164 off = iemNativeEmitTestIfGprIsNotZeroAndTbExitEx(pReNative, pCodeBuf, off, idxTmpReg, false /*f64Bit*/, 2156 kIemNative ExitReason_RaiseSseRelated);2165 kIemNativeLabelType_RaiseSseRelated); 2157 2166 2158 2167 #else … … 2242 2251 off = iemNativeEmitXorGpr32ByImmEx(pCodeBuf, off, idxTmpReg, ((XSAVE_C_YMM | XSAVE_C_SSE) << 2) | 2); 2243 2252 /* -> idxTmpReg[0]=CR0.TS idxTmpReg[1]=~CR4.OSXSAVE; idxTmpReg[2]=0; idxTmpReg[3]=~SSE; idxTmpReg[4]=~YMM; */ 2244 off = iemNativeEmitJccTbExitEx(pReNative, pCodeBuf, off, kIemNative ExitReason_RaiseAvxRelated, kIemNativeInstrCond_ne);2253 off = iemNativeEmitJccTbExitEx(pReNative, pCodeBuf, off, kIemNativeLabelType_RaiseAvxRelated, kIemNativeInstrCond_ne); 2245 2254 2246 2255 #elif defined(RT_ARCH_ARM64) … … 2261 2270 /* -> idxTmpReg[0]=CR0.TS; idxTmpReg[1]=~CR4.OSXSAVE; idxTmpReg[2]=~SSE; idxTmpReg[3]=~YMM; (the rest is zero) */ 2262 2271 off = iemNativeEmitTestIfGprIsNotZeroAndTbExitEx(pReNative, pCodeBuf, off, idxTmpReg, false /*f64Bit*/, 2263 kIemNative ExitReason_RaiseAvxRelated);2272 kIemNativeLabelType_RaiseAvxRelated); 2264 2273 2265 2274 #else … … 2302 2311 #endif 2303 2312 2304 uint8_t const idxRegMxCsr = iemNativeRegAllocTmpForGuestReg(pReNative, &off, kIemNativeGstReg_MxCsr, kIemNativeGstRegUse_ReadOnly); 2313 uint8_t const idxRegMxCsr = iemNativeRegAllocTmpForGuestReg(pReNative, &off, kIemNativeGstReg_MxCsr, 2314 kIemNativeGstRegUse_ReadOnly); 2305 2315 uint8_t const idxRegTmp = iemNativeRegAllocTmp(pReNative, &off); 2306 2316 … … 2316 2326 off = iemNativeEmitAndGpr32ByGpr32(pReNative, off, idxRegTmp, idxRegMxCsr); 2317 2327 off = iemNativeEmitTestAnyBitsInGprAndTbExitIfAnySet(pReNative, off, idxRegTmp, X86_MXCSR_XCPT_FLAGS, 2318 kIemNative ExitReason_RaiseSseAvxFpRelated);2328 kIemNativeLabelType_RaiseSseAvxFpRelated); 2319 2329 2320 2330 /* Free but don't flush the MXCSR register. */ … … 2353 2363 2354 2364 /* raise \#DE exception unconditionally. */ 2355 return iemNativeEmitTbExit(pReNative, off, kIemNative ExitReason_RaiseDe);2365 return iemNativeEmitTbExit(pReNative, off, kIemNativeLabelType_RaiseDe); 2356 2366 } 2357 2367 … … 2371 2381 */ 2372 2382 DECL_INLINE_THROW(uint32_t) 2373 iemNativeEmitRaiseGp0IfEffAddrUnaligned(PIEMRECOMPILERSTATE pReNative, uint32_t off, uint8_t idxInstr, uint8_t idxVarEffAddr, uint8_t cbAlign) 2383 iemNativeEmitRaiseGp0IfEffAddrUnaligned(PIEMRECOMPILERSTATE pReNative, uint32_t off, uint8_t idxInstr, 2384 uint8_t idxVarEffAddr, uint8_t cbAlign) 2374 2385 { 2375 2386 IEMNATIVE_ASSERT_VAR_IDX(pReNative, idxVarEffAddr); … … 2390 2401 2391 2402 off = iemNativeEmitTestAnyBitsInGprAndTbExitIfAnySet(pReNative, off, idxVarReg, cbAlign - 1, 2392 kIemNative ExitReason_RaiseGp0);2403 kIemNativeLabelType_RaiseGp0); 2393 2404 2394 2405 iemNativeVarRegisterRelease(pReNative, idxVarEffAddr); … … 3430 3441 #endif 3431 3442 fGstShwFlush = iemNativeCImplFlagsToGuestShadowFlushMask(pReNative->fCImpl, fGstShwFlush | RT_BIT_64(kIemNativeGstReg_Pc)); 3432 if (!(pReNative->fMc & IEM_MC_F_WITHOUT_FLAGS)) /** @todo We don't emit with-flags/without-flags variations for CIMPL calls. 3443 if (!(pReNative->fMc & IEM_MC_F_WITHOUT_FLAGS)) /** @todo We don't emit with-flags/without-flags variations for CIMPL calls. */ 3433 3444 fGstShwFlush |= RT_BIT_64(kIemNativeGstReg_EFlags); 3434 3445 iemNativeRegFlushGuestShadows(pReNative, fGstShwFlush); … … 5210 5221 5211 5222 /** Handles IEM_MC_SET_EFL_BIT/IEM_MC_CLEAR_EFL_BIT/IEM_MC_FLIP_EFL_BIT. */ 5212 DECL_INLINE_THROW(uint32_t) iemNativeEmitModifyEFlagsBit(PIEMRECOMPILERSTATE pReNative, uint32_t off, uint32_t fEflBit, IEMNATIVEMITEFLOP enmOp) 5223 DECL_INLINE_THROW(uint32_t) 5224 iemNativeEmitModifyEFlagsBit(PIEMRECOMPILERSTATE pReNative, uint32_t off, uint32_t fEflBit, IEMNATIVEMITEFLOP enmOp) 5213 5225 { 5214 5226 uint8_t const idxEflReg = iemNativeRegAllocTmpForGuestReg(pReNative, &off, kIemNativeGstReg_EFlags, … … 6679 6691 */ 6680 6692 /* Allocate a temporary PC register. */ 6681 uint8_t const idxPcReg = iemNativeRegAllocTmpForGuestReg(pReNative, &off, kIemNativeGstReg_Pc, kIemNativeGstRegUse_ForUpdate); 6693 uint8_t const idxPcReg = iemNativeRegAllocTmpForGuestReg(pReNative, &off, kIemNativeGstReg_Pc, 6694 kIemNativeGstRegUse_ForUpdate); 6682 6695 6683 6696 /* Restore the original value. */ … … 8010 8023 AssertMsg( pReNative->idxCurCall == 0 8011 8024 || IEMLIVENESS_STATE_IS_CLOBBER_EXPECTED(iemNativeLivenessGetPrevStateByGstReg(pReNative, IEMNATIVEGSTREG_GPR(idxGReg))), 8012 ("%s - %u\n", g_aGstShadowInfo[idxGReg].pszName, iemNativeLivenessGetPrevStateByGstReg(pReNative, IEMNATIVEGSTREG_GPR(idxGReg)))); 8025 ("%s - %u\n", g_aGstShadowInfo[idxGReg].pszName, 8026 iemNativeLivenessGetPrevStateByGstReg(pReNative, IEMNATIVEGSTREG_GPR(idxGReg)))); 8013 8027 #endif 8014 8028 iemNativeRegClearAndMarkAsGstRegShadow(pReNative, idxRegMemResult, IEMNATIVEGSTREG_GPR(idxGReg), off); … … 8866 8880 /* Allocate destination and source register. */ 8867 8881 uint8_t const idxSimdRegDst = iemNativeSimdRegAllocTmpForGuestSimdReg(pReNative, &off, IEMNATIVEGSTSIMDREG_SIMD(iXRegDst), 8868 kIemNativeGstSimdRegLdStSz_Low128, kIemNativeGstRegUse_ForFullWrite); 8882 kIemNativeGstSimdRegLdStSz_Low128, 8883 kIemNativeGstRegUse_ForFullWrite); 8869 8884 uint8_t const idxSimdRegSrc = iemNativeSimdRegAllocTmpForGuestSimdReg(pReNative, &off, IEMNATIVEGSTSIMDREG_SIMD(iXRegSrc), 8870 kIemNativeGstSimdRegLdStSz_Low128, kIemNativeGstRegUse_ReadOnly); 8885 kIemNativeGstSimdRegLdStSz_Low128, 8886 kIemNativeGstRegUse_ReadOnly); 8871 8887 8872 8888 off = iemNativeEmitSimdLoadVecRegFromVecRegU128(pReNative, off, idxSimdRegDst, idxSimdRegSrc); … … 8920 8936 8921 8937 uint8_t const idxSimdRegSrc = iemNativeSimdRegAllocTmpForGuestSimdReg(pReNative, &off, IEMNATIVEGSTSIMDREG_SIMD(iXReg), 8922 kIemNativeGstSimdRegLdStSz_Low128, kIemNativeGstRegUse_ReadOnly); 8938 kIemNativeGstSimdRegLdStSz_Low128, 8939 kIemNativeGstRegUse_ReadOnly); 8923 8940 8924 8941 iemNativeVarSetKindToStack(pReNative, idxDstVar); … … 8949 8966 8950 8967 uint8_t const idxSimdRegSrc = iemNativeSimdRegAllocTmpForGuestSimdReg(pReNative, &off, IEMNATIVEGSTSIMDREG_SIMD(iXReg), 8951 kIemNativeGstSimdRegLdStSz_Low128, kIemNativeGstRegUse_ReadOnly); 8968 kIemNativeGstSimdRegLdStSz_Low128, 8969 kIemNativeGstRegUse_ReadOnly); 8952 8970 8953 8971 iemNativeVarSetKindToStack(pReNative, idxDstVar); … … 8975 8993 8976 8994 uint8_t const idxSimdRegSrc = iemNativeSimdRegAllocTmpForGuestSimdReg(pReNative, &off, IEMNATIVEGSTSIMDREG_SIMD(iXReg), 8977 kIemNativeGstSimdRegLdStSz_Low128, kIemNativeGstRegUse_ReadOnly); 8995 kIemNativeGstSimdRegLdStSz_Low128, 8996 kIemNativeGstRegUse_ReadOnly); 8978 8997 8979 8998 iemNativeVarSetKindToStack(pReNative, idxDstVar); … … 9001 9020 9002 9021 uint8_t const idxSimdRegSrc = iemNativeSimdRegAllocTmpForGuestSimdReg(pReNative, &off, IEMNATIVEGSTSIMDREG_SIMD(iXReg), 9003 kIemNativeGstSimdRegLdStSz_Low128, kIemNativeGstRegUse_ReadOnly); 9022 kIemNativeGstSimdRegLdStSz_Low128, 9023 kIemNativeGstRegUse_ReadOnly); 9004 9024 9005 9025 iemNativeVarSetKindToStack(pReNative, idxDstVar); … … 9032 9052 9033 9053 uint8_t const idxSimdRegDst = iemNativeSimdRegAllocTmpForGuestSimdReg(pReNative, &off, IEMNATIVEGSTSIMDREG_SIMD(iXReg), 9034 kIemNativeGstSimdRegLdStSz_Low128, kIemNativeGstRegUse_ForFullWrite); 9054 kIemNativeGstSimdRegLdStSz_Low128, 9055 kIemNativeGstRegUse_ForFullWrite); 9035 9056 uint8_t const idxVarReg = iemNativeVarSimdRegisterAcquire(pReNative, idxSrcVar, &off, true /*fInitialized*/); 9036 9057 … … 9083 9104 9084 9105 uint8_t const idxSimdRegDst = iemNativeSimdRegAllocTmpForGuestSimdReg(pReNative, &off, IEMNATIVEGSTSIMDREG_SIMD(iXReg), 9085 kIemNativeGstSimdRegLdStSz_Low128, kIemNativeGstRegUse_ForUpdate); 9106 kIemNativeGstSimdRegLdStSz_Low128, 9107 kIemNativeGstRegUse_ForUpdate); 9086 9108 uint8_t const idxVarReg = iemNativeVarRegisterAcquire(pReNative, idxDstVar, &off, true /*fInitialized*/); 9087 9109 … … 9114 9136 9115 9137 uint8_t const idxSimdRegDst = iemNativeSimdRegAllocTmpForGuestSimdReg(pReNative, &off, IEMNATIVEGSTSIMDREG_SIMD(iXReg), 9116 kIemNativeGstSimdRegLdStSz_Low128, kIemNativeGstRegUse_ForUpdate); 9138 kIemNativeGstSimdRegLdStSz_Low128, 9139 kIemNativeGstRegUse_ForUpdate); 9117 9140 uint8_t const idxVarReg = iemNativeVarRegisterAcquire(pReNative, idxDstVar, &off, true /*fInitialized*/); 9118 9141 … … 9140 9163 9141 9164 uint8_t const idxSimdRegDst = iemNativeSimdRegAllocTmpForGuestSimdReg(pReNative, &off, IEMNATIVEGSTSIMDREG_SIMD(iXReg), 9142 kIemNativeGstSimdRegLdStSz_Low128, kIemNativeGstRegUse_ForUpdate); 9165 kIemNativeGstSimdRegLdStSz_Low128, 9166 kIemNativeGstRegUse_ForUpdate); 9143 9167 uint8_t const idxVarReg = iemNativeVarRegisterAcquire(pReNative, idxDstVar, &off, true /*fInitialized*/); 9144 9168 … … 9167 9191 9168 9192 uint8_t const idxSimdRegDst = iemNativeSimdRegAllocTmpForGuestSimdReg(pReNative, &off, IEMNATIVEGSTSIMDREG_SIMD(iXReg), 9169 kIemNativeGstSimdRegLdStSz_Low128, kIemNativeGstRegUse_ForUpdate); 9193 kIemNativeGstSimdRegLdStSz_Low128, 9194 kIemNativeGstRegUse_ForUpdate); 9170 9195 uint8_t const idxVarReg = iemNativeVarSimdRegisterAcquire(pReNative, idxSrcVar, &off, true /*fInitialized*/); 9171 9196 … … 9189 9214 { 9190 9215 /* 9191 * The iYRegSrc == iYRegDst case needs to be treated differently here, because if iYRegDst gets allocated first for the full write 9192 * it won't load the actual value from CPUMCTX. When allocating iYRegSrc afterwards it will get duplicated from the already 9193 * allocated host register for iYRegDst containing garbage. This will be catched by the guest register value checking in debug builds. 9216 * The iYRegSrc == iYRegDst case needs to be treated differently here, because 9217 * if iYRegDst gets allocated first for the full write it won't load the 9218 * actual value from CPUMCTX. When allocating iYRegSrc afterwards it will get 9219 * duplicated from the already allocated host register for iYRegDst containing 9220 * garbage. This will be catched by the guest register value checking in debug 9221 * builds. 9194 9222 */ 9195 9223 if (iYRegDst != iYRegSrc) … … 9214 9242 /* This effectively only clears the upper 128-bits of the register. */ 9215 9243 uint8_t const idxSimdReg = iemNativeSimdRegAllocTmpForGuestSimdReg(pReNative, &off, IEMNATIVEGSTSIMDREG_SIMD(iYRegDst), 9216 kIemNativeGstSimdRegLdStSz_High128, kIemNativeGstRegUse_ForFullWrite); 9244 kIemNativeGstSimdRegLdStSz_High128, 9245 kIemNativeGstRegUse_ForFullWrite); 9217 9246 9218 9247 off = iemNativeEmitSimdZeroVecRegHighU128(pReNative, off, idxSimdReg); … … 9234 9263 { 9235 9264 /* 9236 * The iYRegSrc == iYRegDst case needs to be treated differently here, because if iYRegDst gets allocated first for the full write 9237 * it won't load the actual value from CPUMCTX. When allocating iYRegSrc afterwards it will get duplicated from the already 9238 * allocated host register for iYRegDst containing garbage. This will be catched by the guest register value checking in debug builds. 9239 * iYRegSrc == iYRegDst would effectively only clear any upper 256-bits for a zmm register we don't support yet, so this is just a nop. 9265 * The iYRegSrc == iYRegDst case needs to be treated differently here, because 9266 * if iYRegDst gets allocated first for the full write it won't load the 9267 * actual value from CPUMCTX. When allocating iYRegSrc afterwards it will get 9268 * duplicated from the already allocated host register for iYRegDst containing 9269 * garbage. This will be catched by the guest register value checking in debug 9270 * builds. iYRegSrc == iYRegDst would effectively only clear any upper 256-bits 9271 * for a zmm register we don't support yet, so this is just a nop. 9240 9272 */ 9241 9273 if (iYRegDst != iYRegSrc) … … 9243 9275 /* Allocate destination and source register. */ 9244 9276 uint8_t const idxSimdRegSrc = iemNativeSimdRegAllocTmpForGuestSimdReg(pReNative, &off, IEMNATIVEGSTSIMDREG_SIMD(iYRegSrc), 9245 kIemNativeGstSimdRegLdStSz_256, kIemNativeGstRegUse_ReadOnly); 9277 kIemNativeGstSimdRegLdStSz_256, 9278 kIemNativeGstRegUse_ReadOnly); 9246 9279 uint8_t const idxSimdRegDst = iemNativeSimdRegAllocTmpForGuestSimdReg(pReNative, &off, IEMNATIVEGSTSIMDREG_SIMD(iYRegDst), 9247 kIemNativeGstSimdRegLdStSz_256, kIemNativeGstRegUse_ForFullWrite); 9280 kIemNativeGstSimdRegLdStSz_256, 9281 kIemNativeGstRegUse_ForFullWrite); 9248 9282 9249 9283 off = iemNativeEmitSimdLoadVecRegFromVecRegU256(pReNative, off, idxSimdRegDst, idxSimdRegSrc); … … 9357 9391 { 9358 9392 uint8_t const idxSimdReg = iemNativeSimdRegAllocTmpForGuestSimdReg(pReNative, &off, IEMNATIVEGSTSIMDREG_SIMD(iYReg), 9359 kIemNativeGstSimdRegLdStSz_High128, kIemNativeGstRegUse_ForFullWrite); 9393 kIemNativeGstSimdRegLdStSz_High128, 9394 kIemNativeGstRegUse_ForFullWrite); 9360 9395 9361 9396 off = iemNativeEmitSimdZeroVecRegHighU128(pReNative, off, idxSimdReg); … … 9411 9446 9412 9447 uint8_t const idxSimdRegDst = iemNativeSimdRegAllocTmpForGuestSimdReg(pReNative, &off, IEMNATIVEGSTSIMDREG_SIMD(iYReg), 9413 kIemNativeGstSimdRegLdStSz_256, kIemNativeGstRegUse_ForFullWrite); 9448 kIemNativeGstSimdRegLdStSz_256, 9449 kIemNativeGstRegUse_ForFullWrite); 9414 9450 9415 9451 uint8_t const idxVarReg = iemNativeVarSimdRegisterAcquire(pReNative, idxSrcVar, &off); … … 9437 9473 9438 9474 uint8_t const idxSimdRegDst = iemNativeSimdRegAllocTmpForGuestSimdReg(pReNative, &off, IEMNATIVEGSTSIMDREG_SIMD(iXReg), 9439 kIemNativeGstSimdRegLdStSz_256, kIemNativeGstRegUse_ForFullWrite); 9475 kIemNativeGstSimdRegLdStSz_256, 9476 kIemNativeGstRegUse_ForFullWrite); 9440 9477 9441 9478 uint8_t const idxVarReg = iemNativeVarRegisterAcquire(pReNative, idxSrcVar, &off); … … 9462 9499 9463 9500 uint8_t const idxSimdRegDst = iemNativeSimdRegAllocTmpForGuestSimdReg(pReNative, &off, IEMNATIVEGSTSIMDREG_SIMD(iXReg), 9464 kIemNativeGstSimdRegLdStSz_256, kIemNativeGstRegUse_ForFullWrite); 9501 kIemNativeGstSimdRegLdStSz_256, 9502 kIemNativeGstRegUse_ForFullWrite); 9465 9503 9466 9504 uint8_t const idxVarReg = iemNativeVarRegisterAcquire(pReNative, idxSrcVar, &off); … … 9488 9526 9489 9527 uint8_t const idxSimdRegDst = iemNativeSimdRegAllocTmpForGuestSimdReg(pReNative, &off, IEMNATIVEGSTSIMDREG_SIMD(iXReg), 9490 kIemNativeGstSimdRegLdStSz_256, kIemNativeGstRegUse_ForFullWrite); 9528 kIemNativeGstSimdRegLdStSz_256, 9529 kIemNativeGstRegUse_ForFullWrite); 9491 9530 9492 9531 uint8_t const idxVarReg = iemNativeVarRegisterAcquire(pReNative, idxSrcVar, &off); … … 9514 9553 9515 9554 uint8_t const idxSimdRegDst = iemNativeSimdRegAllocTmpForGuestSimdReg(pReNative, &off, IEMNATIVEGSTSIMDREG_SIMD(iXReg), 9516 kIemNativeGstSimdRegLdStSz_256, kIemNativeGstRegUse_ForFullWrite); 9555 kIemNativeGstSimdRegLdStSz_256, 9556 kIemNativeGstRegUse_ForFullWrite); 9517 9557 9518 9558 uint8_t const idxVarReg = iemNativeVarRegisterAcquire(pReNative, idxSrcVar, &off); … … 9540 9580 9541 9581 uint8_t const idxSimdRegDst = iemNativeSimdRegAllocTmpForGuestSimdReg(pReNative, &off, IEMNATIVEGSTSIMDREG_SIMD(iYReg), 9542 kIemNativeGstSimdRegLdStSz_256, kIemNativeGstRegUse_ForFullWrite); 9582 kIemNativeGstSimdRegLdStSz_256, 9583 kIemNativeGstRegUse_ForFullWrite); 9543 9584 9544 9585 uint8_t const idxVarReg = iemNativeVarRegisterAcquire(pReNative, idxSrcVar, &off); … … 9564 9605 9565 9606 uint8_t const idxSimdRegDst = iemNativeSimdRegAllocTmpForGuestSimdReg(pReNative, &off, IEMNATIVEGSTSIMDREG_SIMD(iYReg), 9566 kIemNativeGstSimdRegLdStSz_256, kIemNativeGstRegUse_ForFullWrite); 9607 kIemNativeGstSimdRegLdStSz_256, 9608 kIemNativeGstRegUse_ForFullWrite); 9567 9609 9568 9610 uint8_t const idxVarReg = iemNativeVarRegisterAcquire(pReNative, idxSrcVar, &off); … … 9588 9630 9589 9631 uint8_t const idxSimdRegDst = iemNativeSimdRegAllocTmpForGuestSimdReg(pReNative, &off, IEMNATIVEGSTSIMDREG_SIMD(iYReg), 9590 kIemNativeGstSimdRegLdStSz_256, kIemNativeGstRegUse_ForFullWrite); 9632 kIemNativeGstSimdRegLdStSz_256, 9633 kIemNativeGstRegUse_ForFullWrite); 9591 9634 9592 9635 uint8_t const idxVarReg = iemNativeVarRegisterAcquire(pReNative, idxSrcVar, &off); … … 9613 9656 9614 9657 uint8_t const idxSimdRegDst = iemNativeSimdRegAllocTmpForGuestSimdReg(pReNative, &off, IEMNATIVEGSTSIMDREG_SIMD(iYReg), 9615 kIemNativeGstSimdRegLdStSz_256, kIemNativeGstRegUse_ForFullWrite); 9658 kIemNativeGstSimdRegLdStSz_256, 9659 kIemNativeGstRegUse_ForFullWrite); 9616 9660 9617 9661 uint8_t const idxVarReg = iemNativeVarRegisterAcquire(pReNative, idxSrcVar, &off); … … 9638 9682 9639 9683 uint8_t const idxSimdRegDst = iemNativeSimdRegAllocTmpForGuestSimdReg(pReNative, &off, IEMNATIVEGSTSIMDREG_SIMD(iYReg), 9640 kIemNativeGstSimdRegLdStSz_256, kIemNativeGstRegUse_ForFullWrite); 9684 kIemNativeGstSimdRegLdStSz_256, 9685 kIemNativeGstRegUse_ForFullWrite); 9641 9686 9642 9687 uint8_t const idxVarReg = iemNativeVarSimdRegisterAcquire(pReNative, idxSrcVar, &off); … … 9663 9708 9664 9709 uint8_t const idxSimdRegDst = iemNativeSimdRegAllocTmpForGuestSimdReg(pReNative, &off, IEMNATIVEGSTSIMDREG_SIMD(iYReg), 9665 kIemNativeGstSimdRegLdStSz_256, kIemNativeGstRegUse_ForFullWrite); 9710 kIemNativeGstSimdRegLdStSz_256, 9711 kIemNativeGstRegUse_ForFullWrite); 9666 9712 9667 9713 uint8_t const idxVarReg = iemNativeVarRegisterAcquire(pReNative, idxSrcVar, &off); … … 9689 9735 9690 9736 uint8_t const idxSimdRegDst = iemNativeSimdRegAllocTmpForGuestSimdReg(pReNative, &off, IEMNATIVEGSTSIMDREG_SIMD(iYReg), 9691 kIemNativeGstSimdRegLdStSz_256, kIemNativeGstRegUse_ForFullWrite); 9737 kIemNativeGstSimdRegLdStSz_256, 9738 kIemNativeGstRegUse_ForFullWrite); 9692 9739 9693 9740 uint8_t const idxVarReg = iemNativeVarRegisterAcquire(pReNative, idxSrcVar, &off); … … 9715 9762 9716 9763 uint8_t const idxSimdRegDst = iemNativeSimdRegAllocTmpForGuestSimdReg(pReNative, &off, IEMNATIVEGSTSIMDREG_SIMD(iYRegDst), 9717 kIemNativeGstSimdRegLdStSz_256, kIemNativeGstRegUse_ForFullWrite); 9764 kIemNativeGstSimdRegLdStSz_256, 9765 kIemNativeGstRegUse_ForFullWrite); 9718 9766 uint8_t const idxSimdRegSrcHx = iemNativeSimdRegAllocTmpForGuestSimdReg(pReNative, &off, IEMNATIVEGSTSIMDREG_SIMD(iYRegSrcHx), 9719 kIemNativeGstSimdRegLdStSz_Low128, kIemNativeGstRegUse_ReadOnly); 9767 kIemNativeGstSimdRegLdStSz_Low128, 9768 kIemNativeGstRegUse_ReadOnly); 9720 9769 uint8_t const idxVarReg = iemNativeVarRegisterAcquire(pReNative, idxSrcVar, &off); 9721 9770 … … 9744 9793 9745 9794 uint8_t const idxSimdRegDst = iemNativeSimdRegAllocTmpForGuestSimdReg(pReNative, &off, IEMNATIVEGSTSIMDREG_SIMD(iYRegDst), 9746 kIemNativeGstSimdRegLdStSz_256, kIemNativeGstRegUse_ForFullWrite); 9795 kIemNativeGstSimdRegLdStSz_256, 9796 kIemNativeGstRegUse_ForFullWrite); 9747 9797 uint8_t const idxSimdRegSrcHx = iemNativeSimdRegAllocTmpForGuestSimdReg(pReNative, &off, IEMNATIVEGSTSIMDREG_SIMD(iYRegSrcHx), 9748 kIemNativeGstSimdRegLdStSz_Low128, kIemNativeGstRegUse_ReadOnly); 9798 kIemNativeGstSimdRegLdStSz_Low128, 9799 kIemNativeGstRegUse_ReadOnly); 9749 9800 uint8_t const idxVarReg = iemNativeVarRegisterAcquire(pReNative, idxSrcVar, &off); 9750 9801 … … 9771 9822 { 9772 9823 uint8_t const idxSimdRegDst = iemNativeSimdRegAllocTmpForGuestSimdReg(pReNative, &off, IEMNATIVEGSTSIMDREG_SIMD(iXReg), 9773 kIemNativeGstSimdRegLdStSz_Low128, kIemNativeGstRegUse_ForUpdate); 9824 kIemNativeGstSimdRegLdStSz_Low128, 9825 kIemNativeGstRegUse_ForUpdate); 9774 9826 9775 9827 /** @todo r=aeichner For certain bit combinations we could reduce the number of emitted instructions. */ … … 9804 9856 9805 9857 uint8_t const idxSimdRegSrc = iemNativeSimdRegAllocTmpForGuestSimdReg(pReNative, &off, IEMNATIVEGSTSIMDREG_SIMD(iYRegSrc), 9806 kIemNativeGstSimdRegLdStSz_256, kIemNativeGstRegUse_ReadOnly); 9858 kIemNativeGstSimdRegLdStSz_256, 9859 kIemNativeGstRegUse_ReadOnly); 9807 9860 uint8_t const idxVarReg = iemNativeVarSimdRegisterAcquire(pReNative, idxDstVar, &off); 9808 9861 … … 9831 9884 9832 9885 uint8_t const idxSimdRegDst = iemNativeSimdRegAllocTmpForGuestSimdReg(pReNative, &off, IEMNATIVEGSTSIMDREG_SIMD(iYRegDst), 9833 kIemNativeGstSimdRegLdStSz_256, kIemNativeGstRegUse_ForFullWrite); 9886 kIemNativeGstSimdRegLdStSz_256, 9887 kIemNativeGstRegUse_ForFullWrite); 9834 9888 uint8_t const idxVarRegSrc = iemNativeVarSimdRegisterAcquire(pReNative, idxSrcVar, &off, true /*fInitalized*/); 9835 9889 … … 9974 10028 * Do all the call setup and cleanup. 9975 10029 */ 9976 off = iemNativeEmitCallCommon(pReNative, off, cArgs + IEM_SSE_AIMPL_HIDDEN_ARGS, IEM_SSE_AIMPL_HIDDEN_ARGS, false /*fFlushPendingWrites*/); 10030 off = iemNativeEmitCallCommon(pReNative, off, cArgs + IEM_SSE_AIMPL_HIDDEN_ARGS, IEM_SSE_AIMPL_HIDDEN_ARGS, 10031 false /*fFlushPendingWrites*/); 9977 10032 9978 10033 /* … … 10020 10075 /** Emits code for IEM_MC_CALL_SSE_AIMPL_3. */ 10021 10076 DECL_INLINE_THROW(uint32_t) 10022 iemNativeEmitCallSseAImpl3(PIEMRECOMPILERSTATE pReNative, uint32_t off, uintptr_t pfnAImpl, uint8_t idxArg0, uint8_t idxArg1, uint8_t idxArg2) 10077 iemNativeEmitCallSseAImpl3(PIEMRECOMPILERSTATE pReNative, uint32_t off, uintptr_t pfnAImpl, 10078 uint8_t idxArg0, uint8_t idxArg1, uint8_t idxArg2) 10023 10079 { 10024 10080 IEMNATIVE_ASSERT_ARG_VAR_IDX(pReNative, idxArg0, 0 + IEM_SSE_AIMPL_HIDDEN_ARGS); … … 10051 10107 /** Emits code for IEM_MC_CALL_AVX_AIMPL_3. */ 10052 10108 DECL_INLINE_THROW(uint32_t) 10053 iemNativeEmitCallAvxAImpl3(PIEMRECOMPILERSTATE pReNative, uint32_t off, uintptr_t pfnAImpl, uint8_t idxArg0, uint8_t idxArg1, uint8_t idxArg2) 10109 iemNativeEmitCallAvxAImpl3(PIEMRECOMPILERSTATE pReNative, uint32_t off, uintptr_t pfnAImpl, 10110 uint8_t idxArg0, uint8_t idxArg1, uint8_t idxArg2) 10054 10111 { 10055 10112 IEMNATIVE_ASSERT_ARG_VAR_IDX(pReNative, idxArg0, 0 + IEM_AVX_AIMPL_HIDDEN_ARGS); … … 10058 10115 return iemNativeEmitCallSseAvxAImplCommon(pReNative, off, pfnAImpl, 3); 10059 10116 } 10117 10118 10060 10119 #endif /* IEMNATIVE_WITH_SIMD_REG_ALLOCATOR */ 10061 10120
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