Index: trunk/src/VBox/VMM/VMMAll/IEMAllAImpl.asm
===================================================================
--- trunk/src/VBox/VMM/VMMAll/IEMAllAImpl.asm	(revision 105307)
+++ trunk/src/VBox/VMM/VMMAll/IEMAllAImpl.asm	(revision 105309)
@@ -6634,6 +6634,7 @@
 ENDPROC iemAImpl_cvtsi2ss_r32_i32
 
-;;
-; cvtsi2ss instruction - 64-bit variant.
+
+;;
+; vcvtsi2ss instruction - 32-bit variant.
 ;
 ; @return   R0_32   The new MXCSR value of the guest.
@@ -6641,4 +6642,28 @@
 ; @param    A1      Pointer to the result operand (output).
 ; @param    A2      Pointer to the second operand (input).
+; @param    A3      Pointer to the third operand (input).
+;
+BEGINPROC_FASTCALL iemAImpl_vcvtsi2ss_u128_i32, 16
+        PROLOGUE_3_ARGS
+        IEMIMPL_AVX_PROLOGUE
+        SSE_AVX_LD_MXCSR A0_32
+
+        movdqu    xmm0, [A2]
+        vcvtsi2ss xmm0, xmm0, dword [A3]
+        movdqu    [A1], xmm0
+
+        SSE_AVX_ST_MXCSR R0_32, A0_32
+        IEMIMPL_AVX_EPILOGUE
+        EPILOGUE_3_ARGS
+ENDPROC iemAImpl_vcvtsi2ss_u128_i32
+
+
+;;
+; cvtsi2ss instruction - 64-bit variant.
+;
+; @return   R0_32   The new MXCSR value of the guest.
+; @param    A0_32   The guest's MXCSR register value to use.
+; @param    A1      Pointer to the result operand (output).
+; @param    A2      Pointer to the second operand (input).
 ;
 BEGINPROC_FASTCALL iemAImpl_cvtsi2ss_r32_i64, 16
@@ -6654,4 +6679,28 @@
         EPILOGUE_3_ARGS
 ENDPROC iemAImpl_cvtsi2ss_r32_i64
+
+
+;;
+; vcvtsi2ss instruction - 64-bit variant.
+;
+; @return   R0_32   The new MXCSR value of the guest.
+; @param    A0_32   The guest's MXCSR register value to use.
+; @param    A1      Pointer to the result operand (output).
+; @param    A2      Pointer to the second operand (input).
+; @param    A3      Pointer to the third operand (input).
+;
+BEGINPROC_FASTCALL iemAImpl_vcvtsi2ss_u128_i64, 16
+        PROLOGUE_3_ARGS
+        IEMIMPL_AVX_PROLOGUE
+        SSE_AVX_LD_MXCSR A0_32
+
+        movdqu    xmm0, [A2]
+        vcvtsi2ss xmm0, xmm0, qword [A3]
+        movdqu    [A1], xmm0
+
+        SSE_AVX_ST_MXCSR R0_32, A0_32
+        IEMIMPL_AVX_EPILOGUE
+        EPILOGUE_3_ARGS
+ENDPROC iemAImpl_vcvtsi2ss_u128_i64
 
 
Index: trunk/src/VBox/VMM/VMMAll/IEMAllAImplC.cpp
===================================================================
--- trunk/src/VBox/VMM/VMMAll/IEMAllAImplC.cpp	(revision 105307)
+++ trunk/src/VBox/VMM/VMMAll/IEMAllAImplC.cpp	(revision 105309)
@@ -19113,5 +19113,5 @@
 
 /**
- * CVTSI2SS
+ * [V]CVTSI2SS
  */
 #ifdef IEM_WITHOUT_ASSEMBLY
@@ -19131,4 +19131,26 @@
 }
 #endif
+
+
+IEM_DECL_IMPL_DEF(uint32_t, iemAImpl_vcvtsi2ss_u128_i32_fallback, (uint32_t uMxCsrIn, PX86XMMREG puDst, PCX86XMMREG puSrc1, const int32_t *pi32Src2))
+{
+    puDst->au32[1] = puSrc1->au32[1];
+    puDst->au64[1] = puSrc1->au64[1];
+
+    softfloat_state_t SoftState = IEM_SOFTFLOAT_STATE_INITIALIZER_FROM_MXCSR(uMxCsrIn);
+    float32_t r32Res = i32_to_f32(*pi32Src2, &SoftState);
+    return iemSseSoftStateAndR32ToMxcsrAndIprtResult(&SoftState, r32Res, &puDst->ar32[0], uMxCsrIn);
+}
+
+
+IEM_DECL_IMPL_DEF(uint32_t, iemAImpl_vcvtsi2ss_u128_i64_fallback, (uint32_t uMxCsrIn, PX86XMMREG puDst, PCX86XMMREG puSrc1, const int64_t *pi64Src2))
+{
+    puDst->au32[1] = puSrc1->au32[1];
+    puDst->au64[1] = puSrc1->au64[1];
+
+    softfloat_state_t SoftState = IEM_SOFTFLOAT_STATE_INITIALIZER_FROM_MXCSR(uMxCsrIn);
+    float32_t r32Res = i64_to_f32(*pi64Src2, &SoftState);
+    return iemSseSoftStateAndR32ToMxcsrAndIprtResult(&SoftState, r32Res, &puDst->ar32[0], uMxCsrIn);
+}
 
 
Index: trunk/src/VBox/VMM/VMMAll/IEMAllInstVexMap1.cpp.h
===================================================================
--- trunk/src/VBox/VMM/VMMAll/IEMAllInstVexMap1.cpp.h	(revision 105307)
+++ trunk/src/VBox/VMM/VMMAll/IEMAllInstVexMap1.cpp.h	(revision 105309)
@@ -2381,6 +2381,115 @@
 /** Opcode VEX.0F 0x2a - invalid */
 /** Opcode VEX.66.0F 0x2a - invalid */
+
+
 /** Opcode VEX.F3.0F 0x2a - vcvtsi2ss Vss, Hss, Ey */
-FNIEMOP_STUB(iemOp_vcvtsi2ss_Vss_Hss_Ey);
+FNIEMOP_DEF(iemOp_vcvtsi2ss_Vss_Hss_Ey)
+{
+    IEMOP_MNEMONIC3(VEX_RVM, VCVTSI2SS, vcvtsi2ss, Vps, Hps, Ey, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, 0);
+    IEMOP_HLP_IGNORE_VEX_W_PREFIX_IF_NOT_IN_64BIT();
+    uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
+    if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_REX_W)
+    {
+        if (IEM_IS_MODRM_REG_MODE(bRm))
+        {
+            /* XMM, greg64 */
+            IEM_MC_BEGIN(IEM_MC_F_64BIT, 0);
+            IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx);
+            IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
+            IEM_MC_PREPARE_AVX_USAGE();
+
+            IEM_MC_LOCAL(X86XMMREG,             uDst);
+            IEM_MC_ARG_LOCAL_REF(PX86XMMREG,    puDst,  uDst,  0);
+            IEM_MC_ARG(PCX86XMMREG,             puSrc1,        1);
+            IEM_MC_REF_XREG_XMM_CONST(puSrc1,   IEM_GET_EFFECTIVE_VVVV(pVCpu));
+            IEM_MC_ARG(const int64_t *,         pi64Src2,      2);
+            IEM_MC_REF_GREG_I64_CONST(pi64Src2, IEM_GET_MODRM_RM(pVCpu, bRm));
+            IEM_MC_CALL_AVX_AIMPL_3(IEM_SELECT_HOST_OR_FALLBACK(fAvx, iemAImpl_vcvtsi2ss_u128_i64, iemAImpl_vcvtsi2ss_u128_i64_fallback),
+                                    puDst, puSrc1, pi64Src2);
+            IEM_MC_MAYBE_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT();
+            IEM_MC_STORE_XREG_XMM(             IEM_GET_MODRM_REG(pVCpu, bRm), uDst);
+            IEM_MC_CLEAR_YREG_128_UP(          IEM_GET_MODRM_REG(pVCpu, bRm));
+            IEM_MC_ADVANCE_RIP_AND_FINISH();
+            IEM_MC_END();
+        }
+        else
+        {
+            /* XMM, [mem64] */
+            IEM_MC_BEGIN(IEM_MC_F_64BIT, 0);
+            IEM_MC_LOCAL(RTGCPTR,    GCPtrEffSrc);
+            IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
+            IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx);
+            IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
+            IEM_MC_PREPARE_AVX_USAGE();
+
+            IEM_MC_LOCAL(X86XMMREG,             uDst);
+            IEM_MC_ARG_LOCAL_REF(PX86XMMREG,    puDst,  uDst,          0);
+            IEM_MC_ARG(PCX86XMMREG,             puSrc1,                1);
+            IEM_MC_REF_XREG_XMM_CONST(puSrc1,   IEM_GET_EFFECTIVE_VVVV(pVCpu));
+            IEM_MC_LOCAL(int64_t,    i64Src2);
+            IEM_MC_ARG_LOCAL_REF(const int64_t *,   pi64Src2, i64Src2, 2);
+            IEM_MC_FETCH_MEM_I64(i64Src2, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
+            IEM_MC_CALL_AVX_AIMPL_3(IEM_SELECT_HOST_OR_FALLBACK(fAvx, iemAImpl_vcvtsi2ss_u128_i64, iemAImpl_vcvtsi2ss_u128_i64_fallback),
+                                    puDst, puSrc1, pi64Src2);
+            IEM_MC_MAYBE_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT();
+            IEM_MC_STORE_XREG_XMM(             IEM_GET_MODRM_REG(pVCpu, bRm), uDst);
+            IEM_MC_CLEAR_YREG_128_UP(          IEM_GET_MODRM_REG(pVCpu, bRm));
+            IEM_MC_ADVANCE_RIP_AND_FINISH();
+            IEM_MC_END();
+        }
+    }
+    else
+    {
+        if (IEM_IS_MODRM_REG_MODE(bRm))
+        {
+            /* XMM, greg32 */
+            IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
+            IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx);
+            IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
+            IEM_MC_PREPARE_AVX_USAGE();
+
+            IEM_MC_LOCAL(X86XMMREG,             uDst);
+            IEM_MC_ARG_LOCAL_REF(PX86XMMREG,    puDst,  uDst,  0);
+            IEM_MC_ARG(PCX86XMMREG,             puSrc1,        1);
+            IEM_MC_REF_XREG_XMM_CONST(puSrc1,   IEM_GET_EFFECTIVE_VVVV(pVCpu));
+            IEM_MC_ARG(const int32_t *,         pi32Src2,      2);
+            IEM_MC_REF_GREG_I32_CONST(pi32Src2, IEM_GET_MODRM_RM(pVCpu, bRm));
+            IEM_MC_CALL_AVX_AIMPL_3(IEM_SELECT_HOST_OR_FALLBACK(fAvx, iemAImpl_vcvtsi2ss_u128_i32, iemAImpl_vcvtsi2ss_u128_i32_fallback),
+                                    puDst, puSrc1, pi32Src2);
+            IEM_MC_MAYBE_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT();
+            IEM_MC_STORE_XREG_XMM(             IEM_GET_MODRM_REG(pVCpu, bRm), uDst);
+            IEM_MC_CLEAR_YREG_128_UP(          IEM_GET_MODRM_REG(pVCpu, bRm));
+            IEM_MC_ADVANCE_RIP_AND_FINISH();
+            IEM_MC_END();
+        }
+        else
+        {
+            /* greg, [mem32] */
+            IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
+            IEM_MC_LOCAL(RTGCPTR,    GCPtrEffSrc);
+            IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
+            IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx);
+            IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
+            IEM_MC_PREPARE_AVX_USAGE();
+
+            IEM_MC_LOCAL(X86XMMREG,             uDst);
+            IEM_MC_ARG_LOCAL_REF(PX86XMMREG,    puDst,  uDst,          0);
+            IEM_MC_ARG(PCX86XMMREG,             puSrc1,                1);
+            IEM_MC_REF_XREG_XMM_CONST(puSrc1,   IEM_GET_EFFECTIVE_VVVV(pVCpu));
+            IEM_MC_LOCAL(int32_t,    i32Src2);
+            IEM_MC_ARG_LOCAL_REF(const int32_t *,   pi32Src2, i32Src2, 2);
+            IEM_MC_FETCH_MEM_I32(i32Src2, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
+            IEM_MC_CALL_AVX_AIMPL_3(IEM_SELECT_HOST_OR_FALLBACK(fAvx, iemAImpl_vcvtsi2ss_u128_i32, iemAImpl_vcvtsi2ss_u128_i32_fallback),
+                                    puDst, puSrc1, pi32Src2);
+            IEM_MC_MAYBE_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT();
+            IEM_MC_STORE_XREG_XMM(             IEM_GET_MODRM_REG(pVCpu, bRm), uDst);
+            IEM_MC_CLEAR_YREG_128_UP(          IEM_GET_MODRM_REG(pVCpu, bRm));
+            IEM_MC_ADVANCE_RIP_AND_FINISH();
+            IEM_MC_END();
+        }
+    }
+}
+
+
 /** Opcode VEX.F2.0F 0x2a - vcvtsi2sd Vsd, Hsd, Ey */
 FNIEMOP_STUB(iemOp_vcvtsi2sd_Vsd_Hsd_Ey);
