Changeset 105364 in vbox

Timestamp:

Jul 17, 2024 7:32:44 AM (10 months ago)

Author:

vboxsync

svn:sync-xref-src-repo-rev:

164017

Message:

VMM: Expose FMA and F16C instruction set extensions if available and nested paging is supported, bugref:10726

Location:

trunk

Files:

• include/VBox/vmm/cpum-x86-amd64.h (modified) (2 diffs)
• src/VBox/VMM/VMMAll/CPUMAllCpuId.cpp (modified) (2 diffs)
• src/VBox/VMM/VMMR3/CPUMR3CpuId.cpp (modified) (5 diffs)

trunk/include/VBox/vmm/cpum-x86-amd64.h

@@ -889 +889 @@
     /** Support ADX instructions. */
     uint32_t        fAdx : 1;
+    /** Supports FMA. */
+    uint32_t        fFma : 1;
+    /** Supports F16C. */
+    uint32_t        fF16c : 1;
 
     /** Supports AMD 3DNow instructions. */
@@ -952 +956 @@
     /** Alignment padding / reserved for future use (96 bits total, plus 12 bytes
      *  prior to the bit fields -> total of 24 bytes) */
-    uint32_t        fPadding0 : 21;
+    uint32_t        fPadding0 : 19;
 
 

trunk/src/VBox/VMM/VMMAll/CPUMAllCpuId.cpp

@@ -1449 +1449 @@
         pFeatures->fSse3                = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_SSE3);
         pFeatures->fSsse3               = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_SSSE3);
+        pFeatures->fFma                 = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_FMA);
         pFeatures->fSse41               = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_SSE4_1);
         pFeatures->fSse42               = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_SSE4_2);
@@ -1467 +1468 @@
         pFeatures->fPclMul              = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_PCLMUL);
         pFeatures->fMovBe               = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_MOVBE);
+        pFeatures->fF16c                = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_F16C);
         if (pFeatures->fVmx)
             cpumExplodeVmxFeatures(&pMsrs->hwvirt.vmx, pFeatures);

trunk/src/VBox/VMM/VMMR3/CPUMR3CpuId.cpp

@@ -1064 +1064 @@
     CPUMISAEXTCFG   enmMdsClear;
     CPUMISAEXTCFG   enmArchCapMsr;
+    CPUMISAEXTCFG   enmFma;
+    CPUMISAEXTCFG   enmF16c;
 
     CPUMISAEXTCFG   enmAbm;
@@ -1399 +1401 @@
                            | X86_CPUID_FEATURE_ECX_SSSE3
                            //| X86_CPUID_FEATURE_ECX_CNTXID - no L1 context id (MSR++).
-                           //| X86_CPUID_FEATURE_ECX_FMA   - not implemented yet.
+                           | PASSTHRU_FEATURE(pConfig->enmFma, pHstFeat->fFma, X86_CPUID_FEATURE_ECX_FMA)
                            | PASSTHRU_FEATURE(pConfig->enmCmpXchg16b, pHstFeat->fCmpXchg16b, X86_CPUID_FEATURE_ECX_CX16)
                            /* ECX Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
@@ -1416 +1418 @@
                            //| X86_CPUID_FEATURE_ECX_OSXSAVE - mirrors CR4.OSXSAVE state, set dynamically.
                            | PASSTHRU_FEATURE(pConfig->enmAvx, pHstFeat->fAvx, X86_CPUID_FEATURE_ECX_AVX)
-                           //| X86_CPUID_FEATURE_ECX_F16C  - not implemented yet.
+                           | PASSTHRU_FEATURE(pConfig->enmF16c, pHstFeat->fFma, X86_CPUID_FEATURE_ECX_F16C)
                            | PASSTHRU_FEATURE_TODO(pConfig->enmRdRand, X86_CPUID_FEATURE_ECX_RDRAND)
                            //| X86_CPUID_FEATURE_ECX_HVP   - Set explicitly later.
@@ -2850 +2852 @@
                                   "|INVPCID"
                                   "|FlushCmdMsr"
+                                  "|FMA"
+                                  "|F16C"
                                   "|ABM"
                                   "|SSE4A"
@@ -3034 +3038 @@
      */
     rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "ArchCapMsr", &pConfig->enmArchCapMsr, CPUMISAEXTCFG_ENABLED_SUPPORTED_OR_NOT_AMD64);
+    AssertLogRelRCReturn(rc, rc);
+
+    /** @cfgm{/CPUM/IsaExts/FMA, boolean, depends}
+     * Expose the FMA instruction set extensions to the guest if available and
+     * XSAVE is exposed too. For the time being the default is to only expose this
+     * to VMs with nested paging and AMD-V or unrestricted guest execution mode.
+     */
+    rc = cpumR3CpuIdReadIsaExtCfgEx(pVM, pIsaExts, "FMA", &pConfig->enmFma, fNestedPagingAndFullGuestExec /* temporarily */,
+                                    fMayHaveXSave && pConfig->enmXSave && (fXStateHostMask & XSAVE_C_YMM) /*fAllowed*/);
+    AssertLogRelRCReturn(rc, rc);
+
+    /** @cfgm{/CPUM/IsaExts/F16C, boolean, depends}
+     * Expose the F16C instruction set extensions to the guest if available and
+     * XSAVE is exposed too. For the time being the default is to only expose this
+     * to VMs with nested paging and AMD-V or unrestricted guest execution mode.
+     */
+    rc = cpumR3CpuIdReadIsaExtCfgEx(pVM, pIsaExts, "F16C", &pConfig->enmF16c, fNestedPagingAndFullGuestExec /* temporarily */,
+                                    fMayHaveXSave && pConfig->enmXSave && (fXStateHostMask & XSAVE_C_YMM) /*fAllowed*/);
     AssertLogRelRCReturn(rc, rc);