Changeset 105407 in vbox

Timestamp:

Jul 18, 2024 5:54:12 PM (6 months ago)

Author:

vboxsync

Message:

VMM/IEM: Implement native emitters for pmovzxbw/pmovzxwd/pmovzxdq/pmovsxbw/pmovsxwd/pmovsxdq instruction emulations, bugref:10652 [fix, the register allocation order is important]

File:

• trunk/src/VBox/VMM/VMMAll/target-x86/IEMAllN8veEmit-x86.h (modified) (2 diffs)

trunk/src/VBox/VMM/VMMAll/target-x86/IEMAllN8veEmit-x86.h

@@ -2451 +2451 @@
                                                 uint8_t const idxSimdGstRegDst, uint8_t const idxSimdGstRegSrc) \
     { \
+        /* \
+         * The order of register allocation is important here when idxSimdGstRegSrc == idxSimdGstRegDst, \
+         * if _ForFullWrite is allocated first the register won't be initialized. \
+         */ \
+        uint8_t const idxSimdRegSrc = iemNativeSimdRegAllocTmpForGuestSimdReg(pReNative, &off, IEMNATIVEGSTSIMDREG_SIMD(idxSimdGstRegSrc), \
+                                                                              kIemNativeGstSimdRegLdStSz_Low128, kIemNativeGstRegUse_ReadOnly); \
         uint8_t const idxSimdRegDst = iemNativeSimdRegAllocTmpForGuestSimdReg(pReNative, &off, IEMNATIVEGSTSIMDREG_SIMD(idxSimdGstRegDst), \
                                                                               kIemNativeGstSimdRegLdStSz_Low128, kIemNativeGstRegUse_ForFullWrite); \
-        uint8_t const idxSimdRegSrc = iemNativeSimdRegAllocTmpForGuestSimdReg(pReNative, &off, IEMNATIVEGSTSIMDREG_SIMD(idxSimdGstRegSrc), \
-                                                                              kIemNativeGstSimdRegLdStSz_Low128, kIemNativeGstRegUse_ReadOnly); \
         PIEMNATIVEINSTR const pCodeBuf = iemNativeInstrBufEnsure(pReNative, off, 6); \
         pCodeBuf[off++] = X86_OP_PRF_SIZE_OP; \
@@ -2506 +2510 @@
                                                 uint8_t const idxSimdGstRegDst, uint8_t const idxSimdGstRegSrc) \
     { \
+        /* \
+         * The order of register allocation is important here when idxSimdGstRegSrc == idxSimdGstRegDst, \
+         * if _ForFullWrite is allocated first the register won't be initialized. \
+         */ \
+        uint8_t const idxSimdRegSrc = iemNativeSimdRegAllocTmpForGuestSimdReg(pReNative, &off, IEMNATIVEGSTSIMDREG_SIMD(idxSimdGstRegSrc), \
+                                                                              kIemNativeGstSimdRegLdStSz_Low128, kIemNativeGstRegUse_ReadOnly); \
         uint8_t const idxSimdRegDst = iemNativeSimdRegAllocTmpForGuestSimdReg(pReNative, &off, IEMNATIVEGSTSIMDREG_SIMD(idxSimdGstRegDst), \
                                                                               kIemNativeGstSimdRegLdStSz_Low128, kIemNativeGstRegUse_ForFullWrite); \
-        uint8_t const idxSimdRegSrc = iemNativeSimdRegAllocTmpForGuestSimdReg(pReNative, &off, IEMNATIVEGSTSIMDREG_SIMD(idxSimdGstRegSrc), \
-                                                                              kIemNativeGstSimdRegLdStSz_Low128, kIemNativeGstRegUse_ReadOnly); \
         PIEMNATIVEINSTR const pCodeBuf = iemNativeInstrBufEnsure(pReNative, off, 1); \
         pCodeBuf[off++] = Armv8A64MkVecInstrUShll(idxSimdRegDst, idxSimdRegSrc, 0, (a_ArmElemSz), (a_fArmUnsigned)); \