Changeset 105441 in vbox

Timestamp:

Jul 23, 2024 10:55:43 AM (9 months ago)

Author:

vboxsync

svn:sync-xref-src-repo-rev:

164098

Message:

include/{x86.h,armv8.h}: Some additional definitions for MXCSR and FPCR registers, bugref:10652

Location:

trunk/include/iprt

Files:

• armv8.h (modified) (2 diffs)
• x86.h (modified) (3 diffs)

trunk/include/iprt/armv8.h

@@ -2374 +2374 @@
 /** Bit 0 - Flush Inputs to Zero when FEAT_AFP is supported. */
 #define ARMV8_FPCR_FIZ                                          RT_BIT_64(0)
+#define ARMV8_FPCR_FIZ_BIT                                      0
 /** Bit 1 - Alternate Handling of floating-point numbers when FEAT_AFP is supported. */
 #define ARMV8_FPCR_AH                                           RT_BIT_64(1)
+#define ARMV8_FPCR_AH_BIT                                       1
 /** Bit 2 - Controls how the output elements other than the lowest element of the vector are determined for
  * Advanced SIMD scalar instructions, when FEAT_AFP is supported. */
 #define ARMV8_FPCR_NEP                                          RT_BIT_64(2)
+#define ARMV8_FPCR_NEP_BIT                                      2
 /* Bit 3 - 7 - Reserved.*/
 /** Bit 8 - Invalid Operation floating-point exception trap enable. */
 #define ARMV8_FPCR_IOE                                          RT_BIT_64(8)
+#define ARMV8_FPCR_IOE_BIT                                      8
 /** Bit 9 - Divide by Zero floating-point exception trap enable. */
 #define ARMV8_FPCR_DZE                                          RT_BIT_64(9)
+#define ARMV8_FPCR_DZE_BIT                                      9
 /** Bit 10 - Overflow floating-point exception trap enable. */
 #define ARMV8_FPCR_OFE                                          RT_BIT_64(10)
+#define ARMV8_FPCR_OFE_BIT                                      10
 /** Bit 11 - Underflow floating-point exception trap enable. */
 #define ARMV8_FPCR_UFE                                          RT_BIT_64(11)
+#define ARMV8_FPCR_UFE_BIT                                      11
 /** Bit 12 - Inexact floating-point exception trap enable. */
 #define ARMV8_FPCR_IXE                                          RT_BIT_64(12)
+#define ARMV8_FPCR_IXE_BIT                                      12
 /** Bit 13 - Controls numeric behavior of BFloat16 dot productions calculations performed,
  * supported when FEAT_EBF16 is supported. */
 #define ARMV8_FPCR_EBF                                          RT_BIT_64(13)
+#define ARMV8_FPCR_EBF_BIT                                      13
 /* Bit 14 - Reserved */
 /** Bit 15 - Input Denormal floating-point exception trap enable. */
 #define ARMV8_FPCR_IDE                                          RT_BIT_64(15)
+#define ARMV8_FPCR_IDE_BIT                                      15
 /* Bit 16 - 18 - Reserved for AArch64 (Len field for AArch32). */
 /** Bit 19 - Flushing denormalized numbers to zero control bit on half-precision data-processing instructions,
  * available when FEAT_FP16 is supported. */
 #define ARMV8_FPCR_FZ16                                         RT_BIT_64(19)
+#define ARMV8_FPCR_FZ16_BIT                                       19
 /* Bit 20 - 21 - Reserved for AArch64 (Stride field dor AArch32). */
 /** Bit 22 - 23 - Rounding Mode control field. */
@@ -2414 +2425 @@
 /** Bit 24 - Flushing denormalized numbers to zero control bit. */
 #define ARMV8_FPCR_FZ                                           RT_BIT_64(24)
+#define ARMV8_FPCR_FZ_BIT                                       24
 /** Bit 25 - Default NaN use for NaN propagation. */
 #define ARMV8_FPCR_DN                                           RT_BIT_64(25)
+#define ARMV8_FPCR_DN_BIT                                       25
 /** Bit 26 - Alternative half-precision control bit. */
 #define ARMV8_FPCR_AHP                                          RT_BIT_64(26)
+#define ARMV8_FPCR_AHP_BIT                                      26
 /* Bit 27 - 63 - Reserved. */
 /** @} */

trunk/include/iprt/x86.h

@@ -3843 +3843 @@
 /** Exception Flag: Invalid operation.  */
 #define X86_MXCSR_IE          RT_BIT_32(0)
+#define X86_MXCSR_IE_BIT      0
 /** Exception Flag: Denormalized operand.  */
 #define X86_MXCSR_DE          RT_BIT_32(1)
+#define X86_MXCSR_DE_BIT      1
 /** Exception Flag: Zero divide.  */
 #define X86_MXCSR_ZE          RT_BIT_32(2)
+#define X86_MXCSR_ZE_BIT      2
 /** Exception Flag: Overflow.  */
 #define X86_MXCSR_OE          RT_BIT_32(3)
+#define X86_MXCSR_OE_BIT      3
 /** Exception Flag: Underflow.  */
 #define X86_MXCSR_UE          RT_BIT_32(4)
+#define X86_MXCSR_EU_BIT      4
 /** Exception Flag: Precision.  */
 #define X86_MXCSR_PE          RT_BIT_32(5)
+#define X86_MXCSR_PE_BIT      5
 /** Exception Flags: mask */
 #define X86_MXCSR_XCPT_FLAGS  UINT32_C(0x003f)
@@ -3858 +3864 @@
 /** Denormals are zero. */
 #define X86_MXCSR_DAZ         RT_BIT_32(6)
+#define X86_MXCSR_DAZ_BIT     6
 
 /** Exception Mask: Invalid operation. */
 #define X86_MXCSR_IM          RT_BIT_32(7)
+#define X86_MXCSR_IM_BIT      7
 /** Exception Mask: Denormalized operand. */
 #define X86_MXCSR_DM          RT_BIT_32(8)
+#define X86_MXCSR_DM_BIT      8
 /** Exception Mask: Zero divide.  */
 #define X86_MXCSR_ZM          RT_BIT_32(9)
+#define X86_MXCSR_ZM_BIT      9
 /** Exception Mask: Overflow.  */
 #define X86_MXCSR_OM          RT_BIT_32(10)
+#define X86_MXCSR_OM_BIT      10
 /** Exception Mask: Underflow.  */
 #define X86_MXCSR_UM          RT_BIT_32(11)
+#define X86_MXCSR_UM_BIT      11
 /** Exception Mask: Precision.  */
 #define X86_MXCSR_PM          RT_BIT_32(12)
+#define X86_MXCSR_PM_BIT      12
 /** Exception Mask: mask.  */
 #define X86_MXCSR_XCPT_MASK   UINT32_C(0x1f80)
@@ -3891 +3904 @@
 /** Flush-to-zero for masked underflow.  */
 #define X86_MXCSR_FZ          RT_BIT_32(15)
+#define X86_MXCSR_FZ_BIT      15
 
 /** Misaligned Exception Mask (AMD MISALIGNSSE).  */
 #define X86_MXCSR_MM          RT_BIT_32(17)
+#define X86_MXCSR_MM_BIT      17
 /** Bits which should be zero, apparently. */
 #define X86_MXCSR_ZERO_MASK   UINT32_C(0xfffd0000)