Changeset 105450 in vbox

Timestamp:

Jul 23, 2024 2:52:34 PM (7 months ago)

Author:

vboxsync

Message:

VMM/IEM: Exception flags generation fixes for the SIMD floating point C helpers, bugref:10652

File:

• trunk/src/VBox/VMM/VMMAll/IEMAllAImplC.cpp (modified) (5 diffs)

trunk/src/VBox/VMM/VMMAll/IEMAllAImplC.cpp

@@ -15587 +15587 @@
 {
     iemFpSoftF32ToIprt(pr32Result, r32Result);
-
     uint8_t fXcpt = pSoftState->exceptionFlags;
-    if (   (fMxcsr & X86_MXCSR_FZ)
-        && RTFLOAT32U_IS_SUBNORMAL(pr32Result))
-    {
-        /* Underflow masked and flush to zero is set. */
-        pr32Result->s.uFraction = 0;
-        pr32Result->s.uExponent = 0;
-        fXcpt |= X86_MXCSR_UE | X86_MXCSR_PE;
-    }
-
     /* If DAZ is set \#DE is never set. */
     if (   fMxcsr & X86_MXCSR_DAZ
@@ -15603 +15593 @@
             && (RTFLOAT32U_IS_SUBNORMAL(pr32Result))))
         fXcpt &= ~X86_MXCSR_DE;
+
+    /*
+     * Skip computing the post-computational exception flags if any of the pre-computational exception flags
+     * are set and are unmasked in MXCSR.
+     */
+    if (  ((fMxcsr | fXcpt) & (X86_MXCSR_IE | X86_MXCSR_DE | X86_MXCSR_ZE))
+        & ~((fMxcsr & X86_MXCSR_XCPT_MASK) >> X86_MXCSR_XCPT_MASK_SHIFT))
+        return fMxcsr | (fXcpt & (X86_MXCSR_IE | X86_MXCSR_DE | X86_MXCSR_ZE));
+
+    if (   (fMxcsr & X86_MXCSR_FZ)
+        && RTFLOAT32U_IS_SUBNORMAL(pr32Result))
+    {
+        /* Underflow masked and flush to zero is set. */
+        pr32Result->s.uFraction = 0;
+        pr32Result->s.uExponent = 0;
+        fXcpt |= X86_MXCSR_UE | X86_MXCSR_PE;
+    }
+
+    /* If OE/UE get raised PE won't be set because of the lower priority. */
+    if (   (   ((fXcpt & (X86_MXCSR_PE | X86_MXCSR_OE)) == (X86_MXCSR_PE | X86_MXCSR_OE))
+            && !(fMxcsr & X86_MXCSR_OM))
+        || (   ((fXcpt & (X86_MXCSR_PE | X86_MXCSR_UE)) == (X86_MXCSR_PE | X86_MXCSR_UE))
+            && !(fMxcsr & X86_MXCSR_UM)))
+        fXcpt &= ~X86_MXCSR_PE;
 
     return fMxcsr | (fXcpt & X86_MXCSR_XCPT_FLAGS);
@@ -15639 +15653 @@
  *
  * @returns Updated MXCSR.
- * @param   pSoftState      The SoftFloat state following the operation.
- * @param   r64Result       The result of the SoftFloat operation.
- * @param   pr64Result      Where to store the result for IEM.
- * @param   fMxcsr          The original MXCSR value.
+ * @param   pSoftState           The SoftFloat state following the operation.
+ * @param   r64Result            The result of the SoftFloat operation.
+ * @param   pr64Result           Where to store the result for IEM.
+ * @param   fMxcsr               The original MXCSR value.
  */
 DECLINLINE(uint32_t) iemSseSoftStateAndR64ToMxcsrAndIprtResult(softfloat_state_t const *pSoftState, float64_t r64Result,
@@ -15649 +15663 @@
     iemFpSoftF64ToIprt(pr64Result, r64Result);
     uint8_t fXcpt = pSoftState->exceptionFlags;
-    if (   (fMxcsr & X86_MXCSR_FZ)
-        && RTFLOAT64U_IS_SUBNORMAL(pr64Result))
-    {
-        /* Underflow masked and flush to zero is set. */
-        iemFpSoftF64ToIprt(pr64Result, r64Result);
-        pr64Result->s.uFractionHigh = 0;
-        pr64Result->s.uFractionLow  = 0;
-        pr64Result->s.uExponent     = 0;
-        fXcpt |= X86_MXCSR_UE | X86_MXCSR_PE;
-    }
-
     /* If DAZ is set \#DE is never set. */
     if (   fMxcsr & X86_MXCSR_DAZ
@@ -15665 +15668 @@
             && (RTFLOAT64U_IS_SUBNORMAL(pr64Result))))
         fXcpt &= ~X86_MXCSR_DE;
+
+    /*
+     * Skip computing the post-computational exception flags if any of the pre-computational exception flags
+     * are set and are unmasked in MXCSR.
+     */
+    if (  ((fMxcsr | fXcpt) & (X86_MXCSR_IE | X86_MXCSR_DE | X86_MXCSR_ZE))
+        & ~((fMxcsr & X86_MXCSR_XCPT_MASK) >> X86_MXCSR_XCPT_MASK_SHIFT))
+        return fMxcsr | (fXcpt & (X86_MXCSR_IE | X86_MXCSR_DE | X86_MXCSR_ZE));
+
+    if (   (fMxcsr & X86_MXCSR_FZ)
+        && RTFLOAT64U_IS_SUBNORMAL(pr64Result))
+    {
+        /* Underflow masked and flush to zero is set. */
+        pr64Result->s.uFractionHigh = 0;
+        pr64Result->s.uFractionLow  = 0;
+        pr64Result->s.uExponent     = 0;
+        fXcpt |= X86_MXCSR_UE | X86_MXCSR_PE;
+    }
+
+    /* If OE/UE get raised PE won't be set because of the lower priority. */
+    if (   (   ((fXcpt & (X86_MXCSR_PE | X86_MXCSR_OE)) == (X86_MXCSR_PE | X86_MXCSR_OE))
+            && !(fMxcsr & X86_MXCSR_OM))
+        || (   ((fXcpt & (X86_MXCSR_PE | X86_MXCSR_UE)) == (X86_MXCSR_PE | X86_MXCSR_UE))
+            && !(fMxcsr & X86_MXCSR_UM)))
+        fXcpt &= ~X86_MXCSR_PE;
 
     return fMxcsr | (fXcpt & X86_MXCSR_XCPT_FLAGS);