Index: trunk/src/VBox/VMM/VMMAll/IEMAllN8veHlpA-arm64.S
===================================================================
--- trunk/src/VBox/VMM/VMMAll/IEMAllN8veHlpA-arm64.S	(revision 105489)
+++ trunk/src/VBox/VMM/VMMAll/IEMAllN8veHlpA-arm64.S	(revision 105490)
@@ -257,2 +257,21 @@
         brk #1
 
+
+/**
+ * Restores the FPCR register from the given argument.
+ *
+ * @param    u64RegFpCtrl    (x0)      The value to restore FPCR with.
+ */
+ALIGNCODE(IEM_HLP_FUNCTION_ALIGNMENT)
+BEGINPROC_HIDDEN iemNativeFpCtrlRegRestore
+#ifdef RT_OS_DARWIN
+        pacibsp
+#endif
+
+        msr FPCR, x0
+
+#ifdef RT_OS_DARWIN
+        retab
+#else
+        ret
+#endif
Index: trunk/src/VBox/VMM/VMMAll/IEMAllN8veHlpA.asm
===================================================================
--- trunk/src/VBox/VMM/VMMAll/IEMAllN8veHlpA.asm	(revision 105489)
+++ trunk/src/VBox/VMM/VMMAll/IEMAllN8veHlpA.asm	(revision 105490)
@@ -281,2 +281,21 @@
 ENDPROC     iemNativeHlpAsmSafeWrapCheckTlbLookup
 
+
+;;
+; This is wrapper function that restores MXCSR when TB execution finished.
+;
+; @param    uRegFpCtrl  (gcc:rdi, msc:rcx)  The MXCSR value to restore.
+;
+ALIGNCODE(16)
+BEGINPROC   iemNativeFpCtrlRegRestore
+        sub     xSP, 4
+%ifdef RT_OS_WINDOWS
+        mov     [xSP], edx
+%else
+        mov     [xSP], edi
+%endif
+
+        ldmxcsr [xSP]
+        add     xSP, 4
+        ret
+ENDPROC     iemNativeFpCtrlRegRestore
Index: trunk/src/VBox/VMM/VMMAll/IEMAllN8veLiveness.cpp
===================================================================
--- trunk/src/VBox/VMM/VMMAll/IEMAllN8veLiveness.cpp	(revision 105489)
+++ trunk/src/VBox/VMM/VMMAll/IEMAllN8veLiveness.cpp	(revision 105490)
@@ -1063,4 +1063,5 @@
 #define IEM_MC_NATIVE_EMIT_1(a_fnEmitter, a0)                                                   NOP()
 #define IEM_MC_NATIVE_EMIT_2(a_fnEmitter, a0, a1)                                               NOP()
+#define IEM_MC_NATIVE_EMIT_2_EX(a_fnEmitter, a0, a1)                                            NOP()
 #define IEM_MC_NATIVE_EMIT_3(a_fnEmitter, a0, a1, a2)                                           NOP()
 #define IEM_MC_NATIVE_EMIT_4(a_fnEmitter, a0, a1, a2, a3)                                       NOP()
@@ -1118,15 +1119,15 @@
 #define IEM_MC_FPU_STACK_PUSH_OVERFLOW_MEM_OP(a_iEffSeg, a_GCPtrEff, a_uFpuOpcode)              NOP()
 
-#define IEM_MC_PREPARE_FPU_USAGE()                                                              NOP()
-#define IEM_MC_ACTUALIZE_FPU_STATE_FOR_READ()                                                   NOP()
-#define IEM_MC_ACTUALIZE_FPU_STATE_FOR_CHANGE()                                                 NOP()
-
-#define IEM_MC_PREPARE_SSE_USAGE()                                                              NOP()
-#define IEM_MC_ACTUALIZE_SSE_STATE_FOR_READ()                                                   NOP()
-#define IEM_MC_ACTUALIZE_SSE_STATE_FOR_CHANGE()                                                 NOP()
-
-#define IEM_MC_PREPARE_AVX_USAGE()                                                              NOP()
-#define IEM_MC_ACTUALIZE_AVX_STATE_FOR_READ()                                                   NOP()
-#define IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE()                                                 NOP()
+#define IEM_MC_PREPARE_FPU_USAGE()                                                              IEM_LIVENESS_MXCSR_INPUT() /* fxrstor */
+#define IEM_MC_ACTUALIZE_FPU_STATE_FOR_READ()                                                   IEM_LIVENESS_MXCSR_INPUT()
+#define IEM_MC_ACTUALIZE_FPU_STATE_FOR_CHANGE()                                                 IEM_LIVENESS_MXCSR_INPUT()
+
+#define IEM_MC_PREPARE_SSE_USAGE()                                                              IEM_LIVENESS_MXCSR_INPUT()
+#define IEM_MC_ACTUALIZE_SSE_STATE_FOR_READ()                                                   IEM_LIVENESS_MXCSR_INPUT()
+#define IEM_MC_ACTUALIZE_SSE_STATE_FOR_CHANGE()                                                 IEM_LIVENESS_MXCSR_INPUT()
+
+#define IEM_MC_PREPARE_AVX_USAGE()                                                              IEM_LIVENESS_MXCSR_INPUT()
+#define IEM_MC_ACTUALIZE_AVX_STATE_FOR_READ()                                                   IEM_LIVENESS_MXCSR_INPUT()
+#define IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE()                                                 IEM_LIVENESS_MXCSR_INPUT()
 
 #define IEM_MC_CALL_MMX_AIMPL_2(a_pfnAImpl, a0, a1)                                             NOP()
Index: trunk/src/VBox/VMM/VMMAll/IEMAllN8veRecompFuncs.h
===================================================================
--- trunk/src/VBox/VMM/VMMAll/IEMAllN8veRecompFuncs.h	(revision 105489)
+++ trunk/src/VBox/VMM/VMMAll/IEMAllN8veRecompFuncs.h	(revision 105490)
@@ -79,4 +79,7 @@
 #endif
 
+#if defined(IEMNATIVE_WITH_SIMD_FP_NATIVE_EMITTERS) && !defined(IEMNATIVE_WITH_SIMD_REG_ALLOCATOR)
+# error "IEMNATIVE_WITH_SIMD_FP_NATIVE_EMITTERS requires IEMNATIVE_WITH_SIMD_REG_ALLOCATOR"
+#endif
 
 
@@ -3365,4 +3368,10 @@
                                                     | IEMNATIVE_SIMD_RAISE_XCPT_CHECKS_EMITTED_MAYBE_SSE
                                                     | IEMNATIVE_SIMD_RAISE_XCPT_CHECKS_EMITTED_MAYBE_DEVICE_NOT_AVAILABLE);
+# endif
+
+# ifdef IEMNATIVE_WITH_SIMD_FP_NATIVE_EMITTERS
+    /* Mark the host floating point control register as not synced if MXCSR is modified. */
+    if (fGstShwFlush & RT_BIT_64(kIemNativeGstReg_MxCsr))
+        pReNative->fSimdRaiseXcptChecksEmitted &= ~IEMNATIVE_SIMD_HOST_FP_CTRL_REG_SYNCED;
 # endif
 #endif
@@ -8756,6 +8765,126 @@
 DECL_INLINE_THROW(uint32_t) iemNativeEmitPrepareFpuForUse(PIEMRECOMPILERSTATE pReNative, uint32_t off, bool fForChange)
 {
-    /** @todo this needs a lot more work later. */
+#ifndef IEMNATIVE_WITH_SIMD_FP_NATIVE_EMITTERS
     RT_NOREF(pReNative, fForChange);
+#else
+    if (   !(pReNative->fSimdRaiseXcptChecksEmitted & IEMNATIVE_SIMD_HOST_FP_CTRL_REG_SYNCED)
+        && fForChange)
+    {
+# ifdef RT_ARCH_AMD64
+
+        /* Need to save the host MXCSR the first time, and clear the exception flags. */
+        if (!(pReNative->fSimdRaiseXcptChecksEmitted & IEMNATIVE_SIMD_HOST_FP_CTRL_REG_SAVED))
+        {
+            PIEMNATIVEINSTR pbCodeBuf = iemNativeInstrBufEnsure(pReNative, off, 8);
+
+            /* stmxcsr */
+            if (IEMNATIVE_REG_FIXED_PVMCPU >= 8)
+                pbCodeBuf[off++] = X86_OP_REX_B;
+            pbCodeBuf[off++] = 0x0f;
+            pbCodeBuf[off++] = 0xae;
+            pbCodeBuf[off++] = X86_MODRM_MAKE(X86_MOD_MEM4, 3, IEMNATIVE_REG_FIXED_PVMCPU & 7);
+            pbCodeBuf[off++] = RT_BYTE1(RT_UOFFSETOF(VMCPU, iem.s.uRegFpCtrl));
+            pbCodeBuf[off++] = RT_BYTE2(RT_UOFFSETOF(VMCPU, iem.s.uRegFpCtrl));
+            pbCodeBuf[off++] = RT_BYTE3(RT_UOFFSETOF(VMCPU, iem.s.uRegFpCtrl));
+            pbCodeBuf[off++] = RT_BYTE4(RT_UOFFSETOF(VMCPU, iem.s.uRegFpCtrl));
+            IEMNATIVE_ASSERT_INSTR_BUF_ENSURE(pReNative, off);
+
+            pReNative->fSimdRaiseXcptChecksEmitted |= IEMNATIVE_SIMD_HOST_FP_CTRL_REG_SAVED;
+        }
+
+        uint8_t const idxRegTmp = iemNativeRegAllocTmp(pReNative, &off, false /*fPreferVolatile*/);
+        uint8_t const idxRegMxCsr = iemNativeRegAllocTmpForGuestReg(pReNative, &off, kIemNativeGstReg_MxCsr, kIemNativeGstRegUse_ReadOnly);
+
+        /*
+         * Mask any exceptions and clear the exception status and save into MXCSR,
+         * taking a detour through memory here because ldmxcsr/stmxcsr don't support
+         * a register source/target (sigh).
+         */
+        off = iemNativeEmitLoadGprFromGpr32(pReNative, off, IEMNATIVE_REG_FIXED_TMP0, idxRegMxCsr);
+        off = iemNativeEmitOrGpr32ByImm(pReNative, off, IEMNATIVE_REG_FIXED_TMP0, X86_MXCSR_XCPT_MASK);
+        off = iemNativeEmitAndGpr32ByImm(pReNative, off, IEMNATIVE_REG_FIXED_TMP0, ~X86_MXCSR_XCPT_FLAGS);
+        off = iemNativeEmitStoreGprToVCpuU32(pReNative, off, IEMNATIVE_REG_FIXED_TMP0, RT_UOFFSETOF(VMCPU, iem.s.uRegMxcsrTmp));
+
+        PIEMNATIVEINSTR pbCodeBuf = iemNativeInstrBufEnsure(pReNative, off, 8);
+
+        /* ldmxcsr */
+        if (IEMNATIVE_REG_FIXED_PVMCPU >= 8)
+            pbCodeBuf[off++] = X86_OP_REX_B;
+        pbCodeBuf[off++] = 0x0f;
+        pbCodeBuf[off++] = 0xae;
+        pbCodeBuf[off++] = X86_MODRM_MAKE(X86_MOD_MEM4, 2, IEMNATIVE_REG_FIXED_PVMCPU & 7);
+        pbCodeBuf[off++] = RT_BYTE1(RT_UOFFSETOF(VMCPU, iem.s.uRegMxcsrTmp));
+        pbCodeBuf[off++] = RT_BYTE2(RT_UOFFSETOF(VMCPU, iem.s.uRegMxcsrTmp));
+        pbCodeBuf[off++] = RT_BYTE3(RT_UOFFSETOF(VMCPU, iem.s.uRegMxcsrTmp));
+        pbCodeBuf[off++] = RT_BYTE4(RT_UOFFSETOF(VMCPU, iem.s.uRegMxcsrTmp));
+        IEMNATIVE_ASSERT_INSTR_BUF_ENSURE(pReNative, off);
+
+        iemNativeRegFreeTmp(pReNative, idxRegMxCsr);
+        iemNativeRegFreeTmp(pReNative, idxRegTmp);
+
+# elif defined(RT_ARCH_ARM64)
+        uint8_t const idxRegTmp = iemNativeRegAllocTmp(pReNative, &off, false /*fPreferVolatile*/);
+
+        /* Need to save the host floating point control register the first time, clear FPSR. */
+        if (!(pReNative->fSimdRaiseXcptChecksEmitted & IEMNATIVE_SIMD_HOST_FP_CTRL_REG_SAVED))
+        {
+            PIEMNATIVEINSTR pu32CodeBuf = iemNativeInstrBufEnsure(pReNative, off, 2);
+            pu32CodeBuf[off++] = Armv8A64MkInstrMsr(ARMV8_A64_REG_XZR, ARMV8_AARCH64_SYSREG_FPSR);
+            pu32CodeBuf[off++] = Armv8A64MkInstrMrs(idxRegTmp, ARMV8_AARCH64_SYSREG_FPCR);
+            off = iemNativeEmitStoreGprToVCpuU64(pReNative, off, idxRegTmp, RT_UOFFSETOF(VMCPU, iem.s.uRegFpCtrl));
+            pReNative->fSimdRaiseXcptChecksEmitted |= IEMNATIVE_SIMD_HOST_FP_CTRL_REG_SAVED;
+        }
+
+        /*
+         * Translate MXCSR to FPCR.
+         *
+         * Unfortunately we can't emulate the exact behavior of MXCSR as we can't take
+         * FEAT_AFP on arm64 for granted (My M2 Macbook doesn't has it). So we can't map
+         * MXCSR.DAZ to FPCR.FIZ and MXCSR.FZ to FPCR.FZ with FPCR.AH being set.
+         * We can only use FPCR.FZ which will flush inputs _and_ output de-normals to zero.
+         */
+        /** @todo Check the host supported flags (needs additional work to get the host features from CPUM)
+         *        and implement alternate handling if FEAT_AFP is present. */
+        uint8_t const idxRegMxCsr = iemNativeRegAllocTmpForGuestReg(pReNative, &off, kIemNativeGstReg_MxCsr, kIemNativeGstRegUse_ReadOnly);
+
+        PIEMNATIVEINSTR pu32CodeBuf = iemNativeInstrBufEnsure(pReNative, off, 10);
+
+        /* First make sure that there is nothing set for the upper 16-bits (X86_MXCSR_MM, which we don't emulate right now). */
+        pu32CodeBuf[off++] = Armv8A64MkInstrUxth(idxRegTmp, idxRegMxCsr);
+
+        /* If either MXCSR.FZ or MXCSR.DAZ is set FPCR.FZ will be set. */
+        pu32CodeBuf[off++] = Armv8A64MkInstrUbfx(IEMNATIVE_REG_FIXED_TMP0, idxRegTmp, X86_MXCSR_DAZ_BIT, 1);
+        pu32CodeBuf[off++] = Armv8A64MkInstrLsrImm(idxRegTmp,              idxRegTmp, X86_MXCSR_FZ_BIT);
+        pu32CodeBuf[off++] = Armv8A64MkInstrOrr(idxRegTmp, idxRegTmp, IEMNATIVE_REG_FIXED_TMP0);
+        pu32CodeBuf[off++] = Armv8A64MkInstrLslImm(idxRegTmp, idxRegTmp, ARMV8_FPCR_FZ_BIT);
+
+        /*
+         * Init the rounding mode, the layout differs between MXCSR.RM[14:13] and FPCR.RMode[23:22]:
+         *
+         * Value    MXCSR   FPCR
+         *   0       RN      RN
+         *   1       R-      R+
+         *   2       R+      R-
+         *   3       RZ      RZ
+         *
+         * Conversion can be achieved by switching bit positions
+         */
+        pu32CodeBuf[off++] = Armv8A64MkInstrLsrImm(IEMNATIVE_REG_FIXED_TMP0, idxRegMxCsr, X86_MXCSR_RC_SHIFT);
+        pu32CodeBuf[off++] = Armv8A64MkInstrBfi(idxRegTmp, IEMNATIVE_REG_FIXED_TMP0, 14, 1);
+        pu32CodeBuf[off++] = Armv8A64MkInstrLsrImm(IEMNATIVE_REG_FIXED_TMP0, idxRegMxCsr, X86_MXCSR_RC_SHIFT + 1);
+        pu32CodeBuf[off++] = Armv8A64MkInstrBfi(idxRegTmp, IEMNATIVE_REG_FIXED_TMP0, 13, 1);
+
+        /* Write the value to FPCR. */
+        pu32CodeBuf[off++] = Armv8A64MkInstrMsr(idxRegTmp, ARMV8_AARCH64_SYSREG_FPCR);
+
+        IEMNATIVE_ASSERT_INSTR_BUF_ENSURE(pReNative, off);
+        iemNativeRegFreeTmp(pReNative, idxRegMxCsr);
+        iemNativeRegFreeTmp(pReNative, idxRegTmp);
+# else
+#  error "Port me"
+# endif
+        pReNative->fSimdRaiseXcptChecksEmitted |= IEMNATIVE_SIMD_HOST_FP_CTRL_REG_SYNCED;
+    }
+#endif
     return off;
 }
@@ -9980,8 +10109,10 @@
     AssertRelease(!(RT_BIT_32(idxRegMxCsr) & IEMNATIVE_CALL_VOLATILE_GREG_MASK));
 
+#if 0 /* This is not required right now as the called helper will set up the SSE/AVX state if it is an assembly one. */
     /*
      * Need to do the FPU preparation.
      */
     off = iemNativeEmitPrepareFpuForUse(pReNative, off, true /*fForChange*/);
+#endif
 
     /*
Index: trunk/src/VBox/VMM/VMMAll/IEMAllThrdRecompiler.cpp
===================================================================
--- trunk/src/VBox/VMM/VMMAll/IEMAllThrdRecompiler.cpp	(revision 105489)
+++ trunk/src/VBox/VMM/VMMAll/IEMAllThrdRecompiler.cpp	(revision 105490)
@@ -114,4 +114,7 @@
 #endif
 
+#if defined(IEMNATIVE_WITH_SIMD_FP_NATIVE_EMITTERS) && !defined(IEMNATIVE_WITH_SIMD_REG_ALLOCATOR)
+# error "IEMNATIVE_WITH_SIMD_FP_NATIVE_EMITTERS requires IEMNATIVE_WITH_SIMD_REG_ALLOCATOR"
+#endif
 
 
@@ -2844,4 +2847,13 @@
         pVCpu->iem.s.pvTbFramePointerR3 = NULL;
 # endif
+# ifdef IEMNATIVE_WITH_SIMD_FP_NATIVE_EMITTERS
+        /* Restore FPCR/MXCSR if the TB modified it. */
+        if (pVCpu->iem.s.uRegFpCtrl != IEMNATIVE_SIMD_FP_CTRL_REG_NOT_MODIFIED)
+        {
+            iemNativeFpCtrlRegRestore(pVCpu->iem.s.uRegFpCtrl);
+            /* Reset for the next round saving us an unconditional instruction on next TB entry. */
+            pVCpu->iem.s.uRegFpCtrl = IEMNATIVE_SIMD_FP_CTRL_REG_NOT_MODIFIED;
+        }
+# endif
 # ifdef IEMNATIVE_STRICT_EFLAGS_SKIPPING
         Assert(pVCpu->iem.s.fSkippingEFlags == 0);
@@ -3157,4 +3169,14 @@
                 pVCpu->iem.s.cInstructions += pVCpu->iem.s.idxTbCurInstr;
 # endif
+
+#ifdef IEMNATIVE_WITH_SIMD_FP_NATIVE_EMITTERS
+                /* Restore FPCR/MXCSR if the TB modified it. */
+                if (pVCpu->iem.s.uRegFpCtrl != IEMNATIVE_SIMD_FP_CTRL_REG_NOT_MODIFIED)
+                {
+                    iemNativeFpCtrlRegRestore(pVCpu->iem.s.uRegFpCtrl);
+                    /* Reset for the next round saving us an unconditional instruction on next TB entry. */
+                    pVCpu->iem.s.uRegFpCtrl = IEMNATIVE_SIMD_FP_CTRL_REG_NOT_MODIFIED;
+                }
+#endif
             }
 #endif
Index: trunk/src/VBox/VMM/include/IEMInternal.h
===================================================================
--- trunk/src/VBox/VMM/include/IEMInternal.h	(revision 105489)
+++ trunk/src/VBox/VMM/include/IEMInternal.h	(revision 105490)
@@ -117,4 +117,10 @@
 #if defined(VBOX_WITH_STATISTICS) || defined(DOXYGEN_RUNNING)
 # define IEM_WITH_TLB_STATISTICS
+#endif
+
+/** @def IEMNATIVE_WITH_SIMD_FP_NATIVE_EMITTERS
+ * Enable this to use native emitters for certain SIMD FP operations. */
+#if 1 || defined(DOXYGEN_RUNNING)
+# define IEMNATIVE_WITH_SIMD_FP_NATIVE_EMITTERS
 #endif
 
@@ -2046,4 +2052,20 @@
 #else
     R3PTRTYPE(void *)       pvUnusedR3;
+#endif
+#ifdef IEMNATIVE_WITH_SIMD_FP_NATIVE_EMITTERS
+    /** The saved host floating point control register (MXCSR on x86, FPCR on arm64)
+     * needing restore when the TB finished, IEMNATIVE_SIMD_FP_CTRL_REG_NOT_MODIFIED indicates the TB
+     * didn't modify it so we don't need to restore it. */
+# ifdef RT_ARCH_AMD64
+    uint32_t                uRegFpCtrl;
+    /** Temporary copy of MXCSR for stmxcsr/ldmxcsr (so we don't have to fiddle with stack pointers). */
+    uint32_t                uRegMxcsrTmp;
+# elif defined(RT_ARCH_ARM64)
+    uint64_t                uRegFpCtrl;
+# else
+#  error "Port me"
+# endif
+#else
+    uint64_t                u64Unused;
 #endif
     /** Fixed TB used for threaded recompilation.
@@ -2339,7 +2361,7 @@
 
 #ifdef IEM_WITH_TLB_TRACE
-    uint64_t                au64Padding[3];
+    uint64_t                au64Padding[2];
 #else
-    uint64_t                au64Padding[5];
+    uint64_t                au64Padding[4];
 #endif
     /** @} */
@@ -2390,4 +2412,17 @@
 typedef IEMCPU const *PCIEMCPU;
 
+/** @def IEMNATIVE_SIMD_FP_CTRL_REG_NOT_MODIFIED
+ * Value indicating the TB didn't modified the floating point control register.
+ * @note Neither FPCR nor MXCSR accept this as a valid value (MXCSR is not fully populated,
+ *       FPCR has the upper 32-bit reserved), so this is safe. */
+#if defined(IEMNATIVE_WITH_SIMD_FP_NATIVE_EMITTERS) || defined(DOXYGEN_RUNNING)
+# ifdef RT_ARCH_AMD64
+#  define IEMNATIVE_SIMD_FP_CTRL_REG_NOT_MODIFIED UINT32_MAX
+# elif defined(RT_ARCH_ARM64)
+#  define IEMNATIVE_SIMD_FP_CTRL_REG_NOT_MODIFIED UINT64_MAX
+# else
+#  error "Port me"
+# endif
+#endif
 
 /** @def IEM_GET_CTX
Index: trunk/src/VBox/VMM/include/IEMN8veRecompiler.h
===================================================================
--- trunk/src/VBox/VMM/include/IEMN8veRecompiler.h	(revision 105489)
+++ trunk/src/VBox/VMM/include/IEMN8veRecompiler.h	(revision 105490)
@@ -1349,4 +1349,10 @@
 /** Flag for indicating that IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT() has emitted code in the current TB. */
 # define IEMNATIVE_SIMD_RAISE_XCPT_CHECKS_EMITTED_MAYBE_AVX                         RT_BIT_32(3)
+# ifdef IEMNATIVE_WITH_SIMD_FP_NATIVE_EMITTERS
+/** Flag indicating that the guest MXCSR was synced to the host floating point control register. */
+#  define IEMNATIVE_SIMD_HOST_FP_CTRL_REG_SYNCED                                    RT_BIT_32(4)
+/** Flag indicating whether the host floating point control register was saved before overwriting it. */
+#  define IEMNATIVE_SIMD_HOST_FP_CTRL_REG_SAVED                                     RT_BIT_32(5)
+# endif
 #endif
 
@@ -2581,4 +2587,8 @@
 #endif
 
+#ifdef IEMNATIVE_WITH_SIMD_FP_NATIVE_EMITTERS
+extern "C" IEM_DECL_NATIVE_HLP_DEF(int, iemNativeFpCtrlRegRestore, (uint64_t u64RegFpCtrl));
+#endif
+
 #endif /* !RT_IN_ASSEMBLER - ASM-NOINC-END */
 
