Index: trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-4.c32
===================================================================
--- trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-4.c32	(revision 105590)
+++ trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-4.c32	(revision 105594)
@@ -4514,5 +4514,4 @@
 
 
-#if 0
 /*
  * [V]MULPD.
@@ -4528,43 +4527,50 @@
             { /*src1     */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } },
             { /* =>      */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } },
-              /*mask     */ X86_MXCSR_XCPT_MASK,
-              /*daz,fz,rc*/ 0, 0, X86_MXCSR_RC_NEAREST,
-              /*flags    */ 0, 0 },
+             /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
+             /*128:out  */ X86_MXCSR_XCPT_MASK,
+             /*256:out  */ X86_MXCSR_XCPT_MASK,
+             /*xcpt?    */ false, false },
          { { /*src2     */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } },
            { /*src1     */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } },
            { /* =>      */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } },
-             /*mask     */ ~X86_MXCSR_XCPT_MASK,
-             /*daz,fz,rc*/ 0, 0, X86_MXCSR_RC_NEAREST,
-             /*flags    */ 0, 0 },
+             /*mxcsr:in */ 0,
+             /*128:out  */ 0,
+             /*256:out  */ 0,
+             /*xcpt?    */ false, false },
          { { /*src2     */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } },
            { /*src1     */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } },
            { /* =>      */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } },
-             /*mask     */ ~X86_MXCSR_XCPT_MASK,
-             /*daz,fz,rc*/ X86_MXCSR_DAZ, X86_MXCSR_FZ, X86_MXCSR_RC_UP,
-             /*flags    */ 0, 0 },
+             /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
+             /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
+             /*256:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
+             /*xcpt?    */ false, false },
          { { /*src2     */ { FP64_0(1), FP64_0(0), FP64_0(0), FP64_0(0) } },
            { /*src1     */ { FP64_0(1), FP64_0(0), FP64_0(0), FP64_0(0) } },
            { /* =>      */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } },
-             /*mask     */ ~X86_MXCSR_XCPT_MASK,
-             /*daz,fz,rc*/ X86_MXCSR_DAZ, 0, X86_MXCSR_RC_ZERO,
-             /*flags    */ 0, 0 },
+             /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO,
+             /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO,
+             /*256:out  */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO,
+             /*xcpt?    */ false, false },
          { { /*src2     */ { FP64_0(0), FP64_0(0), FP64_0(1), FP64_0(0) } },
            { /*src1     */ { FP64_0(0), FP64_0(0), FP64_0(1), FP64_0(0) } },
            { /* =>      */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } },
-             /*mask     */ ~X86_MXCSR_XCPT_MASK,
-             /*daz,fz,rc*/ 0, X86_MXCSR_FZ, X86_MXCSR_RC_ZERO,
-             /*flags    */ 0, 0 },
+             /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
+             /*128:out  */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
+             /*256:out  */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
+             /*xcpt?    */ false, false },
          { { /*src2     */ { FP64_0(0), FP64_0(1), FP64_0(0), FP64_0(1) } },
            { /*src1     */ { FP64_0(0), FP64_0(0), FP64_0(1), FP64_0(1) } },
            { /* =>      */ { FP64_0(0), FP64_0(1), FP64_0(1), FP64_0(0) } },
-             /*mask     */ X86_MXCSR_XCPT_MASK,
-             /*daz,fz,rc*/ X86_MXCSR_DAZ, X86_MXCSR_FZ, X86_MXCSR_RC_DOWN,
-             /*flags    */ 0, 0 },
+             /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
+             /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
+             /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
+             /*xcpt?    */ false, false },
          { { /*src2     */ { FP64_NORM_V0(0), FP64_NORM_V1(1), FP64_0(0),       FP64_NORM_V3(1) } },
            { /*src1     */ { FP64_0(0),       FP64_0(0),       FP64_NORM_V2(1), FP64_0(1)       } },
            { /* =>      */ { FP64_0(0),       FP64_0(1),       FP64_0(1),       FP64_0(0)       } },
-             /*mask     */ X86_MXCSR_XCPT_MASK,
-             /*daz,fz,rc*/ X86_MXCSR_DAZ, X86_MXCSR_FZ, X86_MXCSR_RC_DOWN,
-             /*flags    */ 0, 0 },
+             /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
+             /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
+             /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
+             /*xcpt?    */ false, false },
     /*
      * Infinity.
@@ -4573,37 +4579,44 @@
             { /*src1     */ { FP64_INF(1), FP64_0(0), FP64_INF(0), FP64_0(0) } },
             { /* =>      */ { FP64_INF(1), FP64_0(0), FP64_INF(1), FP64_0(0) } },
-              /*mask     */ ~X86_MXCSR_IM,
-              /*daz,fz,rc*/ 0, 0, X86_MXCSR_RC_NEAREST,
-              /*flags    */ 0, 0 },
+             /*mxcsr:in */ X86_MXCSR_XCPT_MASK & ~X86_MXCSR_IM,
+             /*128:out  */ X86_MXCSR_XCPT_MASK & ~X86_MXCSR_IM,
+             /*256:out  */ X86_MXCSR_XCPT_MASK & ~X86_MXCSR_IM,
+             /*xcpt?    */ false, false },
           { { /*src2     */ { FP64_INF(0), FP64_INF(0), FP64_INF(1), FP64_INF(1) } },
             { /*src1     */ { FP64_INF(1), FP64_INF(0), FP64_INF(1), FP64_INF(0) } },
             { /* =>      */ { FP64_INF(1), FP64_INF(0), FP64_INF(0), FP64_INF(1) } },
-              /*mask     */ X86_MXCSR_XCPT_MASK,
-              /*daz,fz,rc*/ 0, 0, X86_MXCSR_RC_NEAREST,
-              /*flags    */ 0, 0 },
+             /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
+             /*128:out  */ X86_MXCSR_XCPT_MASK,
+             /*256:out  */ X86_MXCSR_XCPT_MASK,
+             /*xcpt?    */ false, false },
           { { /*src2     */ { FP64_INF(0), FP64_INF(1), FP64_0(1), FP64_INF(0) } },
             { /*src1     */ { FP64_INF(1), FP64_INF(0), FP64_0(1), FP64_INF(0) } },
             { /* =>      */ { FP64_INF(1), FP64_INF(1), FP64_0(0), FP64_INF(0) } },
-              /*mask     */ ~X86_MXCSR_XCPT_MASK,
-              /*daz,fz,rc*/ 0, X86_MXCSR_FZ, X86_MXCSR_RC_ZERO,
-              /*flags    */ 0, 0 },
+             /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
+             /*128:out  */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
+             /*256:out  */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
+             /*xcpt?    */ false, false },
           { { /*src2     */ { FP64_INF(0), FP64_INF(1), FP64_0(1), FP64_INF(0) } },
             { /*src1     */ { FP64_INF(1), FP64_INF(0), FP64_0(1), FP64_INF(0) } },
             { /* =>      */ { FP64_INF(1), FP64_INF(1), FP64_0(0), FP64_INF(0) } },
-              /*mask     */ X86_MXCSR_XCPT_MASK,
-              /*daz,fz,rc*/ X86_MXCSR_DAZ, X86_MXCSR_FZ, X86_MXCSR_RC_ZERO,
-              /*flags    */ 0, 0 },
+             /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
+             /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
+             /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
+             /*xcpt?    */ false, false },
           { { /*src2     */ { FP64_INF(0), FP64_INF(0),     FP64_1(0),   FP64_INF(0)     } },
             { /*src1     */ { FP64_1(0),   FP64_NORM_V0(0), FP64_INF(0), FP64_NORM_V1(0) } },
             { /* =>      */ { FP64_INF(0), FP64_INF(0),     FP64_INF(0), FP64_INF(0)     } },
-              /*mask     */ X86_MXCSR_XCPT_MASK,
-              /*daz,fz,rc*/ 0, 0, X86_MXCSR_RC_DOWN,
-              /*flags    */ 0, 0 },
+             /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN,
+             /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN,
+             /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN,
+             /*xcpt?    */ false, false },
           { { /*src2     */ { FP64_INF(1), FP64_INF(0),     FP64_NORM_V3(0), FP64_INF(1)     } },
             { /*src1     */ { FP64_1(1),   FP64_NORM_V3(1), FP64_INF(1),     FP64_NORM_V1(1) } },
             { /* =>      */ { FP64_INF(0), FP64_INF(1),     FP64_INF(1),     FP64_INF(0)     } },
-              /*mask     */ X86_MXCSR_XCPT_MASK,
-              /*daz,fz,rc*/ X86_MXCSR_DAZ, X86_MXCSR_FZ, X86_MXCSR_RC_UP,
-              /*flags    */ 0, 0 },
+             /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
+             /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
+             /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
+             /*xcpt?    */ false, false },
+#if 0
     /*
      * Normals.
@@ -4812,4 +4825,5 @@
               /*flags    */ X86_MXCSR_IE, X86_MXCSR_IE },
     /** @todo Underflow, Precision; Rounding, FZ etc. */
+#endif
     };
 
@@ -4861,4 +4875,5 @@
 
 
+#if 0
 /*
  * [V]MULSS.
@@ -5300,6 +5315,6 @@
         { "[v]subss",       bs3CpuInstr4_v_subss,  0 },
         { "[v]mulps",       bs3CpuInstr4_v_mulps,  0 },
+        { "[v]mulpd",       bs3CpuInstr4_v_mulpd,  0 },
 # if 0
-        { "[v]mulpd",       bs3CpuInstr4_v_mulpd,  0 },
         { "[v]mulss",       bs3CpuInstr4_v_mulss,  0 },
 # endif
