Index: trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-4.c32
===================================================================
--- trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-4.c32	(revision 105595)
+++ trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-4.c32	(revision 105596)
@@ -4716,5 +4716,4 @@
               /*256:out  */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_DE,
               /*xcpt?    */ true, true },
-#if 0
     /*
      * Overflow, Precision.
@@ -4723,43 +4722,51 @@
             { /*src1     */ { FP64_1(0),       FP64_1(0), FP64_1(0),        FP64_NORM_MAX(0) } },
             { /* =>      */ { FP64_NORM_V3(1), FP64_1(0), FP64_NORM_MAX(0), FP64_INF(0)      } },
-              /*mask     */ X86_MXCSR_XCPT_MASK,
-              /*daz,fz,rc*/ 0, 0, X86_MXCSR_RC_NEAREST,
-              /*flags    */ 0, X86_MXCSR_OE | X86_MXCSR_PE },
+              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
+              /*128:out  */ X86_MXCSR_XCPT_MASK,
+              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_OE | X86_MXCSR_PE,
+              /*xcpt?    */ false, false },
           { { /*src2     */ { FP64_NORM_MAX(0), FP64_NORM_MAX(0), FP64_NORM_V3(1), FP64_1(0) } },
             { /*src1     */ { FP64_1(0),        FP64_NORM_MAX(0), FP64_1(0),       FP64_1(0) } },
             { /* =>      */ { FP64_NORM_MAX(0), FP64_INF(0),      FP64_NORM_V3(1), FP64_1(0) } },
-              /*mask     */ ~X86_MXCSR_XCPT_MASK,
-              /*daz,fz,rc*/ 0, 0, X86_MXCSR_RC_NEAREST,
-              /*flags    */ X86_MXCSR_OE | X86_MXCSR_PE, X86_MXCSR_OE | X86_MXCSR_PE },
+              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
+              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_OE | X86_MXCSR_PE,
+              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_OE | X86_MXCSR_PE,
+              /*xcpt?    */ false, false },
           { { /*src2     */ { FP64_NORM_V3(0), FP64_NORM_MAX(0), FP64_NORM_MAX(1), FP64_1(0)       } },
             { /*src1     */ { FP64_1(0),       FP64_NORM_MAX(0), FP64_NORM_MAX(1), FP64_NORM_V1(0) } },
             { /* =>      */ { FP64_NORM_V3(0), FP64_NORM_MAX(0), FP64_NORM_MAX(0), FP64_NORM_V1(0) } },
-              /*mask     */ ~(X86_MXCSR_OE | X86_MXCSR_PE),
-              /*daz,fz,rc*/ X86_MXCSR_DAZ, X86_MXCSR_FZ, X86_MXCSR_RC_ZERO,
-              /*flags    */ X86_MXCSR_OE | X86_MXCSR_PE, X86_MXCSR_OE | X86_MXCSR_PE },
+              /*mxcsr:in */ (X86_MXCSR_XCPT_MASK & ~(X86_MXCSR_OE | X86_MXCSR_PE)) | X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO,
+              /*128:out  */ (X86_MXCSR_XCPT_MASK & ~(X86_MXCSR_OE | X86_MXCSR_PE)) | X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO | X86_MXCSR_OE | X86_MXCSR_PE,
+              /*256:out  */ (X86_MXCSR_XCPT_MASK & ~(X86_MXCSR_OE | X86_MXCSR_PE)) | X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO | X86_MXCSR_OE | X86_MXCSR_PE,
+              /*xcpt?    */ false, false },
           { { /*src2     */ { FP64_NORM_MAX(0), FP64_NORM_MIN(1), FP64_NORM_MIN(1),                                       FP64_NORM_MAX(0) } },
             { /*src1     */ { FP64_NORM_MAX(0), FP64_NORM_MIN(1), FP64_NORM_MAX(1),                                       FP64_NORM_MAX(0) } },
             { /* =>      */ { FP64_INF(0),      FP64_0(0),        FP64_V(0, FP64_FRAC_NORM_MAX, RTFLOAT64U_EXP_BIAS + 1), FP64_INF(0)      } },
-              /*mask     */ X86_MXCSR_OM | X86_MXCSR_UM | X86_MXCSR_PM,
-              /*daz,fz,rc*/ X86_MXCSR_DAZ, X86_MXCSR_FZ, X86_MXCSR_RC_NEAREST,
-              /*flags    */ X86_MXCSR_OE | X86_MXCSR_UE | X86_MXCSR_PE, X86_MXCSR_OE | X86_MXCSR_UE | X86_MXCSR_PE },
+              /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_OM | X86_MXCSR_UM | X86_MXCSR_PM,
+              /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_OM | X86_MXCSR_UM | X86_MXCSR_PM | X86_MXCSR_OE | X86_MXCSR_UE | X86_MXCSR_PE,
+              /*256:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_OM | X86_MXCSR_UM | X86_MXCSR_PM | X86_MXCSR_OE | X86_MXCSR_UE | X86_MXCSR_PE,
+              /*xcpt?    */ false, false },
           { { /*src2     */ { FP64_NORM_V3(0), FP64_1(1),       FP64_NORM_MAX(1), FP64_NORM_MIN(0)                                       } },
             { /*src1     */ { FP64_1(0),       FP64_NORM_V2(1), FP64_NORM_MAX(1), FP64_NORM_MAX(1)                                       } },
             { /* =>      */ { FP64_NORM_V3(0), FP64_NORM_V2(0), FP64_NORM_MAX(0), FP64_V(1, FP64_FRAC_NORM_MAX, RTFLOAT64U_EXP_BIAS + 1) } },
-              /*mask     */ ~(X86_MXCSR_OE | X86_MXCSR_PE),
-              /*daz,fz,rc*/ 0, 0, X86_MXCSR_RC_ZERO,
-              /*flags    */ 0, X86_MXCSR_OE | X86_MXCSR_PE },
+              /*mxcsr:in */ X86_MXCSR_XCPT_MASK & ~(X86_MXCSR_OE | X86_MXCSR_PE) | X86_MXCSR_RC_ZERO,
+              /*128:out  */ X86_MXCSR_XCPT_MASK & ~(X86_MXCSR_OE | X86_MXCSR_PE) | X86_MXCSR_RC_ZERO,
+              /*256:out  */ X86_MXCSR_XCPT_MASK & ~(X86_MXCSR_OE | X86_MXCSR_PE) | X86_MXCSR_RC_ZERO | X86_MXCSR_OE | X86_MXCSR_PE,
+              /*xcpt?    */ false, false },
           { { /*src2     */ { FP64_NORM_SAFE_INT_MIN(0),                         FP64_NORM_MAX(0), FP64_NORM_SAFE_INT_MAX(1),                FP64_NORM_SAFE_INT_MIN(0)            } },
             { /*src1     */ { FP64_NORM_SAFE_INT_MAX(0),                         FP64_NORM_MAX(1), FP64_NORM_SAFE_INT_MAX(1),                FP64_NORM_SAFE_INT_MAX(0)            } },
             { /* =>      */ { FP64_V(0, FP64_FRAC_NORM_MAX, FP64_FRAC_BITS + 1), FP64_NORM_MAX(1), FP64_V(0, FP64_FRAC_NORM_MAX - 1, 0x468), FP64_V(0, FP64_FRAC_NORM_MAX, 0x035) } },
-              /*mask     */ X86_MXCSR_XCPT_MASK,
-              /*daz,fz,rc*/ 0, 0, X86_MXCSR_RC_ZERO,
-              /*flags    */ X86_MXCSR_OE | X86_MXCSR_PE, X86_MXCSR_OE | X86_MXCSR_PE },
+              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
+              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO | X86_MXCSR_OE | X86_MXCSR_PE,
+              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO | X86_MXCSR_OE | X86_MXCSR_PE,
+              /*xcpt?    */ false, false },
           { { /*src2     */ { FP64_NORM_SAFE_INT_MIN(0),                         FP64_NORM_MAX(0), FP64_NORM_SAFE_INT_MAX(1),                FP64_NORM_SAFE_INT_MIN(0)            } },
             { /*src1     */ { FP64_NORM_SAFE_INT_MAX(0),                         FP64_NORM_MAX(1), FP64_NORM_SAFE_INT_MAX(1),                FP64_NORM_SAFE_INT_MAX(0)            } },
             { /* =>      */ { FP64_V(0, FP64_FRAC_NORM_MAX, FP64_FRAC_BITS + 1), FP64_INF(1),      FP64_V(0, FP64_FRAC_NORM_MAX - 1, 0x468), FP64_V(0, FP64_FRAC_NORM_MAX, 0x035) } },
-              /*mask     */ X86_MXCSR_XCPT_MASK,
-              /*daz,fz,rc*/ X86_MXCSR_DAZ, X86_MXCSR_FZ, X86_MXCSR_RC_DOWN,
-              /*flags    */ X86_MXCSR_OE | X86_MXCSR_PE, X86_MXCSR_OE | X86_MXCSR_PE },
+              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
+              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN | X86_MXCSR_OE | X86_MXCSR_PE,
+              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN | X86_MXCSR_OE | X86_MXCSR_PE,
+              /*xcpt?    */ false, false },
+#if 0
     /*
      * Invalids.
