Index: trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-4.c32
===================================================================
--- trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-4.c32	(revision 105597)
+++ trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-4.c32	(revision 105599)
@@ -4905,5 +4905,4 @@
 
 
-#if 0
 /*
  * [V]MULSS.
@@ -4919,49 +4918,57 @@
             { /*src1     */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
             { /* =>      */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
-              /*mask     */ X86_MXCSR_XCPT_MASK,
-              /*daz,fz,rc*/ 0, 0, X86_MXCSR_RC_NEAREST,
-              /*flags    */ 0, 0 },
+             /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
+             /*128:out  */ X86_MXCSR_XCPT_MASK,
+             /*256:out  */ X86_MXCSR_XCPT_MASK,
+             /*xcpt?    */ false, false },
           { { /*src2     */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
             { /*src1     */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
             { /* =>      */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
-              /*mask     */ ~X86_MXCSR_XCPT_MASK,
-              /*daz,fz,rc*/ 0, 0, X86_MXCSR_RC_NEAREST,
-              /*flags    */ 0, 0 },
+             /*mxcsr:in */ 0,
+             /*128:out  */ 0,
+             /*256:out  */ 0,
+             /*xcpt?    */ false, false },
           { { /*src2     */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
             { /*src1     */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
             { /* =>      */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
-              /*mask     */ X86_MXCSR_XCPT_MASK,
-              /*daz,fz,rc*/ X86_MXCSR_DAZ, X86_MXCSR_FZ, X86_MXCSR_RC_ZERO,
-              /*flags    */ 0, 0 },
+             /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
+             /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
+             /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
+             /*xcpt?    */ false, false },
           { { /*src2     */ { FP32_0(0), FP32_NORM_V7(0), FP32_NORM_V6(0), FP32_0(0),       FP32_0(1),       FP32_NORM_V3(0), FP32_0(0),       FP32_0(0)       } },
             { /*src1     */ { FP32_0(0), FP32_0(1),       FP32_0(1),       FP32_NORM_V2(0), FP32_NORM_V3(1), FP32_0(0),       FP32_NORM_V6(0), FP32_NORM_V2(0) } },
             { /* =>      */ { FP32_0(0), FP32_0(1),       FP32_0(1),       FP32_NORM_V2(0), FP32_NORM_V3(0), FP32_0(0),       FP32_NORM_V6(0), FP32_NORM_V2(0) } },
-              /*mask     */ X86_MXCSR_XCPT_MASK,
-              /*daz,fz,rc*/ X86_MXCSR_DAZ, X86_MXCSR_FZ, X86_MXCSR_RC_DOWN,
-              /*flags    */ 0, 0 },
+             /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
+             /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
+             /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
+             /*xcpt?    */ false, false },
           { { /*src2     */ { FP32_0(1), FP32_0(0), FP32_RAND_V6(0), FP32_RAND_V5(1), FP32_RAND_V4(1), FP32_RAND_V3(0), FP32_RAND_V2(1), FP32_RAND_V1(1) } },
             { /*src1     */ { FP32_0(1), FP32_0(0), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(1), FP32_RAND_V5(1), FP32_RAND_V6(0) } },
             { /* =>      */ { FP32_0(0), FP32_0(0), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(1), FP32_RAND_V5(1), FP32_RAND_V6(0) } },
-              /*mask     */ ~X86_MXCSR_XCPT_MASK,
-              /*daz,fz,rc*/ X86_MXCSR_DAZ, X86_MXCSR_FZ, X86_MXCSR_RC_UP,
-              /*flags    */ 0, 0 },
+             /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
+             /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
+             /*256:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
+             /*xcpt?    */ false, false },
           { { /*src2     */ { FP32_0(1), FP32_RAND_V0(0), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(1), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(1) } },
             { /*src1     */ { FP32_0(0), FP32_RAND_V7(1), FP32_RAND_V6(0), FP32_RAND_V5(0), FP32_RAND_V4(1), FP32_RAND_V3(0), FP32_RAND_V2(0), FP32_RAND_V1(1) } },
             { /* =>      */ { FP32_0(1), FP32_RAND_V7(1), FP32_RAND_V6(0), FP32_RAND_V5(0), FP32_RAND_V4(1), FP32_RAND_V3(0), FP32_RAND_V2(0), FP32_RAND_V1(1) } },
-              /*mask     */ ~X86_MXCSR_XCPT_MASK,
-              /*daz,fz,rc*/ X86_MXCSR_DAZ, 0, X86_MXCSR_RC_ZERO,
-              /*flags    */ 0, 0 },
+             /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO,
+             /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO,
+             /*256:out  */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO,
+             /*xcpt?    */ false, false },
           { { /*src2     */ { FP32_0(0), FP32_RAND_V0(0), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(1), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(1) } },
             { /*src1     */ { FP32_0(1), FP32_RAND_V6(1), FP32_RAND_V3(0), FP32_RAND_V0(0), FP32_RAND_V1(1), FP32_RAND_V3(0), FP32_RAND_V0(0), FP32_RAND_V3(1) } },
             { /* =>      */ { FP32_0(1), FP32_RAND_V6(1), FP32_RAND_V3(0), FP32_RAND_V0(0), FP32_RAND_V1(1), FP32_RAND_V3(0), FP32_RAND_V0(0), FP32_RAND_V3(1) } },
-              /*mask     */ X86_MXCSR_XCPT_MASK,
-              /*daz,fz,rc*/ X86_MXCSR_DAZ, 0, X86_MXCSR_RC_NEAREST,
-              /*flags    */ 0, 0 },
+             /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ,
+             /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ,
+             /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ,
+             /*xcpt?    */ false, false },
           { { /*src2     */ { FP32_0(0), FP32_RAND_V0(0), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(1), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(1) } },
             { /*src1     */ { FP32_1(0), FP32_RAND_V6(1), FP32_RAND_V3(0), FP32_RAND_V0(0), FP32_RAND_V1(1), FP32_RAND_V3(0), FP32_RAND_V0(0), FP32_RAND_V3(1) } },
             { /* =>      */ { FP32_0(0), FP32_RAND_V6(1), FP32_RAND_V3(0), FP32_RAND_V0(0), FP32_RAND_V1(1), FP32_RAND_V3(0), FP32_RAND_V0(0), FP32_RAND_V3(1) } },
-              /*mask     */ X86_MXCSR_XCPT_MASK,
-              /*daz,fz,rc*/ 0, X86_MXCSR_FZ, X86_MXCSR_RC_DOWN,
-              /*flags    */ 0, 0 },
+             /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
+             /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
+             /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
+             /*xcpt?    */ false, false },
     /*
      * Infinity.
@@ -4970,43 +4977,51 @@
             { /*src1     */ { FP32_1(1),   FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
             { /* =>      */ { FP32_INF(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
-              /*mask     */ ~X86_MXCSR_IM,
-              /*daz,fz,rc*/ 0, 0, X86_MXCSR_RC_NEAREST,
-              /*flags    */ 0, 0 },
+             /*mxcsr:in */ X86_MXCSR_XCPT_MASK & ~X86_MXCSR_IM,
+             /*128:out  */ X86_MXCSR_XCPT_MASK & ~X86_MXCSR_IM,
+             /*256:out  */ X86_MXCSR_XCPT_MASK & ~X86_MXCSR_IM,
+             /*xcpt?    */ false, false },
           { { /*src2     */ { FP32_INF(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
             { /*src1     */ { FP32_1(1),   FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
             { /* =>      */ { FP32_INF(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
-              /*mask     */ X86_MXCSR_XCPT_MASK,
-              /*daz,fz,rc*/ 0, 0, X86_MXCSR_RC_NEAREST,
-              /*flags    */ 0, 0 },
+             /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
+             /*128:out  */ X86_MXCSR_XCPT_MASK,
+             /*256:out  */ X86_MXCSR_XCPT_MASK,
+             /*xcpt?    */ false, false },
           { { /*src2     */ { FP32_INF(0), FP32_RAND_V7(0), FP32_RAND_V6(0), FP32_RAND_V5(1), FP32_RAND_V4(1), FP32_RAND_V3(0), FP32_RAND_V2(1), FP32_RAND_V1(1) } },
             { /*src1     */ { FP32_INF(0), FP32_RAND_V0(0), FP32_RAND_V1(1), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(1), FP32_RAND_V5(1), FP32_RAND_V6(0) } },
             { /* =>      */ { FP32_INF(0), FP32_RAND_V0(0), FP32_RAND_V1(1), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(1), FP32_RAND_V5(1), FP32_RAND_V6(0) } },
-              /*mask     */ ~X86_MXCSR_IM,
-              /*daz,fz,rc*/ X86_MXCSR_DAZ, X86_MXCSR_FZ, X86_MXCSR_RC_NEAREST,
-              /*flags    */ 0, 0 },
+             /*mxcsr:in */ (X86_MXCSR_XCPT_MASK & ~X86_MXCSR_IM) | X86_MXCSR_DAZ | X86_MXCSR_FZ,
+             /*128:out  */ (X86_MXCSR_XCPT_MASK & ~X86_MXCSR_IM) | X86_MXCSR_DAZ | X86_MXCSR_FZ,
+             /*256:out  */ (X86_MXCSR_XCPT_MASK & ~X86_MXCSR_IM) | X86_MXCSR_DAZ | X86_MXCSR_FZ,
+             /*xcpt?    */ false, false },
           { { /*src2     */ { FP32_INF(1), FP32_RAND_V7(1), FP32_RAND_V6(0), FP32_RAND_V5(1), FP32_RAND_V4(0), FP32_RAND_V3(0), FP32_RAND_V2(1), FP32_RAND_V1(1) } },
             { /*src1     */ { FP32_INF(0), FP32_RAND_V0(1), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(0) } },
             { /* =>      */ { FP32_INF(1), FP32_RAND_V0(1), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(0) } },
-              /*mask     */ X86_MXCSR_XCPT_MASK,
-              /*daz,fz,rc*/ 0, 0, X86_MXCSR_RC_ZERO,
-              /*flags    */ 0, 0 },
+             /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
+             /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
+             /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
+             /*xcpt?    */ false, false },
           { { /*src2     */ { FP32_1(0),   FP32_RAND_V0(0), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(1), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(1) } },
             { /*src1     */ { FP32_INF(0), FP32_RAND_V6(1), FP32_RAND_V3(0), FP32_RAND_V2(0), FP32_RAND_V0(1), FP32_RAND_V3(0), FP32_RAND_V4(0), FP32_RAND_V2(1) } },
             { /* =>      */ { FP32_INF(0), FP32_RAND_V6(1), FP32_RAND_V3(0), FP32_RAND_V2(0), FP32_RAND_V0(1), FP32_RAND_V3(0), FP32_RAND_V4(0), FP32_RAND_V2(1) } },
-              /*mask     */ X86_MXCSR_XCPT_MASK,
-              /*daz,fz,rc*/ 0, X86_MXCSR_FZ, X86_MXCSR_RC_NEAREST,
-              /*flags    */ 0, 0 },
+             /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ,
+             /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ,
+             /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ,
+             /*xcpt?    */ false, false },
           { { /*src2     */ { FP32_INF(0), FP32_INF(0), FP32_INF(0), FP32_INF(0), FP32_INF(1), FP32_INF(0), FP32_INF(1), FP32_INF(1) } },
             { /*src1     */ { FP32_1(1),   FP32_INF(0), FP32_INF(1), FP32_INF(0), FP32_INF(1), FP32_INF(1), FP32_INF(1), FP32_INF(0) } },
             { /* =>      */ { FP32_INF(1), FP32_INF(0), FP32_INF(1), FP32_INF(0), FP32_INF(0), FP32_INF(1), FP32_INF(0), FP32_INF(1) } },
-              /*mask     */ ~X86_MXCSR_XCPT_MASK,
-              /*daz,fz,rc*/ 0, X86_MXCSR_FZ, X86_MXCSR_RC_NEAREST,
-              /*flags    */ 0, 0 },
+             /*mxcsr:in */ X86_MXCSR_FZ,
+             /*128:out  */ X86_MXCSR_FZ,
+             /*256:out  */ X86_MXCSR_FZ,
+             /*xcpt?    */ false, false },
           { { /*src2     */ { FP32_INF(1), FP32_QNAN(0), FP32_SNAN(0), FP32_RAND_V0(0), FP32_RAND_V1(1), FP32_QNAN(0), FP32_SNAN(0), FP32_RAND_V2(0) } },
             { /*src1     */ { FP32_INF(0), FP32_QNAN(0), FP32_SNAN(0), FP32_RAND_V0(0), FP32_RAND_V1(1), FP32_QNAN(0), FP32_SNAN(0), FP32_RAND_V2(0) } },
             { /* =>      */ { FP32_INF(1), FP32_QNAN(0), FP32_SNAN(0), FP32_RAND_V0(0), FP32_RAND_V1(0), FP32_QNAN(0), FP32_SNAN(0), FP32_RAND_V2(0) } },
-              /*mask     */ ~X86_MXCSR_XCPT_MASK,
-              /*daz,fz,rc*/ X86_MXCSR_DAZ, X86_MXCSR_FZ, X86_MXCSR_RC_ZERO,
-              /*flags    */ 0, 0 },
+             /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
+             /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
+             /*256:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
+             /*xcpt?    */ false, false },
+#if 0
     /*
      * Normals.
@@ -5280,4 +5295,5 @@
               /*flags    */ X86_MXCSR_IE, X86_MXCSR_IE },
     /** @todo Underflow, Precision; Rounding, FZ etc. */
+#endif
     };
 
@@ -5315,5 +5331,4 @@
                                         g_aXcptConfig3, RT_ELEMENTS(g_aXcptConfig3));
 }
-#endif
 
 
@@ -5346,7 +5361,5 @@
         { "[v]mulps",       bs3CpuInstr4_v_mulps,  0 },
         { "[v]mulpd",       bs3CpuInstr4_v_mulpd,  0 },
-# if 0
         { "[v]mulss",       bs3CpuInstr4_v_mulss,  0 },
-# endif
 #endif
     };
