Changeset 105611 in vbox for trunk/src/VBox/ValidationKit
- Timestamp:
- Aug 7, 2024 3:33:51 AM (8 months ago)
- svn:sync-xref-src-repo-rev:
- 164291
- Location:
- trunk/src/VBox/ValidationKit/bootsectors
- Files:
-
- 2 edited
-
bs3-cpu-instr-4-template.mac (modified) (1 diff)
-
bs3-cpu-instr-4.c32 (modified) (6 diffs)
Legend:
- Unmodified
- Added
- Removed
-
trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-4-template.mac
r105334 r105611 200 200 201 201 ; 202 ;; [v]addsd 203 ; 204 EMIT_INSTR_PLUS_ICEBP addsd, XMM1, XMM2 205 EMIT_INSTR_PLUS_ICEBP addsd, XMM1, FSxBX 206 EMIT_INSTR_PLUS_ICEBP_C64 addsd, XMM8, XMM9 207 EMIT_INSTR_PLUS_ICEBP_C64 addsd, XMM8, FSxBX 208 209 EMIT_INSTR_PLUS_ICEBP vaddsd, XMM1, XMM2, XMM3 210 EMIT_INSTR_PLUS_ICEBP vaddsd, XMM1, XMM2, FSxBX 211 EMIT_INSTR_PLUS_ICEBP_C64 vaddsd, XMM8, XMM9, XMM10 212 EMIT_INSTR_PLUS_ICEBP_C64 vaddsd, XMM8, XMM9, FSxBX 213 214 ; 202 215 ;; [v]haddps 203 216 ; -
trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-4.c32
r105604 r105611 150 150 * Single-precision random values (incl. potentially invalid values). 151 151 * We don't care what the exact values are as these are meant to populate 152 * unmodified operands and be compared bitwise.152 * unmodified parts of operands and be compared bitwise. 153 153 */ 154 154 #define FP32_RAND_V0(a_Sign) RTFLOAT32U_INIT_C(a_Sign, 0x7bacda, 0x55) … … 197 197 #define FP64_SNAN(a_Sign) RTFLOAT64U_INIT_SNAN(a_Sign) 198 198 #define FP64_SNAN_V(a_Sign, a_Val) RTFLOAT64U_INIT_SNAN_EX(a_Sign, a_Val) 199 200 /* 201 * Double-precision random values (incl. potentially invalid values). 202 * We don't care what the exact values are as these are meant to populate 203 * unmodified parts of operands and be compared bitwise. 204 */ 205 #define FP64_RAND_V0(a_Sign) RTFLOAT64U_INIT_C(a_Sign, 0xab07eb7bcebce, 0x777) 206 #define FP64_RAND_V1(a_Sign) RTFLOAT64U_INIT_C(a_Sign, 0x2fa17e10b3c7c, 0x6b6) 207 #define FP64_RAND_V2(a_Sign) RTFLOAT64U_INIT_C(a_Sign, 0xceb1703cbe310, 0x100) 208 #define FP64_RAND_V3(a_Sign) RTFLOAT64U_INIT_C(a_Sign, 0x7134abcdef10f, 0x70f) 199 209 200 210 /* … … 377 387 { 378 388 /** Scalar double-precision floating-point view. */ 379 RTFLOAT64U ar64[ 3];389 RTFLOAT64U ar64[4]; 380 390 /** 256-bit integer view. */ 381 391 RTUINT256U ymm; … … 1076 1086 AssertCompileMembersSameSizeAndOffset(BS3CPUINSTR4_TEST1_VALUES_SS_T, f128FpXcptExpected, BS3CPUINSTR4_TEST1_VALUES_T, f128FpXcptExpected); 1077 1087 AssertCompileMembersSameSizeAndOffset(BS3CPUINSTR4_TEST1_VALUES_SS_T, f256FpXcptExpected, BS3CPUINSTR4_TEST1_VALUES_T, f256FpXcptExpected); 1088 1089 /* 1090 * Test type #1. 1091 * Scalar double-precision. 1092 */ 1093 typedef struct BS3CPUINSTR4_TEST1_VALUES_SD_T 1094 { 1095 X86YMMFLOATSDREG uSrc2; /**< Second source operand. */ 1096 X86YMMFLOATSDREG uSrc1; /**< uDstIn for SSE */ 1097 X86YMMFLOATSDREG uDstOut; /**< Destination output. */ 1098 uint32_t uMxCsr; /**< MXCSR to set prior to executing the instruction. */ 1099 uint32_t u128ExpectedMxCsr; /**< Expected MXCSR for a 128-bit instruction. */ 1100 uint32_t u256ExpectedMxCsr; /**< Expected MXCSR for a 256-bit instructions. */ 1101 uint8_t f128FpXcptExpected; /**< Whether a floating-point exception is expected for a 128-bit instruction. */ 1102 uint8_t f256FpXcptExpected; /**< Whether a floating-point exception is expected for a 256-bit instruction. */ 1103 uint8_t afPadding[2]; /**< Alignment padding. */ 1104 } BS3CPUINSTR4_TEST1_VALUES_SD_T; 1105 AssertCompile(sizeof(BS3CPUINSTR4_TEST1_VALUES_SD_T) == sizeof(BS3CPUINSTR4_TEST1_VALUES_T)); 1106 AssertCompileMembersSameSizeAndOffset(BS3CPUINSTR4_TEST1_VALUES_SD_T, uSrc2, BS3CPUINSTR4_TEST1_VALUES_T, uSrc2); 1107 AssertCompileMembersSameSizeAndOffset(BS3CPUINSTR4_TEST1_VALUES_SD_T, uSrc1, BS3CPUINSTR4_TEST1_VALUES_T, uSrc1); 1108 AssertCompileMembersSameSizeAndOffset(BS3CPUINSTR4_TEST1_VALUES_SD_T, uDstOut, BS3CPUINSTR4_TEST1_VALUES_T, uDstOut); 1109 AssertCompileMembersSameSizeAndOffset(BS3CPUINSTR4_TEST1_VALUES_SD_T, uMxCsr, BS3CPUINSTR4_TEST1_VALUES_T, uMxCsr); 1110 AssertCompileMembersSameSizeAndOffset(BS3CPUINSTR4_TEST1_VALUES_SD_T, u128ExpectedMxCsr, BS3CPUINSTR4_TEST1_VALUES_T, u128ExpectedMxCsr); 1111 AssertCompileMembersSameSizeAndOffset(BS3CPUINSTR4_TEST1_VALUES_SD_T, u256ExpectedMxCsr, BS3CPUINSTR4_TEST1_VALUES_T, u256ExpectedMxCsr); 1112 AssertCompileMembersSameSizeAndOffset(BS3CPUINSTR4_TEST1_VALUES_SD_T, f128FpXcptExpected, BS3CPUINSTR4_TEST1_VALUES_T, f128FpXcptExpected); 1113 AssertCompileMembersSameSizeAndOffset(BS3CPUINSTR4_TEST1_VALUES_SD_T, f256FpXcptExpected, BS3CPUINSTR4_TEST1_VALUES_T, f256FpXcptExpected); 1078 1114 1079 1115 /* … … 2730 2766 { bs3CpuInstr4_addss_XMM8_XMM9_icebp_c64, 255, RM_REG, T_SSE, 8, 8, 9, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, 2731 2767 { bs3CpuInstr4_addss_XMM8_FSxBX_icebp_c64, X86_XCPT_AC, RM_MEM, T_SSE, 8, 8, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, 2768 }; 2769 2770 static BS3CPUINSTR4_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR4_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64); 2771 unsigned const iTest = BS3CPUINSTR4_TEST_MODES_INDEX(bMode); 2772 return bs3CpuInstr4_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests, 2773 g_aXcptConfig3, RT_ELEMENTS(g_aXcptConfig3)); 2774 } 2775 2776 2777 /* 2778 * [V]ADDSD. 2779 */ 2780 BS3_DECL_FAR(uint8_t) bs3CpuInstr4_v_addsd(uint8_t bMode) 2781 { 2782 static BS3CPUINSTR4_TEST1_VALUES_SD_T const s_aValues[] = 2783 { 2784 /* 2785 * Zero. 2786 */ 2787 /* 0*/{ { /*src2 */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } }, 2788 { /*src1 */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } }, 2789 { /* => */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } }, 2790 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 2791 /*128:out */ X86_MXCSR_XCPT_MASK, 2792 /*256:out */ X86_MXCSR_XCPT_MASK, 2793 /*xcpt? */ false, false }, 2794 { { /*src2 */ { FP64_0(0), FP64_RAND_V3(0), FP32_RAND_V2(0), FP32_RAND_V1(1) } }, 2795 { /*src1 */ { FP64_0(0), FP64_RAND_V0(0), FP32_RAND_V1(1), FP32_RAND_V2(1) } }, 2796 { /* => */ { FP64_0(0), FP64_RAND_V0(0), FP32_RAND_V1(1), FP32_RAND_V2(1) } }, 2797 /*mxcsr:in */ 0, 2798 /*128:out */ 0, 2799 /*256:out */ 0, 2800 /*xcpt? */ false, false }, 2801 { { /*src2 */ { FP64_0(0), FP64_RAND_V1(0), FP64_RAND_V2(0), FP64_RAND_V0(1) } }, 2802 { /*src1 */ { FP64_0(0), FP64_RAND_V0(0), FP64_RAND_V1(1), FP64_RAND_V2(1) } }, 2803 { /* => */ { FP64_0(0), FP64_RAND_V0(0), FP64_RAND_V1(1), FP64_RAND_V2(1) } }, 2804 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP, 2805 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP, 2806 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP, 2807 /*xcpt? */ false, false }, 2808 { { /*src2 */ { FP64_0(1), FP64_RAND_V0(0), FP64_RAND_V1(0), FP64_RAND_V2(1) } }, 2809 { /*src1 */ { FP64_0(1), FP64_RAND_V3(1), FP64_RAND_V2(0), FP64_RAND_V0(0) } }, 2810 { /* => */ { FP64_0(1), FP64_RAND_V3(1), FP64_RAND_V2(0), FP64_RAND_V0(0) } }, 2811 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO, 2812 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO, 2813 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO, 2814 /*xcpt? */ false, false }, 2815 { { /*src2 */ { FP64_0(0), FP64_RAND_V0(0), FP64_RAND_V1(0), FP64_RAND_V2(1) } }, 2816 { /*src1 */ { FP64_0(0), FP64_RAND_V3(1), FP64_RAND_V1(0), FP64_RAND_V0(0) } }, 2817 { /* => */ { FP64_0(0), FP64_RAND_V3(1), FP64_RAND_V1(0), FP64_RAND_V0(0) } }, 2818 /*mxcsr:in */ X86_MXCSR_FZ, 2819 /*128:out */ X86_MXCSR_FZ, 2820 /*256:out */ X86_MXCSR_FZ, 2821 /*xcpt? */ false, false }, 2822 { { /*src2 */ { FP64_0(0), FP64_RAND_V1(1), FP64_RAND_V2(0), FP64_RAND_V1(1) } }, 2823 { /*src1 */ { FP64_0(0), FP64_RAND_V3(1), FP64_RAND_V0(0), FP64_RAND_V2(1) } }, 2824 { /* => */ { FP64_0(0), FP64_RAND_V3(1), FP64_RAND_V0(0), FP64_RAND_V1(1) } }, 2825 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_RC_DOWN, 2826 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_DOWN, 2827 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_DOWN, 2828 /*xcpt? */ false, false }, 2829 /** @todo Infinity, Normalds, Denormals, Overflow/Precision, Invalids etc. */ 2830 }; 2831 2832 static BS3CPUINSTR4_TEST1_T const s_aTests16[] = 2833 { 2834 { bs3CpuInstr4_addsd_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE, 1, 1, 2, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, 2835 { bs3CpuInstr4_addsd_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE, 1, 1, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, 2836 2837 { bs3CpuInstr4_vaddsd_XMM1_XMM2_XMM3_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, 2838 { bs3CpuInstr4_vaddsd_XMM1_XMM2_FSxBX_icebp_c16, X86_XCPT_AC, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, 2839 }; 2840 static BS3CPUINSTR4_TEST1_T const s_aTests32[] = 2841 { 2842 { bs3CpuInstr4_addsd_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE, 1, 1, 2, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, 2843 { bs3CpuInstr4_addsd_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE, 1, 1, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, 2844 2845 { bs3CpuInstr4_vaddsd_XMM1_XMM2_XMM3_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, 2846 { bs3CpuInstr4_vaddsd_XMM1_XMM2_FSxBX_icebp_c32, X86_XCPT_AC, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, 2847 }; 2848 static BS3CPUINSTR4_TEST1_T const s_aTests64[] = 2849 { 2850 { bs3CpuInstr4_addsd_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE, 1, 1, 2, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, 2851 { bs3CpuInstr4_addsd_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE, 1, 1, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, 2852 2853 { bs3CpuInstr4_vaddsd_XMM1_XMM2_XMM3_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, 2854 { bs3CpuInstr4_vaddsd_XMM1_XMM2_FSxBX_icebp_c64, X86_XCPT_AC, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, 2855 2856 { bs3CpuInstr4_addsd_XMM8_XMM9_icebp_c64, 255, RM_REG, T_SSE, 8, 8, 9, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, 2857 { bs3CpuInstr4_addsd_XMM8_FSxBX_icebp_c64, X86_XCPT_AC, RM_MEM, T_SSE, 8, 8, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, 2732 2858 }; 2733 2859 … … 5368 5494 { "[v]addpd", bs3CpuInstr4_v_addpd, 0 }, 5369 5495 { "[v]addss", bs3CpuInstr4_v_addss, 0 }, 5496 { "[v]addsd", bs3CpuInstr4_v_addsd, 0 }, 5370 5497 { "[v]haddps", bs3CpuInstr4_v_haddps, 0 }, 5371 5498 { "[v]subps", bs3CpuInstr4_v_subps, 0 },
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