VirtualBox

Changeset 105645 in vbox for trunk/src/VBox/ValidationKit


Ignore:
Timestamp:
Aug 12, 2024 6:45:00 AM (9 months ago)
Author:
vboxsync
svn:sync-xref-src-repo-rev:
164336
Message:

ValidationKit/bootsectors: bugref:10658 SIMD FP testcase: [v]haddpd (W.I.P)

File:
1 edited

Legend:

Unmodified
Added
Removed

  • trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-4.c32

    r105632 r105645  
    36973697          { { /*src2     */ { FP64_0(1), FP64_0(0), FP64_0(1), FP64_0(1) } },
    36983698            { /*src1     */ { FP64_0(0), FP64_0(0), FP64_0(1), FP64_0(0) } },
    3699             { /* =>      */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } },
     3699            { /* =>      */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(1) } },
    37003700              /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
    37013701              /*128:out  */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
    … …  
    37093709              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
    37103710              /*xcpt?    */ false, false },
    3711     /** @todo Infinity, Normals, Denormals, Overflow/Precision, Invalids etc. */
     3711    /*
     3712     * Infinity.
     3713     */
     3714    /* 6*/{ { /*src2     */ { FP64_INF(0),  FP64_INF(1),  FP64_INF(0), FP64_INF(1)  } },
     3715            { /*src1     */ { FP64_INF(1),  FP64_INF(0),  FP64_0(0),   FP64_0(0)    } },
     3716            { /* =>      */ { FP64_QNAN(1), FP64_QNAN(1), FP64_0(0),   FP64_QNAN(1) } },
     3717              /*mxcsr:in */ X86_MXCSR_IM,
     3718              /*128:out  */ X86_MXCSR_IM | X86_MXCSR_IE,
     3719              /*256:out  */ X86_MXCSR_IM | X86_MXCSR_IE,
     3720              /*xcpt?    */ false, false },
     3721          { { /*src2     */ { FP64_0(0), FP64_0(0), FP64_INF(1),  FP64_INF(1) } },
     3722            { /*src1     */ { FP64_0(0), FP64_0(0), FP64_INF(1),  FP64_INF(0) } },
     3723            { /* =>      */ { FP64_0(0), FP64_0(0), FP64_QNAN(1), FP64_INF(1) } },
     3724              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
     3725              /*128:out  */ X86_MXCSR_XCPT_MASK,
     3726              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,
     3727              /*xcpt?    */ false, false },
     3728          { { /*src2     */ { FP64_INF(0),  FP64_INF(1), FP64_INF(0),  FP64_INF(1)  } },
     3729            { /*src1     */ { FP64_INF(1),  FP64_INF(0), FP64_0(0),    FP64_0(0)    } },
     3730            { /* =>      */ { FP64_QNAN(1), FP64_0(0),   FP64_QNAN(1), FP64_QNAN(1) } },
     3731              /*mxcsr:in */ X86_MXCSR_FZ,
     3732              /*128:out  */ X86_MXCSR_FZ | X86_MXCSR_IE,
     3733              /*256:out  */ X86_MXCSR_FZ | X86_MXCSR_IE,
     3734              /*xcpt?    */ true, true },
     3735          { { /*src2     */ { FP64_INF(1),  FP64_INF(1), FP64_INF(0), FP64_0(0)   } },
     3736            { /*src1     */ { FP64_INF(0),  FP64_INF(0), FP64_INF(1), FP64_0(0)   } },
     3737            { /* =>      */ { FP64_INF(0),  FP64_INF(1), FP64_INF(1), FP64_INF(0) } },
     3738              /*mxcsr:in */ 0,
     3739              /*128:out  */ 0,
     3740              /*256:out  */ 0,
     3741              /*xcpt?    */ false, false },
     3742          { { /*src2     */ { FP64_INF(0),  FP64_QNAN(1), FP64_INF(1),  FP64_QNAN(0) } },
     3743            { /*src1     */ { FP64_INF(0),  FP64_QNAN(0), FP64_INF(1),  FP64_QNAN(0) } },
     3744            { /* =>      */ { FP64_QNAN(0), FP64_QNAN(1), FP64_QNAN(0), FP64_QNAN(0) } },
     3745              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
     3746              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
     3747              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
     3748              /*xcpt?    */ false, false },
     3749    /** @todo Normals, Denormals, Overflow/Precision, Invalids etc. */
    37123750    };
    37133751
    37143752    static BS3CPUINSTR4_TEST1_T const s_aTests16[] =
    37153753    {
    3716         { bs3CpuInstr4_haddps_XMM1_XMM2_icebp_c16,  255, RM_REG, T_SSE, 1, 1, 2,   RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
    3717         { bs3CpuInstr4_haddps_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE, 1, 1, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
    3718 
    3719         { bs3CpuInstr4_vhaddps_XMM1_XMM2_XMM3_icebp_c16,  255, RM_REG, T_AVX_128, 1, 2, 3,   RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
    3720         { bs3CpuInstr4_vhaddps_XMM1_XMM2_FSxBX_icebp_c16, 255, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
    3721 
    3722         { bs3CpuInstr4_vhaddps_YMM1_YMM2_YMM3_icebp_c16,  255, RM_REG, T_AVX_256, 1, 2, 3,   RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
    3723         { bs3CpuInstr4_vhaddps_YMM1_YMM2_FSxBX_icebp_c16, 255, RM_MEM, T_AVX_256, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
     3754        { bs3CpuInstr4_haddpd_XMM1_XMM2_icebp_c16,  255, RM_REG, T_SSE, 1, 1, 2,   RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
     3755        { bs3CpuInstr4_haddpd_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE, 1, 1, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
     3756
     3757        { bs3CpuInstr4_vhaddpd_XMM1_XMM2_XMM3_icebp_c16,  255, RM_REG, T_AVX_128, 1, 2, 3,   RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
     3758        { bs3CpuInstr4_vhaddpd_XMM1_XMM2_FSxBX_icebp_c16, 255, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
     3759
     3760        { bs3CpuInstr4_vhaddpd_YMM1_YMM2_YMM3_icebp_c16,  255, RM_REG, T_AVX_256, 1, 2, 3,   RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
     3761        { bs3CpuInstr4_vhaddpd_YMM1_YMM2_FSxBX_icebp_c16, 255, RM_MEM, T_AVX_256, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
    37243762    };
    37253763    static BS3CPUINSTR4_TEST1_T const s_aTests32[] =
    37263764    {
    3727         { bs3CpuInstr4_haddps_XMM1_XMM2_icebp_c32,  255, RM_REG, T_SSE, 1, 1, 2,   RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
    3728         { bs3CpuInstr4_haddps_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE, 1, 1, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
    3729 
    3730         { bs3CpuInstr4_vhaddps_XMM1_XMM2_XMM3_icebp_c32,  255, RM_REG, T_AVX_128, 1, 2, 3,   RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
    3731         { bs3CpuInstr4_vhaddps_XMM1_XMM2_FSxBX_icebp_c32, 255, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
    3732 
    3733         { bs3CpuInstr4_vhaddps_YMM1_YMM2_YMM3_icebp_c32,  255, RM_REG, T_AVX_256, 1, 2, 3,   RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
    3734         { bs3CpuInstr4_vhaddps_YMM1_YMM2_FSxBX_icebp_c32, 255, RM_MEM, T_AVX_256, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
     3765        { bs3CpuInstr4_haddpd_XMM1_XMM2_icebp_c32,  255, RM_REG, T_SSE, 1, 1, 2,   RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
     3766        { bs3CpuInstr4_haddpd_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE, 1, 1, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
     3767
     3768        { bs3CpuInstr4_vhaddpd_XMM1_XMM2_XMM3_icebp_c32,  255, RM_REG, T_AVX_128, 1, 2, 3,   RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
     3769        { bs3CpuInstr4_vhaddpd_XMM1_XMM2_FSxBX_icebp_c32, 255, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
     3770
     3771        { bs3CpuInstr4_vhaddpd_YMM1_YMM2_YMM3_icebp_c32,  255, RM_REG, T_AVX_256, 1, 2, 3,   RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
     3772        { bs3CpuInstr4_vhaddpd_YMM1_YMM2_FSxBX_icebp_c32, 255, RM_MEM, T_AVX_256, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
    37353773    };
    37363774    static BS3CPUINSTR4_TEST1_T const s_aTests64[] =
    37373775    {
    3738         { bs3CpuInstr4_haddps_XMM1_XMM2_icebp_c64,  255, RM_REG, T_SSE, 1, 1, 2,   RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
    3739         { bs3CpuInstr4_haddps_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE, 1, 1, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
    3740 
    3741         { bs3CpuInstr4_vhaddps_XMM1_XMM2_XMM3_icebp_c64,  255, RM_REG, T_AVX_128, 1, 2, 3,   RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
    3742         { bs3CpuInstr4_vhaddps_XMM1_XMM2_FSxBX_icebp_c64, 255, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
    3743 
    3744         { bs3CpuInstr4_vhaddps_YMM1_YMM2_YMM3_icebp_c64,  255, RM_REG, T_AVX_256, 1, 2, 3,   RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
    3745         { bs3CpuInstr4_vhaddps_YMM1_YMM2_FSxBX_icebp_c64, 255, RM_MEM, T_AVX_256, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
    3746 
    3747         { bs3CpuInstr4_haddps_XMM8_XMM9_icebp_c64,  255, RM_REG, T_SSE, 8, 8, 9,   RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
    3748         { bs3CpuInstr4_haddps_XMM8_FSxBX_icebp_c64, 255, RM_MEM, T_SSE, 8, 8, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
    3749 
    3750         { bs3CpuInstr4_vhaddps_YMM8_YMM9_YMM10_icebp_c64, 255, RM_REG, T_AVX_256, 8, 9, 10,  RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
    3751         { bs3CpuInstr4_vhaddps_YMM8_YMM9_FSxBX_icebp_c64, 255, RM_MEM, T_AVX_256, 8, 9, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
     3776        { bs3CpuInstr4_haddpd_XMM1_XMM2_icebp_c64,  255, RM_REG, T_SSE, 1, 1, 2,   RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
     3777        { bs3CpuInstr4_haddpd_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE, 1, 1, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
     3778
     3779        { bs3CpuInstr4_vhaddpd_XMM1_XMM2_XMM3_icebp_c64,  255, RM_REG, T_AVX_128, 1, 2, 3,   RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
     3780        { bs3CpuInstr4_vhaddpd_XMM1_XMM2_FSxBX_icebp_c64, 255, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
     3781
     3782        { bs3CpuInstr4_vhaddpd_YMM1_YMM2_YMM3_icebp_c64,  255, RM_REG, T_AVX_256, 1, 2, 3,   RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
     3783        { bs3CpuInstr4_vhaddpd_YMM1_YMM2_FSxBX_icebp_c64, 255, RM_MEM, T_AVX_256, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
     3784
     3785        { bs3CpuInstr4_haddpd_XMM8_XMM9_icebp_c64,  255, RM_REG, T_SSE, 8, 8, 9,   RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
     3786        { bs3CpuInstr4_haddpd_XMM8_FSxBX_icebp_c64, 255, RM_MEM, T_SSE, 8, 8, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
     3787
     3788        { bs3CpuInstr4_vhaddpd_YMM8_YMM9_YMM10_icebp_c64, 255, RM_REG, T_AVX_256, 8, 9, 10,  RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
     3789        { bs3CpuInstr4_vhaddpd_YMM8_YMM9_FSxBX_icebp_c64, 255, RM_MEM, T_AVX_256, 8, 9, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
    37523790    };
    37533791
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