Changeset 105646 in vbox for trunk

Timestamp:

Aug 12, 2024 7:54:11 AM (5 months ago)

Author:

vboxsync

Message:

ValidationKit/bootsectors: bugref:10658 SIMD FP testcase: [v]haddpd (W.I.P)

File:

• trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-4.c32 (modified) (1 diff)

trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-4.c32

@@ -3747 +3747 @@
               /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
               /*xcpt?    */ false, false },
-    /** @todo Normals, Denormals, Overflow/Precision, Invalids etc. */
+    /*
+     * Overflow, Precision.
+     */
+    /*11*/{ { /*src2     */ { FP64_0(0), FP64_0(0), FP64_NORM_MIN(1), FP64_NORM_MIN(1) } },
+            { /*src1     */ { FP64_0(0), FP64_0(0), FP64_NORM_MAX(1), FP64_NORM_MAX(1) } },
+            { /* =>      */ { FP64_0(0), FP64_0(0), FP64_0(0),        FP64_0(0)        } },
+              /*mxcsr:in */ 0,
+              /*128:out  */ 0,
+              /*256:out  */ X86_MXCSR_OE,
+              /*xcpt?    */ false, true },
+          { { /*src2     */ { FP64_NORM_MIN(1), FP64_NORM_MIN(1),                                     FP64_NORM_MAX(0), FP64_NORM_MAX(0) } },
+            { /*src1     */ { FP64_NORM_MAX(1), FP64_NORM_MAX(1),                                     FP64_NORM_MAX(1), FP64_NORM_MAX(1) } },
+            { /* =>      */ { FP64_INF(1),      FP64_V(1, FP32_FRAC_NORM_MIN, FP32_EXP_NORM_MIN + 1), FP64_INF(1),      FP64_INF(0),     } },
+              /*mxcsr:in */ X86_MXCSR_OM | X86_MXCSR_PM,
+              /*128:out  */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_OE | X86_MXCSR_PE,
+              /*256:out  */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_OE | X86_MXCSR_PE,
+              /*xcpt?    */ false, false },
+          { { /*src2     */ { FP64_NORM_MAX(1), FP64_NORM_MAX(0), FP64_0(0),        FP64_0(0)        } },
+            { /*src1     */ { FP64_NORM_MAX(0), FP64_NORM_MAX(0), FP64_NORM_MAX(1), FP64_NORM_MAX(1) } },
+            { /* =>      */ { FP64_NORM_MAX(0), FP64_0(0),        FP64_NORM_MAX(1), FP64_0(0)        } },
+              /*mxcsr:in */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_RC_ZERO,
+              /*128:out  */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_RC_ZERO | X86_MXCSR_OE | X86_MXCSR_PE,
+              /*256:out  */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_RC_ZERO | X86_MXCSR_OE | X86_MXCSR_PE,
+              /*xcpt?    */ false, false },
+          { { /*src2     */ { FP64_NORM_MAX(0), FP64_NORM_MAX(1), FP64_0(0),        FP64_NORM_MIN(1) } },
+            { /*src1     */ { FP64_NORM_MAX(0), FP64_NORM_MAX(0), FP64_NORM_MIN(1), FP64_NORM_MIN(1) } },
+            { /* =>      */ { FP64_INF(0),      FP64_0(0),        FP64_V(1, 0, 2),  FP64_NORM_MIN(1) } },
+              /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_RC_UP,
+              /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_RC_UP | X86_MXCSR_OE | X86_MXCSR_PE,
+              /*256:out  */ X86_MXCSR_DAZ | X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_RC_UP | X86_MXCSR_OE | X86_MXCSR_PE,
+              /*xcpt?    */ false, false },
+          { { /*src2     */ { FP64_NORM_MAX(0), FP64_NORM_MAX(0), FP64_0(0),                                            FP64_NORM_MAX(0) } },
+            { /*src1     */ { FP64_NORM_MIN(1), FP64_NORM_MAX(0), FP64_NORM_MIN(0),                                     FP64_NORM_MAX(1) } },
+            { /* =>      */ { FP64_NORM_MAX(0), FP64_INF(0),      FP64_V(1, FP64_FRAC_NORM_MAX - 1, FP64_EXP_NORM_MAX), FP64_NORM_MAX(0) } },
+              /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_RC_UP,
+              /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_RC_UP | X86_MXCSR_OE | X86_MXCSR_PE,
+              /*256:out  */ X86_MXCSR_DAZ | X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_RC_UP | X86_MXCSR_OE | X86_MXCSR_PE,
+              /*xcpt?    */ false, false },
+          { { /*src2     */ { FP64_NORM_MAX(0), FP64_NORM_MAX(0), FP64_NORM_MAX(0), FP64_0(0)        } },
+            { /*src1     */ { FP64_NORM_MIN(1), FP64_NORM_MIN(1), FP64_NORM_MIN(0), FP64_NORM_MIN(0) } },
+            { /* =>      */ { FP64_V(1, 0, 2),  FP64_NORM_MAX(0), FP64_V(0, 0, 2),  FP64_NORM_MAX(0) } },
+              /*mxcsr:in */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_RC_ZERO,
+              /*128:out  */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_RC_ZERO | X86_MXCSR_OE | X86_MXCSR_PE,
+              /*256:out  */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_RC_ZERO | X86_MXCSR_OE | X86_MXCSR_PE,
+              /*xcpt?    */ false, false },
+          { { /*src2     */ { FP64_0(0),                                        FP64_NORM_MAX(0), FP64_NORM_MIN(1), FP64_NORM_MIN(0) } },
+            { /*src1     */ { FP64_NORM_MAX(1),                                 FP64_NORM_MAX(1), FP64_NORM_MIN(1), FP64_NORM_MIN(1) } },
+            { /* =>      */ { FP64_V(1, FP64_FRAC_NORM_MAX, FP64_EXP_NORM_MAX), FP64_NORM_MAX(0), FP64_V(1, 0, 2),  FP64_0(0)        } },
+              /*mxcsr:in */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_RC_ZERO,
+              /*128:out  */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_RC_ZERO | X86_MXCSR_OE | X86_MXCSR_PE,
+              /*256:out  */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_RC_ZERO | X86_MXCSR_OE | X86_MXCSR_PE,
+              /*xcpt?    */ false, false },
+          { { /*src2     */ { FP64_0(0), FP64_0(0), FP64_NORM_MAX(0), FP64_NORM_MAX(1) } },
+            { /*src1     */ { FP64_0(0), FP64_0(0), FP64_NORM_MAX(0), FP64_NORM_MAX(0) } },
+            { /* =>      */ { FP64_0(0), FP64_0(0), FP64_NORM_MAX(0), FP64_NORM_MAX(1) } },
+              /*mxcsr:in */ X86_MXCSR_RC_ZERO,
+              /*128:out  */ X86_MXCSR_RC_ZERO,
+              /*256:out  */ X86_MXCSR_RC_ZERO | X86_MXCSR_OE,
+              /*xcpt?    */ false, true },
+          { { /*src2     */ { FP64_NORM_SAFE_INT_MIN(0), FP64_NORM_SAFE_INT_MAX(0), FP64_NORM_SAFE_INT_MAX(0), FP64_NORM_SAFE_INT_MAX(1) } },
+            { /*src1     */ { FP64_NORM_SAFE_INT_MAX(0), FP64_NORM_SAFE_INT_MIN(0), FP64_NORM_SAFE_INT_MAX(0), FP64_NORM_SAFE_INT_MIN(0) } },
+            { /* =>      */ { FP64_NORM_SAFE_INT_MAX(0), FP64_NORM_SAFE_INT_MAX(0), FP64_NORM_SAFE_INT_MAX(0), FP64_0(0)                 } },
+              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
+              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO | X86_MXCSR_PE,
+              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO | X86_MXCSR_PE,
+              /*xcpt?    */ false, false },
+    /** @todo Normals, Denormals, Invalids etc. */
     };