Changeset 105647 in vbox

Timestamp:

Aug 12, 2024 9:10:06 AM (7 months ago)

Author:

vboxsync

svn:sync-xref-src-repo-rev:

164338

Message:

ValidationKit/bootsectors: bugref:10658 SIMD FP testcase: [v]haddpd (W.I.P)

File:

• trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-4.c32 (modified) (1 diff)

trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-4.c32

@@ -3813 +3813 @@
               /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO | X86_MXCSR_PE,
               /*xcpt?    */ false, false },
-    /** @todo Normals, Denormals, Invalids etc. */
+    /*
+     * Normals.
+     */
+    /*20*/{ { /*src2     */ { FP64_NORM_MIN(0), FP64_NORM_MIN(1), FP64_NORM_V2(1), FP64_NORM_V2(0) } },
+            { /*src1     */ { FP64_NORM_MAX(0), FP64_NORM_MAX(1), FP64_NORM_V1(0), FP64_NORM_V1(1) } },
+            { /* =>      */ { FP64_0(1),        FP64_0(1),        FP64_0(1),       FP64_0(1)       } },
+              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
+              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
+              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
+              /*xcpt?    */ false, false },
+          { { /*src2     */ { FP64_V(0, 0xb800000000000, 0x404)/*  55*/, FP64_V(0, 0xc000000000000, 0x401)/*  7*/, FP64_V(0, 0x26580b4800000, 0x41d)/*1234567890*/, FP64_V(1, 0x26580b4800000, 0x41d)/*-1234567890*/ } },
+            { /*src1     */ { FP64_V(0, 0,               0x409)/*1024*/, FP64_V(0, 0,               0x408)/*512*/, FP64_V(0, 0xd6f3458800000, 0x41c)/* 987654321*/, FP64_V(1, 0x9000000000000, 0x405)/*       -100*/ } },
+            { /* =>      */ { FP64_V(0, 0x8000000000000, 0x409)/*1536*/, FP64_V(0, 0xf000000000000, 0x404)/* 62*/, FP64_V(0, 0xd6f3426800000, 0x41c)/* 987654221*/, FP64_0(0)                                        } },
+              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
+              /*128:out  */ X86_MXCSR_XCPT_MASK,
+              /*256:out  */ X86_MXCSR_XCPT_MASK,
+              /*xcpt?    */ false, false },
+          { { /*src2     */ { FP64_V(0, 0xc122186c3cfd0, 0x42d)/*123456789876543.25*/, FP64_V(0, 0xb88e0395d49b0, 0x42d)/*121098765432102.75*/, FP64_NORM_V2(1), FP64_NORM_V2(0) } },
+            { /*src1     */ { FP64_V(0, 0xcf0033a34f337, 0x432)/*4072598000007579.5*/, FP64_V(0, 0xd6eca42000000, 0x419)/*      123450000.50*/, FP64_NORM_V0(1), FP64_NORM_V0(0) } },
+            { /* =>      */ { FP64_V(0, 0xcf00348ec5858, 0x432)/*4072598123457580.0*/, FP64_V(0, 0xbcd80e0108cc0, 0x42e)/*244555555308646.00*/, FP64_0(0),       FP64_0(0)       } },
+              /*mxcsr:in */ 0,
+              /*128:out  */ 0,
+              /*256:out  */ 0,
+              /*xcpt?    */ false, false },
+          { { /*src2     */ { FP64_NORM_SAFE_INT_MAX(0),                                FP64_1(1),                                                FP64_NORM_V3(1), FP64_NORM_V3(0) } },
+            { /*src1     */ { FP64_V(0, FP64_FRAC_NORM_MAX - 1, FP64_EXP_SAFE_INT_MAX), FP64_1(0),                                                FP64_NORM_V1(0), FP64_NORM_V1(1) } },
+            { /* =>      */ { FP64_NORM_SAFE_INT_MAX(0),                                FP64_V(0, FP64_FRAC_NORM_MAX - 1, FP64_EXP_SAFE_INT_MAX), FP64_0(0),       FP64_0(0)       } },
+              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
+              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
+              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
+              /*xcpt?    */ false, false },
+          { { /*src2     */ { FP64_NORM_SAFE_INT_MIN(0), FP64_0(0),                 FP64_NORM_SAFE_INT_MIN(1), FP64_NORM_SAFE_INT_MIN(1) } },
+            { /*src1     */ { FP64_NORM_SAFE_INT_MIN(1), FP64_NORM_SAFE_INT_MIN(0), FP64_NORM_SAFE_INT_MIN(0), FP64_NORM_SAFE_INT_MIN(0) } },
+            { /* =>      */ { FP64_0(1),                 FP64_NORM_SAFE_INT_MIN(0), FP64_V(0, 0, 2),           FP64_V(1, 0, 2)           } },
+              /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
+              /*128:out  */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
+              /*256:out  */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
+              /*xcpt?    */ false, false },
+          { { /*src2     */ { FP64_V(0, 0xc122186c3cfd0, 0x42d)/*123456789876543.25*/, FP64_V(1, 0xc122186c3cfd0, 0x42d)/*-123456789876543.25*/, FP64_NORM_SAFE_INT_MIN(1), FP64_NORM_SAFE_INT_MIN(1) } },
+            { /*src1     */ { FP64_V(0, 0xc122186c3cfd0, 0x42d)/*123456789876543.25*/, FP64_V(0, 0xb88e0395d49b0, 0x42d)/* 121098765432102.75*/, FP64_NORM_V0(0),           FP64_NORM_V0(1)           } },
+            { /* =>      */ { FP64_V(0, 0xbcd80e0108cc0, 0x42e)/*244555555308646.00*/, FP64_0(0),                                                FP64_0(0),                 FP64_V(1, 0, 2)           } },
+              /*mxcsr:in */ X86_MXCSR_RC_UP,
+              /*128:out  */ X86_MXCSR_RC_UP,
+              /*256:out  */ X86_MXCSR_RC_UP,
+              /*xcpt?    */ false, false },
+          /** @todo Denormals, Invalids etc. */
     };