Changeset 105665 in vbox for trunk/src/VBox/ValidationKit
- Timestamp:
- Aug 14, 2024 8:47:28 AM (6 months ago)
- Location:
- trunk/src/VBox/ValidationKit/bootsectors
- Files:
-
- 2 edited
-
bs3-cpu-instr-3-template.mac (modified) (3 diffs)
-
bs3-cpu-instr-3.c32 (modified) (2 diffs)
Legend:
- Unmodified
- Added
- Removed
-
trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-3-template.mac
r104723 r105665 64 64 %define BS3CPUINSTR3_PROC_BEGIN_CMN_DEFINED 65 65 %macro BS3CPUINSTR3_PROC_BEGIN_CMN 1 66 %define BS3CPUINSTR3_LABEL %1 66 67 align 8, db 0cch 67 68 db BS3_CMN_NM(%1).again - BS3_CMN_NM(%1) … … 70 71 fs 71 72 %endif 73 %endmacro 74 %macro BS3CPUINSTR3_PROC_END_CMN 0 75 BS3_PROC_END_CMN BS3CPUINSTR3_LABEL 76 %undef BS3CPUINSTR3_LABEL 72 77 %endmacro 73 78 %endif ; !BS3CPUINSTR3_PROC_BEGIN_CMN_DEFINED … … 2421 2426 EMIT_V_PEXTRW_ALT_INSTR 000h 2422 2427 EMIT_V_PEXTRW_ALT_INSTR 0FFh 2428 2429 ; 2430 ; vgather / vpgather instructions 2431 ; 2432 %ifndef EMIT_VGATHER_INSTR_DEFINED 2433 %define EMIT_VGATHER_INSTR_DEFINED 2434 2435 ;; @param 1 instruction name 2436 ;; @param 2 destination register 2437 ;; @param 3 base register 2438 ;; @param 4 base register offset 2439 ;; @param 5 vector register 2440 ;; @param 6 vector register scale factor 2441 ;; @param 7 mask register 2442 %macro EMIT_ONE_VGATHER_INSTR 7 2443 BS3CPUINSTR3_PROC_BEGIN_CMN bs3CpuInstr3_ %+ %1 %+ _ %+ %2 %+ _ %+ %3 %+ _plus_ %+ %4 %+ _plus_ %+ %5 %+ _x_ %+ %6 %+ _ %+ %7 %+ _icebp 2444 fs 2445 %1 %2, [%3 + %4 + %5 * %6], %7 2446 .again: 2447 icebp 2448 jmp .again 2449 BS3CPUINSTR3_PROC_END_CMN 2450 %endmacro ; EMIT_ONE_VGATHER_INSTR 2451 %macro EMIT_NEG_VGATHER_INSTR 7 2452 BS3CPUINSTR3_PROC_BEGIN_CMN bs3CpuInstr3_ %+ %1 %+ _ %+ %2 %+ _ %+ %3 %+ _less_ %+ %4 %+ _plus_ %+ %5 %+ _x_ %+ %6 %+ _ %+ %7 %+ _icebp 2453 fs 2454 %1 %2, [%3 - %4 + %5 * %6], %7 2455 .again: 2456 icebp 2457 jmp .again 2458 BS3CPUINSTR3_PROC_END_CMN 2459 %endmacro ; EMIT_NEG_VGATHER_INSTR 2460 2461 ;; @param 1 instruction name 2462 ;; @param 2 'xmm' or 'ymm': type of destination register 2463 ;; @param 3 'xmm' or 'ymm': type of vector register 2464 ;; @param 4 'xmm' or 'ymm': type of mask register 2465 %macro EMIT_VGATHER_INSTR_BLOCK 4 2466 EMIT_ONE_VGATHER_INSTR %1, %2 %+ 0, ebx, 0, %3 %+ 0, 1, %4 %+ 2 ;; UD: dest == index: v?gather?? ?mm0, [ebx+0+1*?mm0], ?mm2 2467 EMIT_ONE_VGATHER_INSTR %1, %2 %+ 0, ebx, 0, %3 %+ 1, 1, %4 %+ 0 ;; UD: dest == mask: v?gather?? ?mm0, [ebx+0+1*?mm1], ?mm0 2468 EMIT_ONE_VGATHER_INSTR %1, %2 %+ 0, ebx, 0, %3 %+ 1, 1, %4 %+ 1 ;; UD: index == mask: v?gather?? ?mm0, [ebx+0+1*?mm1], ?mm1 2469 EMIT_ONE_VGATHER_INSTR %1, %2 %+ 0, ebx, 0, %3 %+ 1, 1, %4 %+ 2 ;; baseline: v?gather?? ?mm0, [ebx+0+1*?mm1], ?mm2 2470 EMIT_ONE_VGATHER_INSTR %1, %2 %+ 0, ebx, 2, %3 %+ 1, 1, %4 %+ 2 ;; offset8: v?gather?? ?mm0, [ebx+2+1*?mm1], ?mm2 2471 EMIT_NEG_VGATHER_INSTR %1, %2 %+ 0, ebx, 2, %3 %+ 1, 1, %4 %+ 2 ;; -offset8: v?gather?? ?mm0, [ebx-2+1*?mm1], ?mm2 2472 EMIT_ONE_VGATHER_INSTR %1, %2 %+ 0, ebx, 153, %3 %+ 1, 1, %4 %+ 2 ;; offset32: v?gather?? ?mm0, [ebx+153+1*?mm1], ?mm2 2473 EMIT_NEG_VGATHER_INSTR %1, %2 %+ 0, ebx, 153, %3 %+ 1, 1, %4 %+ 2 ;; -offset32: v?gather?? ?mm0, [ebx-153+1*?mm1], ?mm2 2474 EMIT_ONE_VGATHER_INSTR %1, %2 %+ 0, ebx, 0, %3 %+ 1, 2, %4 %+ 2 ;; scale: v?gather?? ?mm0, [ebx+0+2*?mm1], ?mm2 2475 %if TMPL_BITS == 64 2476 EMIT_ONE_VGATHER_INSTR %1, %2 %+ 0, rbx, 0, %3 %+ 1, 1, %4 %+ 2 ;; 64-bit base reg: v?gather?? ?mm0, [rbx+0+1*?mm1], ?mm2 2477 EMIT_ONE_VGATHER_INSTR %1, %2 %+ 8, r8d, 0, %3 %+ 9, 1, %4 %+ 10 ;; 64-bit-only regs: v?gather?? ?mm8, [r8d+0+1*?mm9], ?mm10 2478 %endif 2479 %endmacro ; EMIT_VGATHER_INSTR_BLOCK 2480 2481 ;; @param 1 instruction name 2482 ;; @param 2 'xmm' or 'ymm': type of destination register for 256-bit variants 2483 ;; @param 3 'xmm' or 'ymm': type of vector register for 256-bit variants 2484 ;; @param 4 'xmm' or 'ymm': type of mask register for 256-bit variants 2485 %macro EMIT_VGATHER_INSTR_BLOCKS 4 2486 EMIT_VGATHER_INSTR_BLOCK %1, xmm, xmm, xmm 2487 EMIT_VGATHER_INSTR_BLOCK %1, %2, %3, %4 2488 %endmacro ; EMIT_VGATHER_INSTR_BLOCKS 2489 2490 %endif ; !EMIT_VGATHER_INSTR_DEFINED 2491 2492 EMIT_VGATHER_INSTR_BLOCKS vgatherdps, ymm, ymm, ymm 2493 EMIT_VGATHER_INSTR_BLOCKS vgatherqps, xmm, ymm, xmm 2494 EMIT_VGATHER_INSTR_BLOCKS vgatherdpd, ymm, xmm, ymm 2495 EMIT_VGATHER_INSTR_BLOCKS vgatherqpd, ymm, ymm, ymm 2496 2497 EMIT_VGATHER_INSTR_BLOCKS vpgatherdd, ymm, ymm, ymm 2498 EMIT_VGATHER_INSTR_BLOCKS vpgatherqd, xmm, ymm, xmm 2499 EMIT_VGATHER_INSTR_BLOCKS vpgatherdq, ymm, xmm, ymm 2500 EMIT_VGATHER_INSTR_BLOCKS vpgatherqq, ymm, ymm, ymm 2423 2501 2424 2502 ; -
trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-3.c32
r104776 r105665 14732 14732 g_aXcptConfig4, RT_ELEMENTS(g_aXcptConfig4)); 14733 14733 } 14734 14735 14736 /* 14737 * Initialize the global buffer for 'gather' instruction tests. 14738 * 14739 * pbBuf is a buffer of 2x 4K pages which are accessible to the 14740 * instruction under test. The pointer we receive actually points to 14741 * to the midpoint, one page into this buffer; the instruction is 14742 * passed this same pointer to the middle of the buffer. 14743 * 14744 * Initialize this memory to a specific pattern so that reads will produce 14745 * deterministic, identifiable patterns. 14746 * 14747 * The buffer is initialized with 16-bit integers giving the offset in 14748 * bytes away from that center pointer; i.e. negative values in the page 14749 * below the pointer, positive in the page above. 14750 */ 14751 BS3_DECL_FAR(void) bs3CpuInstr3GatherBufSetup(uint8_t BS3_FAR *pbBuf) 14752 { 14753 uint16_t BS3_FAR *pBufEntry = (uint16_t BS3_FAR *)pbBuf; 14754 uint32_t iEntry; 14755 14756 for (iEntry = 0; iEntry < X86_PAGE_SIZE; ++iEntry) 14757 pBufEntry[iEntry] = iEntry * 2 - X86_PAGE_SIZE; 14758 } 14759 14760 14761 /* 14762 * Test type #7 - three source XMM/YMM operands, 14763 * two of which are written, 14764 * and test-table-driven control over the memory pointer. 14765 * 14766 * Probably only used by the V[P]GATHER instruction family. 14767 * 14768 * Derived from 'type #5' (at r163284). 14769 */ 14770 14771 typedef struct BS3CPUINSTR3_TEST7_VALUES_T 14772 { 14773 RTUINT256U uMask; 14774 RTUINT256U uMaskPf; 14775 RTUINT256U uOffsets; 14776 RTUINT256U uDstInit; 14777 RTUINT256U uDstOut; 14778 uint8_t fFlags; 14779 } BS3CPUINSTR3_TEST7_VALUES_T; 14780 14781 typedef struct BS3CPUINSTR3_TEST7_T 14782 { 14783 FPFNBS3FAR pfnWorker; 14784 uint8_t bXcpt; 14785 int32_t cMemOpOffset; 14786 uint8_t enmType; 14787 uint8_t iMmDst; 14788 uint8_t iGpMem; 14789 uint8_t iMmOff; 14790 uint8_t iMmMsk; 14791 uint8_t cValues; 14792 BS3CPUINSTR3_TEST7_VALUES_T const BS3_FAR *paValues; 14793 } BS3CPUINSTR3_TEST7_T; 14794 14795 typedef struct BS3CPUINSTR3_TEST7_MODE_T 14796 { 14797 BS3CPUINSTR3_TEST7_T const BS3_FAR *paTests; 14798 unsigned cTests; 14799 } BS3CPUINSTR3_TEST7_MODE_T; 14800 14801 /** Initializer for a BS3CPUINSTR3_TEST7_MODE_T array (three entries). */ 14802 #define BS3CPUINSTR3_TEST7_MODES_INIT(a_aTests16, a_aTests32, a_aTests64) \ 14803 { { a_aTests16, RT_ELEMENTS(a_aTests16) }, { a_aTests32, RT_ELEMENTS(a_aTests32) }, { a_aTests64, RT_ELEMENTS(a_aTests64) } } 14804 14805 14806 /** 14807 * Test type #7 worker. 14808 */ 14809 static uint8_t bs3CpuInstr3_WorkerTestType7(uint8_t bMode, BS3CPUINSTR3_TEST7_T const BS3_FAR *paTests, unsigned cTests, 14810 PCBS3CPUINSTR3_CONFIG_T paConfigs, unsigned cConfigs) 14811 { 14812 BS3REGCTX Ctx; 14813 BS3TRAPFRAME TrapFrame; 14814 const char BS3_FAR * const pszMode = Bs3GetModeName(bMode); 14815 uint8_t bRing = BS3_MODE_IS_V86(bMode) ? 3 : 0; 14816 uint8_t BS3_FAR *pbBuf = g_pbBuf; 14817 uint32_t cbBuf = g_cbBuf; 14818 PBS3EXTCTX pExtCtxOut; 14819 PBS3EXTCTX pExtCtx = bs3CpuInstr3AllocExtCtxs(&pExtCtxOut); 14820 if (!pExtCtx) 14821 return 0; 14822 14823 /* Ensure the structures are allocated before we sample the stack pointer. */ 14824 Bs3MemSet(&Ctx, 0, sizeof(Ctx)); 14825 Bs3MemSet(&TrapFrame, 0, sizeof(TrapFrame)); 14826 14827 /* 14828 * Create test context. 14829 */ 14830 pbBuf = bs3CpuInstr3BufSetup(pbBuf, &cbBuf, bMode); 14831 bs3CpuInstr3GatherBufSetup(g_pbBufAlias); 14832 Bs3RegCtxSaveForMode(&Ctx, bMode, 1024); 14833 bs3CpuInstr3SetupSseAndAvx(&Ctx, pExtCtx); 14834 //Bs3TestPrintf("FTW=%#x mm1/st1=%.16Rhxs\n", pExtCtx->Ctx.x87.FTW, &pExtCtx->Ctx.x87.aRegs[1]); 14835 14836 /* 14837 * Run the tests in all rings since alignment issues may behave 14838 * differently in ring-3 compared to ring-0. 14839 */ 14840 for (;;) 14841 { 14842 unsigned fPf = 0; 14843 do 14844 { 14845 unsigned iCfg; 14846 for (iCfg = 0; iCfg < cConfigs; iCfg++) 14847 { 14848 unsigned iTest; 14849 BS3CPUINSTR3_CONFIG_SAVED_T SavedCfg; 14850 if (!bs3CpuInstr3ConfigReconfigure(&SavedCfg, &Ctx, pExtCtx, &paConfigs[iCfg], bMode)) 14851 continue; /* unsupported config */ 14852 14853 /* 14854 * Iterate the tests. 14855 */ 14856 for (iTest = 0; iTest < cTests; iTest++) 14857 { 14858 BS3CPUINSTR3_TEST7_VALUES_T const BS3_FAR *paValues = paTests[iTest].paValues; 14859 uint8_t const cbInstr = ((uint8_t const BS3_FAR *)(uintptr_t)paTests[iTest].pfnWorker)[-1]; 14860 unsigned const cValues = paTests[iTest].cValues; 14861 uint8_t const cbOperand = paTests[iTest].enmType < T_256BITS ? 128/8 : 256/8; 14862 PRTUINT256U puMemOp = fPf ? (PRTUINT256U)&pbBuf[X86_PAGE_SIZE * 2 + 256] : (PRTUINT256U)&pbBuf[X86_PAGE_SIZE]; 14863 uint16_t idTestStep = bRing * 10000 + iCfg * 100 + iTest * 10; 14864 unsigned cRecompRuns = 0; 14865 unsigned const cMaxRecompRuns = g_cBs3ThresholdNativeRecompiler + cValues; 14866 unsigned iVal; 14867 14868 Bs3RegCtxSetRipCsFromCurPtr(&Ctx, paTests[iTest].pfnWorker); 14869 14870 /* 14871 * Iterate the test values and do the actual testing. 14872 */ 14873 while (cRecompRuns < cMaxRecompRuns) 14874 for (iVal = 0; iVal < cValues; iVal++, idTestStep++, cRecompRuns++) 14875 { 14876 uint16_t cErrors; 14877 uint16_t uSavedFtw = 0xff; 14878 uint8_t bXcptExpect = !g_afTypeSupports[paTests[iTest].enmType] ? X86_XCPT_UD 14879 : BS3_MODE_IS_RM_OR_V86(bMode) ? X86_XCPT_UD : paConfigs[iCfg].bXcptAvx; 14880 14881 if (BS3_SKIPIT(bRing, iCfg, iTest, iVal, 0)) continue; 14882 14883 /* These instructions do not raise #AC */ 14884 if (bXcptExpect == X86_XCPT_AC) 14885 bXcptExpect = paTests[iTest].bXcpt; 14886 14887 if (paTests[iTest].bXcpt && bXcptExpect == X86_XCPT_DB) 14888 bXcptExpect = paTests[iTest].bXcpt; 14889 14890 if (fPf && bXcptExpect == X86_XCPT_DB && !(paValues[iVal].fFlags & BS3_TEST_F_NO_PF)) 14891 bXcptExpect = X86_XCPT_PF; 14892 14893 /* 14894 * Set up the context and some expectations. 14895 */ 14896 /* initial value of destination register */ 14897 Bs3ExtCtxSetYmm(pExtCtx, paTests[iTest].iMmDst, &paValues[iVal].uDstInit, 32); 14898 14899 /* offsets register */ 14900 Bs3ExtCtxSetYmm(pExtCtx, paTests[iTest].iMmOff, &paValues[iVal].uOffsets, 32); 14901 14902 /* initial value of mask register */ 14903 Bs3ExtCtxSetYmm(pExtCtx, paTests[iTest].iMmMsk, &paValues[iVal].uMask, 32); 14904 14905 /* Memory pointer. */ 14906 puMemOp = fPf ? (PRTUINT256U)&pbBuf[X86_PAGE_SIZE * 2 + 256] : (PRTUINT256U)&pbBuf[X86_PAGE_SIZE]; 14907 puMemOp = (PRTUINT256U)(((uint8_t BS3_FAR *)puMemOp) - paTests[iTest].cMemOpOffset); 14908 BS3_ASSERT(paTests[iTest].iGpMem == X86_GREG_xBX || paTests[iTest].iGpMem == X86_GREG_x8); 14909 if (paTests[iTest].iGpMem == X86_GREG_xBX) 14910 Bs3RegCtxSetGrpSegFromCurPtr(&Ctx, &Ctx.rbx, &Ctx.fs, puMemOp); 14911 else if (paTests[iTest].iGpMem == X86_GREG_x8) 14912 Bs3RegCtxSetGrpSegFromCurPtr(&Ctx, &Ctx.r8, &Ctx.fs, puMemOp); 14913 14914 /* 14915 * Execute. 14916 */ 14917 g_uBs3TrapEipHint = Ctx.rip.u32 + (bXcptExpect == X86_XCPT_DB ? cbInstr + 1 : 0); 14918 Bs3TrapSetJmpAndRestoreWithExtCtxAndRm(&Ctx, pExtCtx, &TrapFrame, pExtCtxOut); 14919 14920 /* CPUs are inconsistent about FTW modification during these exceptions */ 14921 if (bXcptExpect == X86_XCPT_PF || bXcptExpect == X86_XCPT_AC) 14922 Bs3ExtCtxSetAbridgedFtw(pExtCtx, Bs3ExtCtxGetAbridgedFtw(pExtCtxOut)); 14923 14924 /* 14925 * Check the result: 14926 */ 14927 cErrors = Bs3TestSubErrorCount(); 14928 14929 if (bXcptExpect == X86_XCPT_DB) 14930 { 14931 RTUINT256U zip = RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000); 14932 Bs3ExtCtxSetYmm(pExtCtx, paTests[iTest].iMmDst, &paValues[iVal].uDstOut, cbOperand); 14933 Bs3ExtCtxSetYmm(pExtCtx, paTests[iTest].iMmMsk, &zip, cbOperand); 14934 } 14935 14936 if (bXcptExpect == X86_XCPT_PF) 14937 Bs3ExtCtxSetYmm(pExtCtx, paTests[iTest].iMmMsk, &paValues[iVal].uMaskPf, cbOperand); 14938 14939 #if defined(DEBUG_aeichner) /** @todo Necessary kludge on a i7-1068NG7. */ 14940 if ( pExtCtx->enmMethod == BS3EXTCTXMETHOD_XSAVE 14941 && pExtCtx->Ctx.x.Hdr.bmXState == 0x7 14942 && pExtCtxOut->Ctx.x.Hdr.bmXState == 0x3) 14943 pExtCtxOut->Ctx.x.Hdr.bmXState = 0x7; 14944 #endif 14945 Bs3TestCheckExtCtx(pExtCtxOut, pExtCtx, 0 /*fFlags*/, pszMode, idTestStep); 14946 14947 if (TrapFrame.bXcpt != bXcptExpect) 14948 Bs3TestFailedF("Expected bXcpt = %#x, got %#x", bXcptExpect, TrapFrame.bXcpt); 14949 14950 /* Kludge! Looks like EFLAGS.AC is cleared when raising #GP in real mode on the 10980XE. WEIRD! */ 14951 if (bMode == BS3_MODE_RM && (Ctx.rflags.u32 & X86_EFL_AC)) 14952 { 14953 if (TrapFrame.Ctx.rflags.u32 & X86_EFL_AC) 14954 Bs3TestFailedF("Expected EFLAGS.AC to be cleared (bXcpt=%d)", TrapFrame.bXcpt); 14955 TrapFrame.Ctx.rflags.u32 |= X86_EFL_AC; 14956 } 14957 14958 /* 14959 * These instructions can access far wider memory. The cr2Range value reflects 14960 * that the *test scenarios* reside within a +/- 1 page range of puMemOp. 14961 */ 14962 if (bXcptExpect == X86_XCPT_PF) 14963 { 14964 Ctx.cr2.u = ((uintptr_t)puMemOp) - X86_PAGE_SIZE; 14965 Ctx.cr2Range = X86_PAGE_SIZE * 2; 14966 } 14967 14968 Bs3TestCheckRegCtxEx(&TrapFrame.Ctx, &Ctx, bXcptExpect == X86_XCPT_DB ? cbInstr + 1 : 0, 0, 14969 bXcptExpect == X86_XCPT_DB || BS3_MODE_IS_16BIT_SYS(bMode) ? 0 : X86_EFL_RF, 14970 pszMode, idTestStep); 14971 14972 if (bXcptExpect == X86_XCPT_PF) 14973 { 14974 Ctx.cr2.u = 0; 14975 Ctx.cr2Range = 0; 14976 } 14977 14978 if (cErrors != Bs3TestSubErrorCount()) 14979 { 14980 Bs3TestFailedF("ring-%d/cfg#%u/test#%u/value#%u failed (bXcptExpect=%#x)\n", 14981 bRing, iCfg, iTest, iVal, bXcptExpect); 14982 } 14983 14984 if (uSavedFtw != 0xff) 14985 Bs3ExtCtxSetAbridgedFtw(pExtCtx, uSavedFtw); 14986 } 14987 } 14988 14989 bs3CpuInstr3ConfigRestore(&SavedCfg, &Ctx, pExtCtx); 14990 } 14991 } while (fPf++ == 0 && BS3_MODE_IS_PAGED(bMode)); 14992 14993 /* 14994 * Next ring. 14995 */ 14996 bRing++; 14997 if (bRing > 3 || bMode == BS3_MODE_RM) 14998 break; 14999 Bs3RegCtxConvertToRingX(&Ctx, bRing); 15000 } 15001 15002 /* 15003 * Cleanup. 15004 */ 15005 bs3CpuInstr3BufCleanup(pbBuf, cbBuf, bMode); 15006 bs3CpuInstr3FreeExtCtxs(pExtCtx, pExtCtxOut); 15007 return 0; 15008 } 15009 15010 15011 /* 15012 * VGATHERDPS - Gather Packed Single Precision FP Values Using Signed Dword Indices 15013 * VPGATHERDD - Gather Packed Dword Values Using Signed Dword Indices 15014 */ 15015 BS3_DECL_FAR(uint8_t) bs3CpuInstr3_vgatherdps_vpgatherdd(uint8_t bMode) 15016 { 15017 static BS3CPUINSTR3_TEST7_VALUES_T const s_aValuesUD[] = 15018 { // Values don't matter, instruction is supposed to #UD! 15019 { 15020 /*mask*/ RTUINT256_INIT_C(0, 0, 0, 0), 15021 /*pmsk*/ RTUINT256_INIT_C(0, 0, 0, 0), 15022 /*offs*/ RTUINT256_INIT_C(0, 0, 0, 0), 15023 /*init*/ RTUINT256_INIT_C(0, 0, 0, 0), 15024 /* => */ RTUINT256_INIT_C(0, 0, 0, 0), 15025 /*flgs*/ 0 }, 15026 }; 15027 static BS3CPUINSTR3_TEST7_VALUES_T const s_aValues32_32x1[] = 15028 { // 32-bit data slices and 32-bit indices times 1 15029 { 15030 /*mask*/ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000), 15031 /*pmsk*/ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000), 15032 /*offs*/ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000), 15033 /*init*/ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000), 15034 /* => */ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000), 15035 /*flgs*/ BS3_TEST_F_NO_PF }, 15036 { 15037 /*mask*/ RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff), 15038 /*pmsk*/ RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff), 15039 /*offs*/ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000), 15040 /*init*/ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000), 15041 /* => */ RTUINT256_INIT_C(0x0002000000020000, 0x0002000000020000, 0x0002000000020000, 0x0002000000020000), 15042 /*flgs*/ 0 }, 15043 { 15044 /*mask*/ RTUINT256_INIT_C(0xffffffff00000000, 0x11111111eeeeeeee, 0xdddddddd22222222, 0x33333333cccccccc), 15045 /*pmsk*/ RTUINT256_INIT_C(0xffffffff00000000, 0x00000000ffffffff, 0xffffffff00000000, 0x00000000ffffffff), 15046 /*offs*/ RTUINT256_INIT_C(0x00000001ffffff99, 0x0000003300000044, 0xfffffefb00000076, 0x0000007c0000007b), 15047 /*init*/ RTUINT256_INIT_C(0x7878787878787878, 0x7878787878787878, 0x7878787878787878, 0x7878787878787878), 15048 /* => */ RTUINT256_INIT_C(0x0400020078787878, 0x7878787800460044, 0xfefefcfe78787878, 0x787878787e007c00), 15049 /*flgs*/ 0 }, 15050 }; 15051 static BS3CPUINSTR3_TEST7_VALUES_T const s_aValues32_32x2[] = 15052 { // 32-bit data slices and 32-bit indices times 2 15053 { 15054 /*mask*/ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000), 15055 /*pmsk*/ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000), 15056 /*offs*/ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000), 15057 /*init*/ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000), 15058 /* => */ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000), 15059 /*flgs*/ BS3_TEST_F_NO_PF }, 15060 { 15061 /*mask*/ RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff), 15062 /*pmsk*/ RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff), 15063 /*offs*/ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000), 15064 /*init*/ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000), 15065 /* => */ RTUINT256_INIT_C(0x0002000000020000, 0x0002000000020000, 0x0002000000020000, 0x0002000000020000), 15066 /*flgs*/ 0 }, 15067 { 15068 /*mask*/ RTUINT256_INIT_C(0xffffffff00000000, 0x11111111eeeeeeee, 0xdddddddd22222222, 0x33333333cccccccc), 15069 /*pmsk*/ RTUINT256_INIT_C(0xffffffff00000000, 0x00000000ffffffff, 0xffffffff00000000, 0x00000000ffffffff), 15070 /*offs*/ RTUINT256_INIT_C(0x00000001ffffff99, 0x0000003300000044, 0xfffffefb00000076, 0x0000007c0000007b), 15071 /*init*/ RTUINT256_INIT_C(0x7878787878787878, 0x7878787878787878, 0x7878787878787878, 0x7878787878787878), 15072 /* => */ RTUINT256_INIT_C(0x0004000278787878, 0x78787878008a0088, 0xfdf8fdf678787878, 0x7878787800f800f6), 15073 /*flgs*/ 0 }, 15074 }; 15075 15076 static BS3CPUINSTR3_TEST7_T const s_aTests16[] = 15077 { // inst_worker_func, bXcpt, offset, inst_type, init/dest mm, mem_ptr gp, offs mm, mask/pmsk mm, 15078 { bs3CpuInstr3_vgatherdps_xmm0_ebx_plus_0_plus_xmm0_x_1_xmm2_icebp_c16, X86_XCPT_UD, 0, T_AVX2_128, 0, 3, 0, 2, RT_ELEMENTS(s_aValuesUD), s_aValuesUD }, 15079 { bs3CpuInstr3_vgatherdps_xmm0_ebx_plus_0_plus_xmm1_x_1_xmm0_icebp_c16, X86_XCPT_UD, 0, T_AVX2_128, 0, 3, 1, 0, RT_ELEMENTS(s_aValuesUD), s_aValuesUD }, 15080 { bs3CpuInstr3_vgatherdps_xmm0_ebx_plus_0_plus_xmm1_x_1_xmm1_icebp_c16, X86_XCPT_UD, 0, T_AVX2_128, 0, 3, 1, 1, RT_ELEMENTS(s_aValuesUD), s_aValuesUD }, 15081 { bs3CpuInstr3_vgatherdps_xmm0_ebx_plus_0_plus_xmm1_x_1_xmm2_icebp_c16, X86_XCPT_DB, 0, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_32x1), s_aValues32_32x1 }, 15082 { bs3CpuInstr3_vgatherdps_xmm0_ebx_plus_0_plus_xmm1_x_2_xmm2_icebp_c16, X86_XCPT_DB, 0, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_32x2), s_aValues32_32x2 }, 15083 { bs3CpuInstr3_vgatherdps_xmm0_ebx_plus_2_plus_xmm1_x_1_xmm2_icebp_c16, X86_XCPT_DB, 2, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_32x1), s_aValues32_32x1 }, 15084 { bs3CpuInstr3_vgatherdps_xmm0_ebx_less_2_plus_xmm1_x_1_xmm2_icebp_c16, X86_XCPT_DB, -2, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_32x1), s_aValues32_32x1 }, 15085 { bs3CpuInstr3_vgatherdps_xmm0_ebx_plus_153_plus_xmm1_x_1_xmm2_icebp_c16, X86_XCPT_DB, 153, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_32x1), s_aValues32_32x1 }, 15086 { bs3CpuInstr3_vgatherdps_xmm0_ebx_less_153_plus_xmm1_x_1_xmm2_icebp_c16, X86_XCPT_DB, -153, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_32x1), s_aValues32_32x1 }, 15087 { bs3CpuInstr3_vgatherdps_ymm0_ebx_plus_0_plus_ymm0_x_1_ymm2_icebp_c16, X86_XCPT_UD, 0, T_AVX2_256, 0, 3, 0, 2, RT_ELEMENTS(s_aValuesUD), s_aValuesUD }, 15088 { bs3CpuInstr3_vgatherdps_ymm0_ebx_plus_0_plus_ymm1_x_1_ymm0_icebp_c16, X86_XCPT_UD, 0, T_AVX2_256, 0, 3, 1, 0, RT_ELEMENTS(s_aValuesUD), s_aValuesUD }, 15089 { bs3CpuInstr3_vgatherdps_ymm0_ebx_plus_0_plus_ymm1_x_1_ymm1_icebp_c16, X86_XCPT_UD, 0, T_AVX2_256, 0, 3, 1, 1, RT_ELEMENTS(s_aValuesUD), s_aValuesUD }, 15090 { bs3CpuInstr3_vgatherdps_ymm0_ebx_plus_0_plus_ymm1_x_1_ymm2_icebp_c16, X86_XCPT_DB, 0, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_32x1), s_aValues32_32x1 }, 15091 { bs3CpuInstr3_vgatherdps_ymm0_ebx_plus_0_plus_ymm1_x_2_ymm2_icebp_c16, X86_XCPT_DB, 0, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_32x2), s_aValues32_32x2 }, 15092 { bs3CpuInstr3_vgatherdps_ymm0_ebx_plus_2_plus_ymm1_x_1_ymm2_icebp_c16, X86_XCPT_DB, 2, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_32x1), s_aValues32_32x1 }, 15093 { bs3CpuInstr3_vgatherdps_ymm0_ebx_less_2_plus_ymm1_x_1_ymm2_icebp_c16, X86_XCPT_DB, -2, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_32x1), s_aValues32_32x1 }, 15094 { bs3CpuInstr3_vgatherdps_ymm0_ebx_plus_153_plus_ymm1_x_1_ymm2_icebp_c16, X86_XCPT_DB, 153, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_32x1), s_aValues32_32x1 }, 15095 { bs3CpuInstr3_vgatherdps_ymm0_ebx_less_153_plus_ymm1_x_1_ymm2_icebp_c16, X86_XCPT_DB, -153, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_32x1), s_aValues32_32x1 }, 15096 15097 { bs3CpuInstr3_vpgatherdd_xmm0_ebx_plus_0_plus_xmm0_x_1_xmm2_icebp_c16, X86_XCPT_UD, 0, T_AVX2_128, 0, 3, 0, 2, RT_ELEMENTS(s_aValuesUD), s_aValuesUD }, 15098 { bs3CpuInstr3_vpgatherdd_xmm0_ebx_plus_0_plus_xmm1_x_1_xmm0_icebp_c16, X86_XCPT_UD, 0, T_AVX2_128, 0, 3, 1, 0, RT_ELEMENTS(s_aValuesUD), s_aValuesUD }, 15099 { bs3CpuInstr3_vpgatherdd_xmm0_ebx_plus_0_plus_xmm1_x_1_xmm1_icebp_c16, X86_XCPT_UD, 0, T_AVX2_128, 0, 3, 1, 1, RT_ELEMENTS(s_aValuesUD), s_aValuesUD }, 15100 { bs3CpuInstr3_vpgatherdd_xmm0_ebx_plus_0_plus_xmm1_x_1_xmm2_icebp_c16, X86_XCPT_DB, 0, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_32x1), s_aValues32_32x1 }, 15101 { bs3CpuInstr3_vpgatherdd_xmm0_ebx_plus_0_plus_xmm1_x_2_xmm2_icebp_c16, X86_XCPT_DB, 0, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_32x2), s_aValues32_32x2 }, 15102 { bs3CpuInstr3_vpgatherdd_xmm0_ebx_plus_2_plus_xmm1_x_1_xmm2_icebp_c16, X86_XCPT_DB, 2, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_32x1), s_aValues32_32x1 }, 15103 { bs3CpuInstr3_vpgatherdd_xmm0_ebx_less_2_plus_xmm1_x_1_xmm2_icebp_c16, X86_XCPT_DB, -2, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_32x1), s_aValues32_32x1 }, 15104 { bs3CpuInstr3_vpgatherdd_xmm0_ebx_plus_153_plus_xmm1_x_1_xmm2_icebp_c16, X86_XCPT_DB, 153, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_32x1), s_aValues32_32x1 }, 15105 { bs3CpuInstr3_vpgatherdd_xmm0_ebx_less_153_plus_xmm1_x_1_xmm2_icebp_c16, X86_XCPT_DB, -153, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_32x1), s_aValues32_32x1 }, 15106 { bs3CpuInstr3_vpgatherdd_ymm0_ebx_plus_0_plus_ymm0_x_1_ymm2_icebp_c16, X86_XCPT_UD, 0, T_AVX2_256, 0, 3, 0, 2, RT_ELEMENTS(s_aValuesUD), s_aValuesUD }, 15107 { bs3CpuInstr3_vpgatherdd_ymm0_ebx_plus_0_plus_ymm1_x_1_ymm0_icebp_c16, X86_XCPT_UD, 0, T_AVX2_256, 0, 3, 1, 0, RT_ELEMENTS(s_aValuesUD), s_aValuesUD }, 15108 { bs3CpuInstr3_vpgatherdd_ymm0_ebx_plus_0_plus_ymm1_x_1_ymm1_icebp_c16, X86_XCPT_UD, 0, T_AVX2_256, 0, 3, 1, 1, RT_ELEMENTS(s_aValuesUD), s_aValuesUD }, 15109 { bs3CpuInstr3_vpgatherdd_ymm0_ebx_plus_0_plus_ymm1_x_1_ymm2_icebp_c16, X86_XCPT_DB, 0, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_32x1), s_aValues32_32x1 }, 15110 { bs3CpuInstr3_vpgatherdd_ymm0_ebx_plus_0_plus_ymm1_x_2_ymm2_icebp_c16, X86_XCPT_DB, 0, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_32x2), s_aValues32_32x2 }, 15111 { bs3CpuInstr3_vpgatherdd_ymm0_ebx_plus_2_plus_ymm1_x_1_ymm2_icebp_c16, X86_XCPT_DB, 2, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_32x1), s_aValues32_32x1 }, 15112 { bs3CpuInstr3_vpgatherdd_ymm0_ebx_less_2_plus_ymm1_x_1_ymm2_icebp_c16, X86_XCPT_DB, -2, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_32x1), s_aValues32_32x1 }, 15113 { bs3CpuInstr3_vpgatherdd_ymm0_ebx_plus_153_plus_ymm1_x_1_ymm2_icebp_c16, X86_XCPT_DB, 153, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_32x1), s_aValues32_32x1 }, 15114 { bs3CpuInstr3_vpgatherdd_ymm0_ebx_less_153_plus_ymm1_x_1_ymm2_icebp_c16, X86_XCPT_DB, -153, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_32x1), s_aValues32_32x1 }, 15115 }; 15116 static BS3CPUINSTR3_TEST7_T const s_aTests32[] = 15117 { 15118 { bs3CpuInstr3_vgatherdps_xmm0_ebx_plus_0_plus_xmm0_x_1_xmm2_icebp_c32, X86_XCPT_UD, 0, T_AVX2_128, 0, 3, 0, 2, RT_ELEMENTS(s_aValuesUD), s_aValuesUD }, 15119 { bs3CpuInstr3_vgatherdps_xmm0_ebx_plus_0_plus_xmm1_x_1_xmm0_icebp_c32, X86_XCPT_UD, 0, T_AVX2_128, 0, 3, 1, 0, RT_ELEMENTS(s_aValuesUD), s_aValuesUD }, 15120 { bs3CpuInstr3_vgatherdps_xmm0_ebx_plus_0_plus_xmm1_x_1_xmm1_icebp_c32, X86_XCPT_UD, 0, T_AVX2_128, 0, 3, 1, 1, RT_ELEMENTS(s_aValuesUD), s_aValuesUD }, 15121 { bs3CpuInstr3_vgatherdps_xmm0_ebx_plus_0_plus_xmm1_x_1_xmm2_icebp_c32, X86_XCPT_DB, 0, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_32x1), s_aValues32_32x1 }, 15122 { bs3CpuInstr3_vgatherdps_xmm0_ebx_plus_0_plus_xmm1_x_2_xmm2_icebp_c32, X86_XCPT_DB, 0, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_32x2), s_aValues32_32x2 }, 15123 { bs3CpuInstr3_vgatherdps_xmm0_ebx_plus_2_plus_xmm1_x_1_xmm2_icebp_c32, X86_XCPT_DB, 2, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_32x1), s_aValues32_32x1 }, 15124 { bs3CpuInstr3_vgatherdps_xmm0_ebx_less_2_plus_xmm1_x_1_xmm2_icebp_c32, X86_XCPT_DB, -2, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_32x1), s_aValues32_32x1 }, 15125 { bs3CpuInstr3_vgatherdps_xmm0_ebx_plus_153_plus_xmm1_x_1_xmm2_icebp_c32, X86_XCPT_DB, 153, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_32x1), s_aValues32_32x1 }, 15126 { bs3CpuInstr3_vgatherdps_xmm0_ebx_less_153_plus_xmm1_x_1_xmm2_icebp_c32, X86_XCPT_DB, -153, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_32x1), s_aValues32_32x1 }, 15127 { bs3CpuInstr3_vgatherdps_ymm0_ebx_plus_0_plus_ymm0_x_1_ymm2_icebp_c32, X86_XCPT_UD, 0, T_AVX2_256, 0, 3, 0, 2, RT_ELEMENTS(s_aValuesUD), s_aValuesUD }, 15128 { bs3CpuInstr3_vgatherdps_ymm0_ebx_plus_0_plus_ymm1_x_1_ymm0_icebp_c32, X86_XCPT_UD, 0, T_AVX2_256, 0, 3, 1, 0, RT_ELEMENTS(s_aValuesUD), s_aValuesUD }, 15129 { bs3CpuInstr3_vgatherdps_ymm0_ebx_plus_0_plus_ymm1_x_1_ymm1_icebp_c32, X86_XCPT_UD, 0, T_AVX2_256, 0, 3, 1, 1, RT_ELEMENTS(s_aValuesUD), s_aValuesUD }, 15130 { bs3CpuInstr3_vgatherdps_ymm0_ebx_plus_0_plus_ymm1_x_1_ymm2_icebp_c32, X86_XCPT_DB, 0, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_32x1), s_aValues32_32x1 }, 15131 { bs3CpuInstr3_vgatherdps_ymm0_ebx_plus_0_plus_ymm1_x_2_ymm2_icebp_c32, X86_XCPT_DB, 0, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_32x2), s_aValues32_32x2 }, 15132 { bs3CpuInstr3_vgatherdps_ymm0_ebx_plus_2_plus_ymm1_x_1_ymm2_icebp_c32, X86_XCPT_DB, 2, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_32x1), s_aValues32_32x1 }, 15133 { bs3CpuInstr3_vgatherdps_ymm0_ebx_less_2_plus_ymm1_x_1_ymm2_icebp_c32, X86_XCPT_DB, -2, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_32x1), s_aValues32_32x1 }, 15134 { bs3CpuInstr3_vgatherdps_ymm0_ebx_plus_153_plus_ymm1_x_1_ymm2_icebp_c32, X86_XCPT_DB, 153, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_32x1), s_aValues32_32x1 }, 15135 { bs3CpuInstr3_vgatherdps_ymm0_ebx_less_153_plus_ymm1_x_1_ymm2_icebp_c32, X86_XCPT_DB, -153, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_32x1), s_aValues32_32x1 }, 15136 15137 { bs3CpuInstr3_vpgatherdd_xmm0_ebx_plus_0_plus_xmm0_x_1_xmm2_icebp_c32, X86_XCPT_UD, 0, T_AVX2_128, 0, 3, 0, 2, RT_ELEMENTS(s_aValuesUD), s_aValuesUD }, 15138 { bs3CpuInstr3_vpgatherdd_xmm0_ebx_plus_0_plus_xmm1_x_1_xmm0_icebp_c32, X86_XCPT_UD, 0, T_AVX2_128, 0, 3, 1, 0, RT_ELEMENTS(s_aValuesUD), s_aValuesUD }, 15139 { bs3CpuInstr3_vpgatherdd_xmm0_ebx_plus_0_plus_xmm1_x_1_xmm1_icebp_c32, X86_XCPT_UD, 0, T_AVX2_128, 0, 3, 1, 1, RT_ELEMENTS(s_aValuesUD), s_aValuesUD }, 15140 { bs3CpuInstr3_vpgatherdd_xmm0_ebx_plus_0_plus_xmm1_x_1_xmm2_icebp_c32, X86_XCPT_DB, 0, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_32x1), s_aValues32_32x1 }, 15141 { bs3CpuInstr3_vpgatherdd_xmm0_ebx_plus_0_plus_xmm1_x_2_xmm2_icebp_c32, X86_XCPT_DB, 0, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_32x2), s_aValues32_32x2 }, 15142 { bs3CpuInstr3_vpgatherdd_xmm0_ebx_plus_2_plus_xmm1_x_1_xmm2_icebp_c32, X86_XCPT_DB, 2, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_32x1), s_aValues32_32x1 }, 15143 { bs3CpuInstr3_vpgatherdd_xmm0_ebx_less_2_plus_xmm1_x_1_xmm2_icebp_c32, X86_XCPT_DB, -2, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_32x1), s_aValues32_32x1 }, 15144 { bs3CpuInstr3_vpgatherdd_xmm0_ebx_plus_153_plus_xmm1_x_1_xmm2_icebp_c32, X86_XCPT_DB, 153, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_32x1), s_aValues32_32x1 }, 15145 { bs3CpuInstr3_vpgatherdd_xmm0_ebx_less_153_plus_xmm1_x_1_xmm2_icebp_c32, X86_XCPT_DB, -153, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_32x1), s_aValues32_32x1 }, 15146 { bs3CpuInstr3_vpgatherdd_ymm0_ebx_plus_0_plus_ymm0_x_1_ymm2_icebp_c32, X86_XCPT_UD, 0, T_AVX2_256, 0, 3, 0, 2, RT_ELEMENTS(s_aValuesUD), s_aValuesUD }, 15147 { bs3CpuInstr3_vpgatherdd_ymm0_ebx_plus_0_plus_ymm1_x_1_ymm0_icebp_c32, X86_XCPT_UD, 0, T_AVX2_256, 0, 3, 1, 0, RT_ELEMENTS(s_aValuesUD), s_aValuesUD }, 15148 { bs3CpuInstr3_vpgatherdd_ymm0_ebx_plus_0_plus_ymm1_x_1_ymm1_icebp_c32, X86_XCPT_UD, 0, T_AVX2_256, 0, 3, 1, 1, RT_ELEMENTS(s_aValuesUD), s_aValuesUD }, 15149 { bs3CpuInstr3_vpgatherdd_ymm0_ebx_plus_0_plus_ymm1_x_1_ymm2_icebp_c32, X86_XCPT_DB, 0, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_32x1), s_aValues32_32x1 }, 15150 { bs3CpuInstr3_vpgatherdd_ymm0_ebx_plus_0_plus_ymm1_x_2_ymm2_icebp_c32, X86_XCPT_DB, 0, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_32x2), s_aValues32_32x2 }, 15151 { bs3CpuInstr3_vpgatherdd_ymm0_ebx_plus_2_plus_ymm1_x_1_ymm2_icebp_c32, X86_XCPT_DB, 2, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_32x1), s_aValues32_32x1 }, 15152 { bs3CpuInstr3_vpgatherdd_ymm0_ebx_less_2_plus_ymm1_x_1_ymm2_icebp_c32, X86_XCPT_DB, -2, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_32x1), s_aValues32_32x1 }, 15153 { bs3CpuInstr3_vpgatherdd_ymm0_ebx_plus_153_plus_ymm1_x_1_ymm2_icebp_c32, X86_XCPT_DB, 153, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_32x1), s_aValues32_32x1 }, 15154 { bs3CpuInstr3_vpgatherdd_ymm0_ebx_less_153_plus_ymm1_x_1_ymm2_icebp_c32, X86_XCPT_DB, -153, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_32x1), s_aValues32_32x1 }, 15155 }; 15156 static BS3CPUINSTR3_TEST7_T const s_aTests64[] = 15157 { 15158 { bs3CpuInstr3_vgatherdps_xmm0_ebx_plus_0_plus_xmm0_x_1_xmm2_icebp_c64, X86_XCPT_UD, 0, T_AVX2_128, 0, 3, 0, 2, RT_ELEMENTS(s_aValuesUD), s_aValuesUD }, 15159 { bs3CpuInstr3_vgatherdps_xmm0_ebx_plus_0_plus_xmm1_x_1_xmm0_icebp_c64, X86_XCPT_UD, 0, T_AVX2_128, 0, 3, 1, 0, RT_ELEMENTS(s_aValuesUD), s_aValuesUD }, 15160 { bs3CpuInstr3_vgatherdps_xmm0_ebx_plus_0_plus_xmm1_x_1_xmm1_icebp_c64, X86_XCPT_UD, 0, T_AVX2_128, 0, 3, 1, 1, RT_ELEMENTS(s_aValuesUD), s_aValuesUD }, 15161 { bs3CpuInstr3_vgatherdps_xmm0_ebx_plus_0_plus_xmm1_x_1_xmm2_icebp_c64, X86_XCPT_DB, 0, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_32x1), s_aValues32_32x1 }, 15162 { bs3CpuInstr3_vgatherdps_xmm0_ebx_plus_0_plus_xmm1_x_2_xmm2_icebp_c64, X86_XCPT_DB, 0, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_32x2), s_aValues32_32x2 }, 15163 { bs3CpuInstr3_vgatherdps_xmm0_ebx_plus_2_plus_xmm1_x_1_xmm2_icebp_c64, X86_XCPT_DB, 2, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_32x1), s_aValues32_32x1 }, 15164 { bs3CpuInstr3_vgatherdps_xmm0_ebx_less_2_plus_xmm1_x_1_xmm2_icebp_c64, X86_XCPT_DB, -2, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_32x1), s_aValues32_32x1 }, 15165 { bs3CpuInstr3_vgatherdps_xmm0_ebx_plus_153_plus_xmm1_x_1_xmm2_icebp_c64, X86_XCPT_DB, 153, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_32x1), s_aValues32_32x1 }, 15166 { bs3CpuInstr3_vgatherdps_xmm0_ebx_less_153_plus_xmm1_x_1_xmm2_icebp_c64, X86_XCPT_DB, -153, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_32x1), s_aValues32_32x1 }, 15167 { bs3CpuInstr3_vgatherdps_xmm0_rbx_plus_0_plus_xmm1_x_1_xmm2_icebp_c64, X86_XCPT_DB, 0, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_32x1), s_aValues32_32x1 }, 15168 { bs3CpuInstr3_vgatherdps_xmm8_r8d_plus_0_plus_xmm9_x_1_xmm10_icebp_c64, X86_XCPT_DB, 0, T_AVX2_128, 8, 8, 9, 10, RT_ELEMENTS(s_aValues32_32x1), s_aValues32_32x1 }, 15169 { bs3CpuInstr3_vgatherdps_ymm0_ebx_plus_0_plus_ymm1_x_1_ymm1_icebp_c64, X86_XCPT_UD, 0, T_AVX2_256, 0, 3, 1, 1, RT_ELEMENTS(s_aValuesUD), s_aValuesUD }, 15170 { bs3CpuInstr3_vgatherdps_ymm0_ebx_plus_0_plus_ymm1_x_1_ymm2_icebp_c64, X86_XCPT_DB, 0, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_32x1), s_aValues32_32x1 }, 15171 { bs3CpuInstr3_vgatherdps_ymm0_ebx_plus_0_plus_ymm1_x_2_ymm2_icebp_c64, X86_XCPT_DB, 0, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_32x2), s_aValues32_32x2 }, 15172 { bs3CpuInstr3_vgatherdps_ymm0_ebx_plus_2_plus_ymm1_x_1_ymm2_icebp_c64, X86_XCPT_DB, 2, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_32x1), s_aValues32_32x1 }, 15173 { bs3CpuInstr3_vgatherdps_ymm0_ebx_less_2_plus_ymm1_x_1_ymm2_icebp_c64, X86_XCPT_DB, -2, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_32x1), s_aValues32_32x1 }, 15174 { bs3CpuInstr3_vgatherdps_ymm0_ebx_plus_153_plus_ymm1_x_1_ymm2_icebp_c64, X86_XCPT_DB, 153, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_32x1), s_aValues32_32x1 }, 15175 { bs3CpuInstr3_vgatherdps_ymm0_ebx_less_153_plus_ymm1_x_1_ymm2_icebp_c64, X86_XCPT_DB, -153, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_32x1), s_aValues32_32x1 }, 15176 { bs3CpuInstr3_vgatherdps_ymm0_rbx_plus_0_plus_ymm1_x_1_ymm2_icebp_c64, X86_XCPT_DB, 0, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_32x1), s_aValues32_32x1 }, 15177 { bs3CpuInstr3_vgatherdps_ymm8_r8d_plus_0_plus_ymm9_x_1_ymm10_icebp_c64, X86_XCPT_DB, 0, T_AVX2_256, 8, 8, 9, 10, RT_ELEMENTS(s_aValues32_32x1), s_aValues32_32x1 }, 15178 15179 { bs3CpuInstr3_vpgatherdd_xmm0_ebx_plus_0_plus_xmm0_x_1_xmm2_icebp_c64, X86_XCPT_UD, 0, T_AVX2_128, 0, 3, 0, 2, RT_ELEMENTS(s_aValuesUD), s_aValuesUD }, 15180 { bs3CpuInstr3_vpgatherdd_xmm0_ebx_plus_0_plus_xmm1_x_1_xmm0_icebp_c64, X86_XCPT_UD, 0, T_AVX2_128, 0, 3, 1, 0, RT_ELEMENTS(s_aValuesUD), s_aValuesUD }, 15181 { bs3CpuInstr3_vpgatherdd_xmm0_ebx_plus_0_plus_xmm1_x_1_xmm1_icebp_c64, X86_XCPT_UD, 0, T_AVX2_128, 0, 3, 1, 1, RT_ELEMENTS(s_aValuesUD), s_aValuesUD }, 15182 { bs3CpuInstr3_vpgatherdd_xmm0_ebx_plus_0_plus_xmm1_x_1_xmm2_icebp_c64, X86_XCPT_DB, 0, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_32x1), s_aValues32_32x1 }, 15183 { bs3CpuInstr3_vpgatherdd_xmm0_ebx_plus_0_plus_xmm1_x_2_xmm2_icebp_c64, X86_XCPT_DB, 0, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_32x2), s_aValues32_32x2 }, 15184 { bs3CpuInstr3_vpgatherdd_xmm0_ebx_plus_2_plus_xmm1_x_1_xmm2_icebp_c64, X86_XCPT_DB, 2, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_32x1), s_aValues32_32x1 }, 15185 { bs3CpuInstr3_vpgatherdd_xmm0_ebx_less_2_plus_xmm1_x_1_xmm2_icebp_c64, X86_XCPT_DB, -2, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_32x1), s_aValues32_32x1 }, 15186 { bs3CpuInstr3_vpgatherdd_xmm0_ebx_plus_153_plus_xmm1_x_1_xmm2_icebp_c64, X86_XCPT_DB, 153, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_32x1), s_aValues32_32x1 }, 15187 { bs3CpuInstr3_vpgatherdd_xmm0_ebx_less_153_plus_xmm1_x_1_xmm2_icebp_c64, X86_XCPT_DB, -153, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_32x1), s_aValues32_32x1 }, 15188 { bs3CpuInstr3_vpgatherdd_xmm0_rbx_plus_0_plus_xmm1_x_1_xmm2_icebp_c64, X86_XCPT_DB, 0, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_32x1), s_aValues32_32x1 }, 15189 { bs3CpuInstr3_vpgatherdd_xmm8_r8d_plus_0_plus_xmm9_x_1_xmm10_icebp_c64, X86_XCPT_DB, 0, T_AVX2_128, 8, 8, 9, 10, RT_ELEMENTS(s_aValues32_32x1), s_aValues32_32x1 }, 15190 { bs3CpuInstr3_vpgatherdd_ymm0_ebx_plus_0_plus_ymm0_x_1_ymm2_icebp_c64, X86_XCPT_UD, 0, T_AVX2_256, 0, 3, 0, 2, RT_ELEMENTS(s_aValuesUD), s_aValuesUD }, 15191 { bs3CpuInstr3_vpgatherdd_ymm0_ebx_plus_0_plus_ymm1_x_1_ymm0_icebp_c64, X86_XCPT_UD, 0, T_AVX2_256, 0, 3, 1, 0, RT_ELEMENTS(s_aValuesUD), s_aValuesUD }, 15192 { bs3CpuInstr3_vpgatherdd_ymm0_ebx_plus_0_plus_ymm1_x_1_ymm1_icebp_c64, X86_XCPT_UD, 0, T_AVX2_256, 0, 3, 1, 1, RT_ELEMENTS(s_aValuesUD), s_aValuesUD }, 15193 { bs3CpuInstr3_vpgatherdd_ymm0_ebx_plus_0_plus_ymm1_x_1_ymm2_icebp_c64, X86_XCPT_DB, 0, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_32x1), s_aValues32_32x1 }, 15194 { bs3CpuInstr3_vpgatherdd_ymm0_ebx_plus_0_plus_ymm1_x_2_ymm2_icebp_c64, X86_XCPT_DB, 0, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_32x2), s_aValues32_32x2 }, 15195 { bs3CpuInstr3_vpgatherdd_ymm0_ebx_plus_2_plus_ymm1_x_1_ymm2_icebp_c64, X86_XCPT_DB, 2, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_32x1), s_aValues32_32x1 }, 15196 { bs3CpuInstr3_vpgatherdd_ymm0_ebx_less_2_plus_ymm1_x_1_ymm2_icebp_c64, X86_XCPT_DB, -2, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_32x1), s_aValues32_32x1 }, 15197 { bs3CpuInstr3_vpgatherdd_ymm0_ebx_plus_153_plus_ymm1_x_1_ymm2_icebp_c64, X86_XCPT_DB, 153, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_32x1), s_aValues32_32x1 }, 15198 { bs3CpuInstr3_vpgatherdd_ymm0_ebx_less_153_plus_ymm1_x_1_ymm2_icebp_c64, X86_XCPT_DB, -153, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_32x1), s_aValues32_32x1 }, 15199 { bs3CpuInstr3_vpgatherdd_ymm0_rbx_plus_0_plus_ymm1_x_1_ymm2_icebp_c64, X86_XCPT_DB, 0, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_32x1), s_aValues32_32x1 }, 15200 { bs3CpuInstr3_vpgatherdd_ymm8_r8d_plus_0_plus_ymm9_x_1_ymm10_icebp_c64, X86_XCPT_DB, 0, T_AVX2_256, 8, 8, 9, 10, RT_ELEMENTS(s_aValues32_32x1), s_aValues32_32x1 }, 15201 }; 15202 static BS3CPUINSTR3_TEST7_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST7_MODES_INIT(s_aTests16, s_aTests32, s_aTests64); 15203 unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode); 15204 return bs3CpuInstr3_WorkerTestType7(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests, 15205 g_aXcptConfig5, RT_ELEMENTS(g_aXcptConfig5)); 15206 } 15207 15208 15209 /* 15210 * VGATHERQPS - Gather Packed Single Precision FP Values Using Signed Qword Indices 15211 * VPGATHERQD - Gather Packed Dword Values Using Signed Qword Indices 15212 */ 15213 BS3_DECL_FAR(uint8_t) bs3CpuInstr3_vgatherqps_vpgatherqd(uint8_t bMode) 15214 { 15215 static BS3CPUINSTR3_TEST7_VALUES_T const s_aValuesUD[] = 15216 { // Values don't matter, instruction is supposed to #UD! 15217 { 15218 /*mask*/ RTUINT256_INIT_C(0, 0, 0, 0), 15219 /*pmsk*/ RTUINT256_INIT_C(0, 0, 0, 0), 15220 /*offs*/ RTUINT256_INIT_C(0, 0, 0, 0), 15221 /*init*/ RTUINT256_INIT_C(0, 0, 0, 0), 15222 /* => */ RTUINT256_INIT_C(0, 0, 0, 0), 15223 /*flgs*/ 0 }, 15224 }; 15225 static BS3CPUINSTR3_TEST7_VALUES_T const s_aValues32_64x1X[] = 15226 { // 32-bit data slices and 64-bit indices times 1; only 2 indices (XMM's worth) 15227 { 15228 /*mask*/ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000), 15229 /*pmsk*/ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000), 15230 /*offs*/ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000), 15231 /*init*/ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000), 15232 /* => */ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000), 15233 /*flgs*/ BS3_TEST_F_NO_PF }, 15234 { 15235 /*mask*/ RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff), 15236 /*pmsk*/ RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff), 15237 /*offs*/ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000), 15238 /*init*/ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000), 15239 /* => */ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0002000000020000), 15240 /*flgs*/ 0 }, 15241 { 15242 /*mask*/ RTUINT256_INIT_C(0xffffffff00000000, 0x11111111eeeeeeee, 0xdddddddd22222222, 0x33333333cccccccc), 15243 /*pmsk*/ RTUINT256_INIT_C(0xffffffff00000000, 0x00000000ffffffff, 0xffffffff00000000, 0x00000000ffffffff), 15244 /*offs*/ RTUINT256_INIT_C(0x0000000000000002, 0x0000000000000004, 0xfffffffffffffefb, 0x0000000000000345), 15245 /*init*/ RTUINT256_INIT_C(0x7878787878787878, 0x7878787878787878, 0x7878787878787878, 0x7878787878787878), 15246 /* => */ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x7878787848034603), 15247 /*flgs*/ 0 }, 15248 }; 15249 static BS3CPUINSTR3_TEST7_VALUES_T const s_aValues32_64x1Y[] = 15250 { // 32-bit data slices and 64-bit indices times 1; 4 indices (YMM's worth) 15251 { 15252 /*mask*/ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000), 15253 /*pmsk*/ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000), 15254 /*offs*/ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000), 15255 /*init*/ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000), 15256 /* => */ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000), 15257 /*flgs*/ BS3_TEST_F_NO_PF }, 15258 { 15259 /*mask*/ RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff), 15260 /*pmsk*/ RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff), 15261 /*offs*/ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000), 15262 /*init*/ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000), 15263 /* => */ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0002000000020000, 0x0002000000020000), 15264 /*flgs*/ 0 }, 15265 { 15266 /*mask*/ RTUINT256_INIT_C(0xffffffff00000000, 0x11111111eeeeeeee, 0xdddddddd22222222, 0x33333333cccccccc), 15267 /*pmsk*/ RTUINT256_INIT_C(0xffffffff00000000, 0x00000000ffffffff, 0xffffffff00000000, 0x00000000ffffffff), 15268 /*offs*/ RTUINT256_INIT_C(0x0000000000000002, 0x0000000000000004, 0xfffffffffffffefb, 0x0000000000000345), 15269 /*init*/ RTUINT256_INIT_C(0x7878787878787878, 0x7878787878787878, 0x7878787878787878, 0x7878787878787878), 15270 /* => */ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0004000278787878, 0x7878787848034603), 15271 /*flgs*/ 0 }, 15272 }; 15273 static BS3CPUINSTR3_TEST7_VALUES_T const s_aValues32_64x2X[] = 15274 { // 32-bit data slices and 64-bit indices times 2; only 2 indices (XMM's worth) 15275 { 15276 /*mask*/ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000), 15277 /*pmsk*/ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000), 15278 /*offs*/ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000), 15279 /*init*/ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000), 15280 /* => */ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000), 15281 /*flgs*/ BS3_TEST_F_NO_PF }, 15282 { 15283 /*mask*/ RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff), 15284 /*pmsk*/ RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff), 15285 /*offs*/ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000), 15286 /*init*/ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000), 15287 /* => */ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0002000000020000), 15288 /*flgs*/ 0 }, 15289 { 15290 /*mask*/ RTUINT256_INIT_C(0xffffffff00000000, 0x11111111eeeeeeee, 0xdddddddd22222222, 0x33333333cccccccc), 15291 /*pmsk*/ RTUINT256_INIT_C(0xffffffff00000000, 0x00000000ffffffff, 0xffffffff00000000, 0x00000000ffffffff), 15292 /*offs*/ RTUINT256_INIT_C(0x0000000000000002, 0x0000000000000004, 0xfffffffffffffefb, 0x0000000000000345), 15293 /*init*/ RTUINT256_INIT_C(0x7878787878787878, 0x7878787878787878, 0x7878787878787878, 0x7878787878787878), 15294 /* => */ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x78787878068c068a), 15295 /*flgs*/ 0 }, 15296 }; 15297 static BS3CPUINSTR3_TEST7_VALUES_T const s_aValues32_64x2Y[] = 15298 { // 32-bit data slices and 64-bit indices times 2; 4 indices (YMM's worth) 15299 { 15300 /*mask*/ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000), 15301 /*pmsk*/ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000), 15302 /*offs*/ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000), 15303 /*init*/ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000), 15304 /* => */ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000), 15305 /*flgs*/ BS3_TEST_F_NO_PF }, 15306 { 15307 /*mask*/ RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff), 15308 /*pmsk*/ RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff), 15309 /*offs*/ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000), 15310 /*init*/ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000), 15311 /* => */ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0002000000020000, 0x0002000000020000), 15312 /*flgs*/ 0 }, 15313 { 15314 /*mask*/ RTUINT256_INIT_C(0xffffffff00000000, 0x11111111eeeeeeee, 0xdddddddd22222222, 0x33333333cccccccc), 15315 /*pmsk*/ RTUINT256_INIT_C(0xffffffff00000000, 0x00000000ffffffff, 0xffffffff00000000, 0x00000000ffffffff), 15316 /*offs*/ RTUINT256_INIT_C(0x0000000000000002, 0x0000000000000004, 0xfffffffffffffefb, 0x0000000000000345), 15317 /*init*/ RTUINT256_INIT_C(0x7878787878787878, 0x7878787878787878, 0x7878787878787878, 0x7878787878787878), 15318 /* => */ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0006000478787878, 0x78787878068c068a), 15319 /*flgs*/ 0 }, 15320 }; 15321 15322 static BS3CPUINSTR3_TEST7_T const s_aTests16[] = 15323 { // inst_worker_func, bXcpt, offset, inst_type, init/dest mm, mem_ptr gp, offs mm, mask/pmsk mm, 15324 { bs3CpuInstr3_vgatherqps_xmm0_ebx_plus_0_plus_xmm0_x_1_xmm2_icebp_c16, X86_XCPT_UD, 0, T_AVX2_128, 0, 3, 0, 2, RT_ELEMENTS(s_aValuesUD), s_aValuesUD }, 15325 { bs3CpuInstr3_vgatherqps_xmm0_ebx_plus_0_plus_xmm1_x_1_xmm0_icebp_c16, X86_XCPT_UD, 0, T_AVX2_128, 0, 3, 1, 0, RT_ELEMENTS(s_aValuesUD), s_aValuesUD }, 15326 { bs3CpuInstr3_vgatherqps_xmm0_ebx_plus_0_plus_xmm1_x_1_xmm1_icebp_c16, X86_XCPT_UD, 0, T_AVX2_128, 0, 3, 1, 1, RT_ELEMENTS(s_aValuesUD), s_aValuesUD }, 15327 { bs3CpuInstr3_vgatherqps_xmm0_ebx_plus_0_plus_xmm1_x_1_xmm2_icebp_c16, X86_XCPT_DB, 0, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_64x1X), s_aValues32_64x1X }, 15328 { bs3CpuInstr3_vgatherqps_xmm0_ebx_plus_0_plus_xmm1_x_2_xmm2_icebp_c16, X86_XCPT_DB, 0, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_64x2X), s_aValues32_64x2X }, 15329 { bs3CpuInstr3_vgatherqps_xmm0_ebx_plus_2_plus_xmm1_x_1_xmm2_icebp_c16, X86_XCPT_DB, 2, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_64x1X), s_aValues32_64x1X }, 15330 { bs3CpuInstr3_vgatherqps_xmm0_ebx_less_2_plus_xmm1_x_1_xmm2_icebp_c16, X86_XCPT_DB, -2, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_64x1X), s_aValues32_64x1X }, 15331 { bs3CpuInstr3_vgatherqps_xmm0_ebx_plus_153_plus_xmm1_x_1_xmm2_icebp_c16, X86_XCPT_DB, 153, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_64x1X), s_aValues32_64x1X }, 15332 { bs3CpuInstr3_vgatherqps_xmm0_ebx_less_153_plus_xmm1_x_1_xmm2_icebp_c16, X86_XCPT_DB, -153, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_64x1X), s_aValues32_64x1X }, 15333 { bs3CpuInstr3_vgatherqps_xmm0_ebx_plus_0_plus_ymm0_x_1_xmm2_icebp_c16, X86_XCPT_UD, 0, T_AVX2_256, 0, 3, 0, 2, RT_ELEMENTS(s_aValuesUD), s_aValuesUD }, 15334 { bs3CpuInstr3_vgatherqps_xmm0_ebx_plus_0_plus_ymm1_x_1_xmm0_icebp_c16, X86_XCPT_UD, 0, T_AVX2_256, 0, 3, 1, 0, RT_ELEMENTS(s_aValuesUD), s_aValuesUD }, 15335 { bs3CpuInstr3_vgatherqps_xmm0_ebx_plus_0_plus_ymm1_x_1_xmm1_icebp_c16, X86_XCPT_UD, 0, T_AVX2_256, 0, 3, 1, 1, RT_ELEMENTS(s_aValuesUD), s_aValuesUD }, 15336 { bs3CpuInstr3_vgatherqps_xmm0_ebx_plus_0_plus_ymm1_x_1_xmm2_icebp_c16, X86_XCPT_DB, 0, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_64x1Y), s_aValues32_64x1Y }, 15337 { bs3CpuInstr3_vgatherqps_xmm0_ebx_plus_0_plus_ymm1_x_2_xmm2_icebp_c16, X86_XCPT_DB, 0, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_64x2Y), s_aValues32_64x2Y }, 15338 { bs3CpuInstr3_vgatherqps_xmm0_ebx_plus_2_plus_ymm1_x_1_xmm2_icebp_c16, X86_XCPT_DB, 2, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_64x1Y), s_aValues32_64x1Y }, 15339 { bs3CpuInstr3_vgatherqps_xmm0_ebx_less_2_plus_ymm1_x_1_xmm2_icebp_c16, X86_XCPT_DB, -2, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_64x1Y), s_aValues32_64x1Y }, 15340 { bs3CpuInstr3_vgatherqps_xmm0_ebx_plus_153_plus_ymm1_x_1_xmm2_icebp_c16, X86_XCPT_DB, 153, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_64x1Y), s_aValues32_64x1Y }, 15341 { bs3CpuInstr3_vgatherqps_xmm0_ebx_less_153_plus_ymm1_x_1_xmm2_icebp_c16, X86_XCPT_DB, -153, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_64x1Y), s_aValues32_64x1Y }, 15342 15343 { bs3CpuInstr3_vpgatherqd_xmm0_ebx_plus_0_plus_xmm0_x_1_xmm2_icebp_c16, X86_XCPT_UD, 0, T_AVX2_128, 0, 3, 0, 2, RT_ELEMENTS(s_aValuesUD), s_aValuesUD }, 15344 { bs3CpuInstr3_vpgatherqd_xmm0_ebx_plus_0_plus_xmm1_x_1_xmm0_icebp_c16, X86_XCPT_UD, 0, T_AVX2_128, 0, 3, 1, 0, RT_ELEMENTS(s_aValuesUD), s_aValuesUD }, 15345 { bs3CpuInstr3_vpgatherqd_xmm0_ebx_plus_0_plus_xmm1_x_1_xmm1_icebp_c16, X86_XCPT_UD, 0, T_AVX2_128, 0, 3, 1, 1, RT_ELEMENTS(s_aValuesUD), s_aValuesUD }, 15346 { bs3CpuInstr3_vpgatherqd_xmm0_ebx_plus_0_plus_xmm1_x_1_xmm2_icebp_c16, X86_XCPT_DB, 0, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_64x1X), s_aValues32_64x1X }, 15347 { bs3CpuInstr3_vpgatherqd_xmm0_ebx_plus_0_plus_xmm1_x_2_xmm2_icebp_c16, X86_XCPT_DB, 0, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_64x2X), s_aValues32_64x2X }, 15348 { bs3CpuInstr3_vpgatherqd_xmm0_ebx_plus_2_plus_xmm1_x_1_xmm2_icebp_c16, X86_XCPT_DB, 2, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_64x1X), s_aValues32_64x1X }, 15349 { bs3CpuInstr3_vpgatherqd_xmm0_ebx_less_2_plus_xmm1_x_1_xmm2_icebp_c16, X86_XCPT_DB, -2, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_64x1X), s_aValues32_64x1X }, 15350 { bs3CpuInstr3_vpgatherqd_xmm0_ebx_plus_153_plus_xmm1_x_1_xmm2_icebp_c16, X86_XCPT_DB, 153, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_64x1X), s_aValues32_64x1X }, 15351 { bs3CpuInstr3_vpgatherqd_xmm0_ebx_less_153_plus_xmm1_x_1_xmm2_icebp_c16, X86_XCPT_DB, -153, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_64x1X), s_aValues32_64x1X }, 15352 { bs3CpuInstr3_vpgatherqd_xmm0_ebx_plus_0_plus_ymm0_x_1_xmm2_icebp_c16, X86_XCPT_UD, 0, T_AVX2_256, 0, 3, 0, 2, RT_ELEMENTS(s_aValuesUD), s_aValuesUD }, 15353 { bs3CpuInstr3_vpgatherqd_xmm0_ebx_plus_0_plus_ymm1_x_1_xmm0_icebp_c16, X86_XCPT_UD, 0, T_AVX2_256, 0, 3, 1, 0, RT_ELEMENTS(s_aValuesUD), s_aValuesUD }, 15354 { bs3CpuInstr3_vpgatherqd_xmm0_ebx_plus_0_plus_ymm1_x_1_xmm1_icebp_c16, X86_XCPT_UD, 0, T_AVX2_256, 0, 3, 1, 1, RT_ELEMENTS(s_aValuesUD), s_aValuesUD }, 15355 { bs3CpuInstr3_vpgatherqd_xmm0_ebx_plus_0_plus_ymm1_x_1_xmm2_icebp_c16, X86_XCPT_DB, 0, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_64x1Y), s_aValues32_64x1Y }, 15356 { bs3CpuInstr3_vpgatherqd_xmm0_ebx_plus_0_plus_ymm1_x_2_xmm2_icebp_c16, X86_XCPT_DB, 0, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_64x2Y), s_aValues32_64x2Y }, 15357 { bs3CpuInstr3_vpgatherqd_xmm0_ebx_plus_2_plus_ymm1_x_1_xmm2_icebp_c16, X86_XCPT_DB, 2, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_64x1Y), s_aValues32_64x1Y }, 15358 { bs3CpuInstr3_vpgatherqd_xmm0_ebx_less_2_plus_ymm1_x_1_xmm2_icebp_c16, X86_XCPT_DB, -2, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_64x1Y), s_aValues32_64x1Y }, 15359 { bs3CpuInstr3_vpgatherqd_xmm0_ebx_plus_153_plus_ymm1_x_1_xmm2_icebp_c16, X86_XCPT_DB, 153, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_64x1Y), s_aValues32_64x1Y }, 15360 { bs3CpuInstr3_vpgatherqd_xmm0_ebx_less_153_plus_ymm1_x_1_xmm2_icebp_c16, X86_XCPT_DB, -153, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_64x1Y), s_aValues32_64x1Y }, 15361 }; 15362 static BS3CPUINSTR3_TEST7_T const s_aTests32[] = 15363 { 15364 { bs3CpuInstr3_vgatherqps_xmm0_ebx_plus_0_plus_xmm0_x_1_xmm2_icebp_c32, X86_XCPT_UD, 0, T_AVX2_128, 0, 3, 0, 2, RT_ELEMENTS(s_aValuesUD), s_aValuesUD }, 15365 { bs3CpuInstr3_vgatherqps_xmm0_ebx_plus_0_plus_xmm1_x_1_xmm0_icebp_c32, X86_XCPT_UD, 0, T_AVX2_128, 0, 3, 1, 0, RT_ELEMENTS(s_aValuesUD), s_aValuesUD }, 15366 { bs3CpuInstr3_vgatherqps_xmm0_ebx_plus_0_plus_xmm1_x_1_xmm1_icebp_c32, X86_XCPT_UD, 0, T_AVX2_128, 0, 3, 1, 1, RT_ELEMENTS(s_aValuesUD), s_aValuesUD }, 15367 { bs3CpuInstr3_vgatherqps_xmm0_ebx_plus_0_plus_xmm1_x_1_xmm2_icebp_c32, X86_XCPT_DB, 0, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_64x1X), s_aValues32_64x1X }, 15368 { bs3CpuInstr3_vgatherqps_xmm0_ebx_plus_0_plus_xmm1_x_2_xmm2_icebp_c32, X86_XCPT_DB, 0, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_64x2X), s_aValues32_64x2X }, 15369 { bs3CpuInstr3_vgatherqps_xmm0_ebx_plus_2_plus_xmm1_x_1_xmm2_icebp_c32, X86_XCPT_DB, 2, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_64x1X), s_aValues32_64x1X }, 15370 { bs3CpuInstr3_vgatherqps_xmm0_ebx_less_2_plus_xmm1_x_1_xmm2_icebp_c32, X86_XCPT_DB, -2, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_64x1X), s_aValues32_64x1X }, 15371 { bs3CpuInstr3_vgatherqps_xmm0_ebx_plus_153_plus_xmm1_x_1_xmm2_icebp_c32, X86_XCPT_DB, 153, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_64x1X), s_aValues32_64x1X }, 15372 { bs3CpuInstr3_vgatherqps_xmm0_ebx_less_153_plus_xmm1_x_1_xmm2_icebp_c32, X86_XCPT_DB, -153, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_64x1X), s_aValues32_64x1X }, 15373 { bs3CpuInstr3_vgatherqps_xmm0_ebx_plus_0_plus_ymm0_x_1_xmm2_icebp_c32, X86_XCPT_UD, 0, T_AVX2_256, 0, 3, 0, 2, RT_ELEMENTS(s_aValuesUD), s_aValuesUD }, 15374 { bs3CpuInstr3_vgatherqps_xmm0_ebx_plus_0_plus_ymm1_x_1_xmm0_icebp_c32, X86_XCPT_UD, 0, T_AVX2_256, 0, 3, 1, 0, RT_ELEMENTS(s_aValuesUD), s_aValuesUD }, 15375 { bs3CpuInstr3_vgatherqps_xmm0_ebx_plus_0_plus_ymm1_x_1_xmm1_icebp_c32, X86_XCPT_UD, 0, T_AVX2_256, 0, 3, 1, 1, RT_ELEMENTS(s_aValuesUD), s_aValuesUD }, 15376 { bs3CpuInstr3_vgatherqps_xmm0_ebx_plus_0_plus_ymm1_x_1_xmm2_icebp_c32, X86_XCPT_DB, 0, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_64x1Y), s_aValues32_64x1Y }, 15377 { bs3CpuInstr3_vgatherqps_xmm0_ebx_plus_0_plus_ymm1_x_2_xmm2_icebp_c32, X86_XCPT_DB, 0, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_64x2Y), s_aValues32_64x2Y }, 15378 { bs3CpuInstr3_vgatherqps_xmm0_ebx_plus_2_plus_ymm1_x_1_xmm2_icebp_c32, X86_XCPT_DB, 2, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_64x1Y), s_aValues32_64x1Y }, 15379 { bs3CpuInstr3_vgatherqps_xmm0_ebx_less_2_plus_ymm1_x_1_xmm2_icebp_c32, X86_XCPT_DB, -2, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_64x1Y), s_aValues32_64x1Y }, 15380 { bs3CpuInstr3_vgatherqps_xmm0_ebx_plus_153_plus_ymm1_x_1_xmm2_icebp_c32, X86_XCPT_DB, 153, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_64x1Y), s_aValues32_64x1Y }, 15381 { bs3CpuInstr3_vgatherqps_xmm0_ebx_less_153_plus_ymm1_x_1_xmm2_icebp_c32, X86_XCPT_DB, -153, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_64x1Y), s_aValues32_64x1Y }, 15382 15383 { bs3CpuInstr3_vpgatherqd_xmm0_ebx_plus_0_plus_xmm0_x_1_xmm2_icebp_c32, X86_XCPT_UD, 0, T_AVX2_128, 0, 3, 0, 2, RT_ELEMENTS(s_aValuesUD), s_aValuesUD }, 15384 { bs3CpuInstr3_vpgatherqd_xmm0_ebx_plus_0_plus_xmm1_x_1_xmm0_icebp_c32, X86_XCPT_UD, 0, T_AVX2_128, 0, 3, 1, 0, RT_ELEMENTS(s_aValuesUD), s_aValuesUD }, 15385 { bs3CpuInstr3_vpgatherqd_xmm0_ebx_plus_0_plus_xmm1_x_1_xmm1_icebp_c32, X86_XCPT_UD, 0, T_AVX2_128, 0, 3, 1, 1, RT_ELEMENTS(s_aValuesUD), s_aValuesUD }, 15386 { bs3CpuInstr3_vpgatherqd_xmm0_ebx_plus_0_plus_xmm1_x_1_xmm2_icebp_c32, X86_XCPT_DB, 0, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_64x1X), s_aValues32_64x1X }, 15387 { bs3CpuInstr3_vpgatherqd_xmm0_ebx_plus_0_plus_xmm1_x_2_xmm2_icebp_c32, X86_XCPT_DB, 0, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_64x2X), s_aValues32_64x2X }, 15388 { bs3CpuInstr3_vpgatherqd_xmm0_ebx_plus_2_plus_xmm1_x_1_xmm2_icebp_c32, X86_XCPT_DB, 2, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_64x1X), s_aValues32_64x1X }, 15389 { bs3CpuInstr3_vpgatherqd_xmm0_ebx_less_2_plus_xmm1_x_1_xmm2_icebp_c32, X86_XCPT_DB, -2, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_64x1X), s_aValues32_64x1X }, 15390 { bs3CpuInstr3_vpgatherqd_xmm0_ebx_plus_153_plus_xmm1_x_1_xmm2_icebp_c32, X86_XCPT_DB, 153, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_64x1X), s_aValues32_64x1X }, 15391 { bs3CpuInstr3_vpgatherqd_xmm0_ebx_less_153_plus_xmm1_x_1_xmm2_icebp_c32, X86_XCPT_DB, -153, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_64x1X), s_aValues32_64x1X }, 15392 { bs3CpuInstr3_vpgatherqd_xmm0_ebx_plus_0_plus_ymm0_x_1_xmm2_icebp_c32, X86_XCPT_UD, 0, T_AVX2_256, 0, 3, 0, 2, RT_ELEMENTS(s_aValuesUD), s_aValuesUD }, 15393 { bs3CpuInstr3_vpgatherqd_xmm0_ebx_plus_0_plus_ymm1_x_1_xmm0_icebp_c32, X86_XCPT_UD, 0, T_AVX2_256, 0, 3, 1, 0, RT_ELEMENTS(s_aValuesUD), s_aValuesUD }, 15394 { bs3CpuInstr3_vpgatherqd_xmm0_ebx_plus_0_plus_ymm1_x_1_xmm1_icebp_c32, X86_XCPT_UD, 0, T_AVX2_256, 0, 3, 1, 1, RT_ELEMENTS(s_aValuesUD), s_aValuesUD }, 15395 { bs3CpuInstr3_vpgatherqd_xmm0_ebx_plus_0_plus_ymm1_x_1_xmm2_icebp_c32, X86_XCPT_DB, 0, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_64x1Y), s_aValues32_64x1Y }, 15396 { bs3CpuInstr3_vpgatherqd_xmm0_ebx_plus_0_plus_ymm1_x_2_xmm2_icebp_c32, X86_XCPT_DB, 0, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_64x2Y), s_aValues32_64x2Y }, 15397 { bs3CpuInstr3_vpgatherqd_xmm0_ebx_plus_2_plus_ymm1_x_1_xmm2_icebp_c32, X86_XCPT_DB, 2, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_64x1Y), s_aValues32_64x1Y }, 15398 { bs3CpuInstr3_vpgatherqd_xmm0_ebx_less_2_plus_ymm1_x_1_xmm2_icebp_c32, X86_XCPT_DB, -2, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_64x1Y), s_aValues32_64x1Y }, 15399 { bs3CpuInstr3_vpgatherqd_xmm0_ebx_plus_153_plus_ymm1_x_1_xmm2_icebp_c32, X86_XCPT_DB, 153, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_64x1Y), s_aValues32_64x1Y }, 15400 { bs3CpuInstr3_vpgatherqd_xmm0_ebx_less_153_plus_ymm1_x_1_xmm2_icebp_c32, X86_XCPT_DB, -153, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_64x1Y), s_aValues32_64x1Y }, 15401 }; 15402 static BS3CPUINSTR3_TEST7_T const s_aTests64[] = 15403 { 15404 { bs3CpuInstr3_vgatherqps_xmm0_ebx_plus_0_plus_xmm0_x_1_xmm2_icebp_c64, X86_XCPT_UD, 0, T_AVX2_128, 0, 3, 0, 2, RT_ELEMENTS(s_aValuesUD), s_aValuesUD }, 15405 { bs3CpuInstr3_vgatherqps_xmm0_ebx_plus_0_plus_xmm1_x_1_xmm0_icebp_c64, X86_XCPT_UD, 0, T_AVX2_128, 0, 3, 1, 0, RT_ELEMENTS(s_aValuesUD), s_aValuesUD }, 15406 { bs3CpuInstr3_vgatherqps_xmm0_ebx_plus_0_plus_xmm1_x_1_xmm1_icebp_c64, X86_XCPT_UD, 0, T_AVX2_128, 0, 3, 1, 1, RT_ELEMENTS(s_aValuesUD), s_aValuesUD }, 15407 { bs3CpuInstr3_vgatherqps_xmm0_ebx_plus_0_plus_xmm1_x_1_xmm2_icebp_c64, X86_XCPT_DB, 0, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_64x1X), s_aValues32_64x1X }, 15408 { bs3CpuInstr3_vgatherqps_xmm0_ebx_plus_0_plus_xmm1_x_2_xmm2_icebp_c64, X86_XCPT_DB, 0, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_64x2X), s_aValues32_64x2X }, 15409 { bs3CpuInstr3_vgatherqps_xmm0_ebx_plus_2_plus_xmm1_x_1_xmm2_icebp_c64, X86_XCPT_DB, 2, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_64x1X), s_aValues32_64x1X }, 15410 { bs3CpuInstr3_vgatherqps_xmm0_ebx_less_2_plus_xmm1_x_1_xmm2_icebp_c64, X86_XCPT_DB, -2, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_64x1X), s_aValues32_64x1X }, 15411 { bs3CpuInstr3_vgatherqps_xmm0_ebx_plus_153_plus_xmm1_x_1_xmm2_icebp_c64, X86_XCPT_DB, 153, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_64x1X), s_aValues32_64x1X }, 15412 { bs3CpuInstr3_vgatherqps_xmm0_ebx_less_153_plus_xmm1_x_1_xmm2_icebp_c64, X86_XCPT_DB, -153, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_64x1X), s_aValues32_64x1X }, 15413 { bs3CpuInstr3_vgatherqps_xmm0_rbx_plus_0_plus_xmm1_x_1_xmm2_icebp_c64, X86_XCPT_DB, 0, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_64x1X), s_aValues32_64x1X }, 15414 { bs3CpuInstr3_vgatherqps_xmm8_r8d_plus_0_plus_xmm9_x_1_xmm10_icebp_c64, X86_XCPT_DB, 0, T_AVX2_128, 8, 8, 9, 10, RT_ELEMENTS(s_aValues32_64x1X), s_aValues32_64x1X }, 15415 { bs3CpuInstr3_vgatherqps_xmm0_ebx_plus_0_plus_ymm0_x_1_xmm2_icebp_c64, X86_XCPT_UD, 0, T_AVX2_256, 0, 3, 0, 2, RT_ELEMENTS(s_aValuesUD), s_aValuesUD }, 15416 { bs3CpuInstr3_vgatherqps_xmm0_ebx_plus_0_plus_ymm1_x_1_xmm0_icebp_c64, X86_XCPT_UD, 0, T_AVX2_256, 0, 3, 1, 0, RT_ELEMENTS(s_aValuesUD), s_aValuesUD }, 15417 { bs3CpuInstr3_vgatherqps_xmm0_ebx_plus_0_plus_ymm1_x_1_xmm1_icebp_c64, X86_XCPT_UD, 0, T_AVX2_256, 0, 3, 1, 1, RT_ELEMENTS(s_aValuesUD), s_aValuesUD }, 15418 { bs3CpuInstr3_vgatherqps_xmm0_ebx_plus_0_plus_ymm1_x_1_xmm2_icebp_c64, X86_XCPT_DB, 0, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_64x1Y), s_aValues32_64x1Y }, 15419 { bs3CpuInstr3_vgatherqps_xmm0_ebx_plus_0_plus_ymm1_x_2_xmm2_icebp_c64, X86_XCPT_DB, 0, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_64x2Y), s_aValues32_64x2Y }, 15420 { bs3CpuInstr3_vgatherqps_xmm0_ebx_plus_2_plus_ymm1_x_1_xmm2_icebp_c64, X86_XCPT_DB, 2, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_64x1Y), s_aValues32_64x1Y }, 15421 { bs3CpuInstr3_vgatherqps_xmm0_ebx_less_2_plus_ymm1_x_1_xmm2_icebp_c64, X86_XCPT_DB, -2, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_64x1Y), s_aValues32_64x1Y }, 15422 { bs3CpuInstr3_vgatherqps_xmm0_ebx_plus_153_plus_ymm1_x_1_xmm2_icebp_c64, X86_XCPT_DB, 153, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_64x1Y), s_aValues32_64x1Y }, 15423 { bs3CpuInstr3_vgatherqps_xmm0_ebx_less_153_plus_ymm1_x_1_xmm2_icebp_c64, X86_XCPT_DB, -153, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_64x1Y), s_aValues32_64x1Y }, 15424 { bs3CpuInstr3_vgatherqps_xmm0_rbx_plus_0_plus_ymm1_x_1_xmm2_icebp_c64, X86_XCPT_DB, 0, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_64x1Y), s_aValues32_64x1Y }, 15425 { bs3CpuInstr3_vgatherqps_xmm8_r8d_plus_0_plus_ymm9_x_1_xmm10_icebp_c64, X86_XCPT_DB, 0, T_AVX2_256, 8, 8, 9, 10, RT_ELEMENTS(s_aValues32_64x1Y), s_aValues32_64x1Y }, 15426 15427 { bs3CpuInstr3_vpgatherqd_xmm0_ebx_plus_0_plus_xmm0_x_1_xmm2_icebp_c64, X86_XCPT_UD, 0, T_AVX2_128, 0, 3, 0, 2, RT_ELEMENTS(s_aValuesUD), s_aValuesUD }, 15428 { bs3CpuInstr3_vpgatherqd_xmm0_ebx_plus_0_plus_xmm1_x_1_xmm0_icebp_c64, X86_XCPT_UD, 0, T_AVX2_128, 0, 3, 1, 0, RT_ELEMENTS(s_aValuesUD), s_aValuesUD }, 15429 { bs3CpuInstr3_vpgatherqd_xmm0_ebx_plus_0_plus_xmm1_x_1_xmm1_icebp_c64, X86_XCPT_UD, 0, T_AVX2_128, 0, 3, 1, 1, RT_ELEMENTS(s_aValuesUD), s_aValuesUD }, 15430 { bs3CpuInstr3_vpgatherqd_xmm0_ebx_plus_0_plus_xmm1_x_1_xmm2_icebp_c64, X86_XCPT_DB, 0, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_64x1X), s_aValues32_64x1X }, 15431 { bs3CpuInstr3_vpgatherqd_xmm0_ebx_plus_0_plus_xmm1_x_2_xmm2_icebp_c64, X86_XCPT_DB, 0, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_64x2X), s_aValues32_64x2X }, 15432 { bs3CpuInstr3_vpgatherqd_xmm0_ebx_plus_2_plus_xmm1_x_1_xmm2_icebp_c64, X86_XCPT_DB, 2, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_64x1X), s_aValues32_64x1X }, 15433 { bs3CpuInstr3_vpgatherqd_xmm0_ebx_less_2_plus_xmm1_x_1_xmm2_icebp_c64, X86_XCPT_DB, -2, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_64x1X), s_aValues32_64x1X }, 15434 { bs3CpuInstr3_vpgatherqd_xmm0_ebx_plus_153_plus_xmm1_x_1_xmm2_icebp_c64, X86_XCPT_DB, 153, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_64x1X), s_aValues32_64x1X }, 15435 { bs3CpuInstr3_vpgatherqd_xmm0_ebx_less_153_plus_xmm1_x_1_xmm2_icebp_c64, X86_XCPT_DB, -153, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_64x1X), s_aValues32_64x1X }, 15436 { bs3CpuInstr3_vpgatherqd_xmm0_rbx_plus_0_plus_xmm1_x_1_xmm2_icebp_c64, X86_XCPT_DB, 0, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_64x1X), s_aValues32_64x1X }, 15437 { bs3CpuInstr3_vpgatherqd_xmm8_r8d_plus_0_plus_xmm9_x_1_xmm10_icebp_c64, X86_XCPT_DB, 0, T_AVX2_128, 8, 8, 9, 10, RT_ELEMENTS(s_aValues32_64x1X), s_aValues32_64x1X }, 15438 { bs3CpuInstr3_vpgatherqd_xmm0_ebx_plus_0_plus_ymm0_x_1_xmm2_icebp_c64, X86_XCPT_UD, 0, T_AVX2_256, 0, 3, 0, 2, RT_ELEMENTS(s_aValuesUD), s_aValuesUD }, 15439 { bs3CpuInstr3_vpgatherqd_xmm0_ebx_plus_0_plus_ymm1_x_1_xmm0_icebp_c64, X86_XCPT_UD, 0, T_AVX2_256, 0, 3, 1, 0, RT_ELEMENTS(s_aValuesUD), s_aValuesUD }, 15440 { bs3CpuInstr3_vpgatherqd_xmm0_ebx_plus_0_plus_ymm1_x_1_xmm1_icebp_c64, X86_XCPT_UD, 0, T_AVX2_256, 0, 3, 1, 1, RT_ELEMENTS(s_aValuesUD), s_aValuesUD }, 15441 { bs3CpuInstr3_vpgatherqd_xmm0_ebx_plus_0_plus_ymm1_x_1_xmm2_icebp_c64, X86_XCPT_DB, 0, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_64x1Y), s_aValues32_64x1Y }, 15442 { bs3CpuInstr3_vpgatherqd_xmm0_ebx_plus_0_plus_ymm1_x_2_xmm2_icebp_c64, X86_XCPT_DB, 0, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_64x2Y), s_aValues32_64x2Y }, 15443 { bs3CpuInstr3_vpgatherqd_xmm0_ebx_plus_2_plus_ymm1_x_1_xmm2_icebp_c64, X86_XCPT_DB, 2, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_64x1Y), s_aValues32_64x1Y }, 15444 { bs3CpuInstr3_vpgatherqd_xmm0_ebx_less_2_plus_ymm1_x_1_xmm2_icebp_c64, X86_XCPT_DB, -2, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_64x1Y), s_aValues32_64x1Y }, 15445 { bs3CpuInstr3_vpgatherqd_xmm0_ebx_plus_153_plus_ymm1_x_1_xmm2_icebp_c64, X86_XCPT_DB, 153, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_64x1Y), s_aValues32_64x1Y }, 15446 { bs3CpuInstr3_vpgatherqd_xmm0_ebx_less_153_plus_ymm1_x_1_xmm2_icebp_c64, X86_XCPT_DB, -153, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_64x1Y), s_aValues32_64x1Y }, 15447 { bs3CpuInstr3_vpgatherqd_xmm0_rbx_plus_0_plus_ymm1_x_1_xmm2_icebp_c64, X86_XCPT_DB, 0, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_64x1Y), s_aValues32_64x1Y }, 15448 { bs3CpuInstr3_vpgatherqd_xmm8_r8d_plus_0_plus_ymm9_x_1_xmm10_icebp_c64, X86_XCPT_DB, 0, T_AVX2_256, 8, 8, 9, 10, RT_ELEMENTS(s_aValues32_64x1Y), s_aValues32_64x1Y }, 15449 }; 15450 static BS3CPUINSTR3_TEST7_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST7_MODES_INIT(s_aTests16, s_aTests32, s_aTests64); 15451 unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode); 15452 return bs3CpuInstr3_WorkerTestType7(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests, 15453 g_aXcptConfig5, RT_ELEMENTS(g_aXcptConfig5)); 15454 } 15455 15456 15457 /* 15458 * VGATHERDPD - Gather Packed Double Precision FP Values Using Signed Dword Indices 15459 * VPGATHERDQ - Gather Packed Qword Values Using Signed Dword Indices 15460 */ 15461 15462 BS3_DECL_FAR(uint8_t) bs3CpuInstr3_vgatherdpd_vpgatherdq(uint8_t bMode) 15463 { 15464 static BS3CPUINSTR3_TEST7_VALUES_T const s_aValuesUD[] = 15465 { // Values don't matter, instruction is supposed to #UD! 15466 { 15467 /*mask*/ RTUINT256_INIT_C(0, 0, 0, 0), 15468 /*pmsk*/ RTUINT256_INIT_C(0, 0, 0, 0), 15469 /*offs*/ RTUINT256_INIT_C(0, 0, 0, 0), 15470 /*init*/ RTUINT256_INIT_C(0, 0, 0, 0), 15471 /* => */ RTUINT256_INIT_C(0, 0, 0, 0), 15472 /*flgs*/ 0 }, 15473 }; 15474 static BS3CPUINSTR3_TEST7_VALUES_T const s_aValues64_32x1[] = 15475 { // 64-bit data slices and 32-bit indices times 1 15476 { 15477 /*mask*/ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000), 15478 /*pmsk*/ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000), 15479 /*offs*/ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000), 15480 /*init*/ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000), 15481 /* => */ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000), 15482 /*flgs*/ BS3_TEST_F_NO_PF }, 15483 { 15484 /*mask*/ RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff), 15485 /*pmsk*/ RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff), 15486 /*offs*/ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000), 15487 /*init*/ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000), 15488 /* => */ RTUINT256_INIT_C(0x0006000400020000, 0x0006000400020000, 0x0006000400020000, 0x0006000400020000), 15489 /*flgs*/ 0 }, 15490 { 15491 /*mask*/ RTUINT256_INIT_C(0xffffffff00000000, 0x11111111eeeeeeee, 0xdddddddd22222222, 0x33333333cccccccc), 15492 /*pmsk*/ RTUINT256_INIT_C(0xffffffffffffffff, 0x0000000000000000, 0xffffffffffffffff, 0x0000000000000000), 15493 /*offs*/ RTUINT256_INIT_C(0x0000000900000999, 0x123456789abcdef0, 0xfffff68900000006, 0x0000000700000008), 15494 /*init*/ RTUINT256_INIT_C(0x7878787878787878, 0x7878787878787878, 0x7878787878787878, 0x7878787878787878), 15495 /* => */ RTUINT256_INIT_C(0x90f68ef68cf68af6, 0x7878787878787878, 0x0e000c000a000800, 0x7878787878787878), 15496 15497 /*flgs*/ 0 }, 15498 }; 15499 static BS3CPUINSTR3_TEST7_VALUES_T const s_aValues64_32x2[] = 15500 { // 64-bit data slices and 32-bit indices times 2 15501 { 15502 /*mask*/ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000), 15503 /*pmsk*/ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000), 15504 /*offs*/ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000), 15505 /*init*/ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000), 15506 /* => */ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000), 15507 /*flgs*/ BS3_TEST_F_NO_PF }, 15508 { 15509 /*mask*/ RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff), 15510 /*pmsk*/ RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff), 15511 /*offs*/ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000), 15512 /*init*/ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000), 15513 /* => */ RTUINT256_INIT_C(0x0006000400020000, 0x0006000400020000, 0x0006000400020000, 0x0006000400020000), 15514 /*flgs*/ 0 }, 15515 { 15516 /*mask*/ RTUINT256_INIT_C(0xffffffff00000000, 0x11111111eeeeeeee, 0xdddddddd22222222, 0x33333333cccccccc), 15517 /*pmsk*/ RTUINT256_INIT_C(0xffffffffffffffff, 0x0000000000000000, 0xffffffffffffffff, 0x0000000000000000), 15518 /*offs*/ RTUINT256_INIT_C(0x0000000900000999, 0x123456789abcdef0, 0xfffff88900000006, 0x0000000700000008), 15519 /*init*/ RTUINT256_INIT_C(0x7878787878787878, 0x7878787878787878, 0x7878787878787878, 0x7878787878787878), 15520 /* => */ RTUINT256_INIT_C(0xf118f116f114f112, 0x7878787878787878, 0x001400120010000e, 0x7878787878787878), 15521 /*flgs*/ 0 }, 15522 }; 15523 15524 static BS3CPUINSTR3_TEST7_T const s_aTests16[] = 15525 { // inst_worker_func, bXcpt, offset, inst_type, init/dest mm, mem_ptr gp, offs mm, mask/pmsk mm, 15526 { bs3CpuInstr3_vgatherdpd_xmm0_ebx_plus_0_plus_xmm0_x_1_xmm2_icebp_c16, X86_XCPT_UD, 0, T_AVX2_128, 0, 3, 0, 2, RT_ELEMENTS(s_aValuesUD), s_aValuesUD }, 15527 { bs3CpuInstr3_vgatherdpd_xmm0_ebx_plus_0_plus_xmm1_x_1_xmm0_icebp_c16, X86_XCPT_UD, 0, T_AVX2_128, 0, 3, 1, 0, RT_ELEMENTS(s_aValuesUD), s_aValuesUD }, 15528 { bs3CpuInstr3_vgatherdpd_xmm0_ebx_plus_0_plus_xmm1_x_1_xmm1_icebp_c16, X86_XCPT_UD, 0, T_AVX2_128, 0, 3, 1, 1, RT_ELEMENTS(s_aValuesUD), s_aValuesUD }, 15529 { bs3CpuInstr3_vgatherdpd_xmm0_ebx_plus_0_plus_xmm1_x_1_xmm2_icebp_c16, X86_XCPT_DB, 0, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_32x1), s_aValues64_32x1 }, 15530 { bs3CpuInstr3_vgatherdpd_xmm0_ebx_plus_0_plus_xmm1_x_2_xmm2_icebp_c16, X86_XCPT_DB, 0, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_32x2), s_aValues64_32x2 }, 15531 { bs3CpuInstr3_vgatherdpd_xmm0_ebx_plus_2_plus_xmm1_x_1_xmm2_icebp_c16, X86_XCPT_DB, 2, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_32x1), s_aValues64_32x1 }, 15532 { bs3CpuInstr3_vgatherdpd_xmm0_ebx_less_2_plus_xmm1_x_1_xmm2_icebp_c16, X86_XCPT_DB, -2, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_32x1), s_aValues64_32x1 }, 15533 { bs3CpuInstr3_vgatherdpd_xmm0_ebx_plus_153_plus_xmm1_x_1_xmm2_icebp_c16, X86_XCPT_DB, 153, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_32x1), s_aValues64_32x1 }, 15534 { bs3CpuInstr3_vgatherdpd_xmm0_ebx_less_153_plus_xmm1_x_1_xmm2_icebp_c16, X86_XCPT_DB, -153, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_32x1), s_aValues64_32x1 }, 15535 { bs3CpuInstr3_vgatherdpd_ymm0_ebx_plus_0_plus_xmm0_x_1_ymm2_icebp_c16, X86_XCPT_UD, 0, T_AVX2_256, 0, 3, 0, 2, RT_ELEMENTS(s_aValuesUD), s_aValuesUD }, 15536 { bs3CpuInstr3_vgatherdpd_ymm0_ebx_plus_0_plus_xmm1_x_1_ymm0_icebp_c16, X86_XCPT_UD, 0, T_AVX2_256, 0, 3, 1, 0, RT_ELEMENTS(s_aValuesUD), s_aValuesUD }, 15537 { bs3CpuInstr3_vgatherdpd_ymm0_ebx_plus_0_plus_xmm1_x_1_ymm1_icebp_c16, X86_XCPT_UD, 0, T_AVX2_256, 0, 3, 1, 1, RT_ELEMENTS(s_aValuesUD), s_aValuesUD }, 15538 { bs3CpuInstr3_vgatherdpd_ymm0_ebx_plus_0_plus_xmm1_x_1_ymm2_icebp_c16, X86_XCPT_DB, 0, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_32x1), s_aValues64_32x1 }, 15539 { bs3CpuInstr3_vgatherdpd_ymm0_ebx_plus_0_plus_xmm1_x_2_ymm2_icebp_c16, X86_XCPT_DB, 0, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_32x2), s_aValues64_32x2 }, 15540 { bs3CpuInstr3_vgatherdpd_ymm0_ebx_plus_2_plus_xmm1_x_1_ymm2_icebp_c16, X86_XCPT_DB, 2, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_32x1), s_aValues64_32x1 }, 15541 { bs3CpuInstr3_vgatherdpd_ymm0_ebx_less_2_plus_xmm1_x_1_ymm2_icebp_c16, X86_XCPT_DB, -2, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_32x1), s_aValues64_32x1 }, 15542 { bs3CpuInstr3_vgatherdpd_ymm0_ebx_plus_153_plus_xmm1_x_1_ymm2_icebp_c16, X86_XCPT_DB, 153, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_32x1), s_aValues64_32x1 }, 15543 { bs3CpuInstr3_vgatherdpd_ymm0_ebx_less_153_plus_xmm1_x_1_ymm2_icebp_c16, X86_XCPT_DB, -153, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_32x1), s_aValues64_32x1 }, 15544 15545 { bs3CpuInstr3_vpgatherdq_xmm0_ebx_plus_0_plus_xmm0_x_1_xmm2_icebp_c16, X86_XCPT_UD, 0, T_AVX2_128, 0, 3, 0, 2, RT_ELEMENTS(s_aValuesUD), s_aValuesUD }, 15546 { bs3CpuInstr3_vpgatherdq_xmm0_ebx_plus_0_plus_xmm1_x_1_xmm0_icebp_c16, X86_XCPT_UD, 0, T_AVX2_128, 0, 3, 1, 0, RT_ELEMENTS(s_aValuesUD), s_aValuesUD }, 15547 { bs3CpuInstr3_vpgatherdq_xmm0_ebx_plus_0_plus_xmm1_x_1_xmm1_icebp_c16, X86_XCPT_UD, 0, T_AVX2_128, 0, 3, 1, 1, RT_ELEMENTS(s_aValuesUD), s_aValuesUD }, 15548 { bs3CpuInstr3_vpgatherdq_xmm0_ebx_plus_0_plus_xmm1_x_1_xmm2_icebp_c16, X86_XCPT_DB, 0, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_32x1), s_aValues64_32x1 }, 15549 { bs3CpuInstr3_vpgatherdq_xmm0_ebx_plus_0_plus_xmm1_x_2_xmm2_icebp_c16, X86_XCPT_DB, 0, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_32x2), s_aValues64_32x2 }, 15550 { bs3CpuInstr3_vpgatherdq_xmm0_ebx_plus_2_plus_xmm1_x_1_xmm2_icebp_c16, X86_XCPT_DB, 2, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_32x1), s_aValues64_32x1 }, 15551 { bs3CpuInstr3_vpgatherdq_xmm0_ebx_less_2_plus_xmm1_x_1_xmm2_icebp_c16, X86_XCPT_DB, -2, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_32x1), s_aValues64_32x1 }, 15552 { bs3CpuInstr3_vpgatherdq_xmm0_ebx_plus_153_plus_xmm1_x_1_xmm2_icebp_c16, X86_XCPT_DB, 153, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_32x1), s_aValues64_32x1 }, 15553 { bs3CpuInstr3_vpgatherdq_xmm0_ebx_less_153_plus_xmm1_x_1_xmm2_icebp_c16, X86_XCPT_DB, -153, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_32x1), s_aValues64_32x1 }, 15554 { bs3CpuInstr3_vpgatherdq_ymm0_ebx_plus_0_plus_xmm0_x_1_ymm2_icebp_c16, X86_XCPT_UD, 0, T_AVX2_256, 0, 3, 0, 2, RT_ELEMENTS(s_aValuesUD), s_aValuesUD }, 15555 { bs3CpuInstr3_vpgatherdq_ymm0_ebx_plus_0_plus_xmm1_x_1_ymm0_icebp_c16, X86_XCPT_UD, 0, T_AVX2_256, 0, 3, 1, 0, RT_ELEMENTS(s_aValuesUD), s_aValuesUD }, 15556 { bs3CpuInstr3_vpgatherdq_ymm0_ebx_plus_0_plus_xmm1_x_1_ymm1_icebp_c16, X86_XCPT_UD, 0, T_AVX2_256, 0, 3, 1, 1, RT_ELEMENTS(s_aValuesUD), s_aValuesUD }, 15557 { bs3CpuInstr3_vpgatherdq_ymm0_ebx_plus_0_plus_xmm1_x_1_ymm2_icebp_c16, X86_XCPT_DB, 0, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_32x1), s_aValues64_32x1 }, 15558 { bs3CpuInstr3_vpgatherdq_ymm0_ebx_plus_0_plus_xmm1_x_2_ymm2_icebp_c16, X86_XCPT_DB, 0, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_32x2), s_aValues64_32x2 }, 15559 { bs3CpuInstr3_vpgatherdq_ymm0_ebx_plus_2_plus_xmm1_x_1_ymm2_icebp_c16, X86_XCPT_DB, 2, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_32x1), s_aValues64_32x1 }, 15560 { bs3CpuInstr3_vpgatherdq_ymm0_ebx_less_2_plus_xmm1_x_1_ymm2_icebp_c16, X86_XCPT_DB, -2, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_32x1), s_aValues64_32x1 }, 15561 { bs3CpuInstr3_vpgatherdq_ymm0_ebx_plus_153_plus_xmm1_x_1_ymm2_icebp_c16, X86_XCPT_DB, 153, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_32x1), s_aValues64_32x1 }, 15562 { bs3CpuInstr3_vpgatherdq_ymm0_ebx_less_153_plus_xmm1_x_1_ymm2_icebp_c16, X86_XCPT_DB, -153, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_32x1), s_aValues64_32x1 }, 15563 }; 15564 static BS3CPUINSTR3_TEST7_T const s_aTests32[] = 15565 { 15566 { bs3CpuInstr3_vgatherdpd_xmm0_ebx_plus_0_plus_xmm0_x_1_xmm2_icebp_c32, X86_XCPT_UD, 0, T_AVX2_128, 0, 3, 0, 2, RT_ELEMENTS(s_aValuesUD), s_aValuesUD }, 15567 { bs3CpuInstr3_vgatherdpd_xmm0_ebx_plus_0_plus_xmm1_x_1_xmm0_icebp_c32, X86_XCPT_UD, 0, T_AVX2_128, 0, 3, 1, 0, RT_ELEMENTS(s_aValuesUD), s_aValuesUD }, 15568 { bs3CpuInstr3_vgatherdpd_xmm0_ebx_plus_0_plus_xmm1_x_1_xmm1_icebp_c32, X86_XCPT_UD, 0, T_AVX2_128, 0, 3, 1, 1, RT_ELEMENTS(s_aValuesUD), s_aValuesUD }, 15569 { bs3CpuInstr3_vgatherdpd_xmm0_ebx_plus_0_plus_xmm1_x_1_xmm2_icebp_c32, X86_XCPT_DB, 0, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_32x1), s_aValues64_32x1 }, 15570 { bs3CpuInstr3_vgatherdpd_xmm0_ebx_plus_0_plus_xmm1_x_2_xmm2_icebp_c32, X86_XCPT_DB, 0, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_32x2), s_aValues64_32x2 }, 15571 { bs3CpuInstr3_vgatherdpd_xmm0_ebx_plus_2_plus_xmm1_x_1_xmm2_icebp_c32, X86_XCPT_DB, 2, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_32x1), s_aValues64_32x1 }, 15572 { bs3CpuInstr3_vgatherdpd_xmm0_ebx_less_2_plus_xmm1_x_1_xmm2_icebp_c32, X86_XCPT_DB, -2, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_32x1), s_aValues64_32x1 }, 15573 { bs3CpuInstr3_vgatherdpd_xmm0_ebx_plus_153_plus_xmm1_x_1_xmm2_icebp_c32, X86_XCPT_DB, 153, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_32x1), s_aValues64_32x1 }, 15574 { bs3CpuInstr3_vgatherdpd_xmm0_ebx_less_153_plus_xmm1_x_1_xmm2_icebp_c32, X86_XCPT_DB, -153, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_32x1), s_aValues64_32x1 }, 15575 { bs3CpuInstr3_vgatherdpd_ymm0_ebx_plus_0_plus_xmm0_x_1_ymm2_icebp_c32, X86_XCPT_UD, 0, T_AVX2_256, 0, 3, 0, 2, RT_ELEMENTS(s_aValuesUD), s_aValuesUD }, 15576 { bs3CpuInstr3_vgatherdpd_ymm0_ebx_plus_0_plus_xmm1_x_1_ymm0_icebp_c32, X86_XCPT_UD, 0, T_AVX2_256, 0, 3, 1, 0, RT_ELEMENTS(s_aValuesUD), s_aValuesUD }, 15577 { bs3CpuInstr3_vgatherdpd_ymm0_ebx_plus_0_plus_xmm1_x_1_ymm1_icebp_c32, X86_XCPT_UD, 0, T_AVX2_256, 0, 3, 1, 1, RT_ELEMENTS(s_aValuesUD), s_aValuesUD }, 15578 { bs3CpuInstr3_vgatherdpd_ymm0_ebx_plus_0_plus_xmm1_x_1_ymm2_icebp_c32, X86_XCPT_DB, 0, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_32x1), s_aValues64_32x1 }, 15579 { bs3CpuInstr3_vgatherdpd_ymm0_ebx_plus_0_plus_xmm1_x_2_ymm2_icebp_c32, X86_XCPT_DB, 0, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_32x2), s_aValues64_32x2 }, 15580 { bs3CpuInstr3_vgatherdpd_ymm0_ebx_plus_2_plus_xmm1_x_1_ymm2_icebp_c32, X86_XCPT_DB, 2, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_32x1), s_aValues64_32x1 }, 15581 { bs3CpuInstr3_vgatherdpd_ymm0_ebx_less_2_plus_xmm1_x_1_ymm2_icebp_c32, X86_XCPT_DB, -2, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_32x1), s_aValues64_32x1 }, 15582 { bs3CpuInstr3_vgatherdpd_ymm0_ebx_plus_153_plus_xmm1_x_1_ymm2_icebp_c32, X86_XCPT_DB, 153, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_32x1), s_aValues64_32x1 }, 15583 { bs3CpuInstr3_vgatherdpd_ymm0_ebx_less_153_plus_xmm1_x_1_ymm2_icebp_c32, X86_XCPT_DB, -153, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_32x1), s_aValues64_32x1 }, 15584 15585 { bs3CpuInstr3_vpgatherdq_xmm0_ebx_plus_0_plus_xmm0_x_1_xmm2_icebp_c32, X86_XCPT_UD, 0, T_AVX2_128, 0, 3, 0, 2, RT_ELEMENTS(s_aValuesUD), s_aValuesUD }, 15586 { bs3CpuInstr3_vpgatherdq_xmm0_ebx_plus_0_plus_xmm1_x_1_xmm0_icebp_c32, X86_XCPT_UD, 0, T_AVX2_128, 0, 3, 1, 0, RT_ELEMENTS(s_aValuesUD), s_aValuesUD }, 15587 { bs3CpuInstr3_vpgatherdq_xmm0_ebx_plus_0_plus_xmm1_x_1_xmm1_icebp_c32, X86_XCPT_UD, 0, T_AVX2_128, 0, 3, 1, 1, RT_ELEMENTS(s_aValuesUD), s_aValuesUD }, 15588 { bs3CpuInstr3_vpgatherdq_xmm0_ebx_plus_0_plus_xmm1_x_1_xmm2_icebp_c32, X86_XCPT_DB, 0, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_32x1), s_aValues64_32x1 }, 15589 { bs3CpuInstr3_vpgatherdq_xmm0_ebx_plus_0_plus_xmm1_x_2_xmm2_icebp_c32, X86_XCPT_DB, 0, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_32x2), s_aValues64_32x2 }, 15590 { bs3CpuInstr3_vpgatherdq_xmm0_ebx_plus_2_plus_xmm1_x_1_xmm2_icebp_c32, X86_XCPT_DB, 2, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_32x1), s_aValues64_32x1 }, 15591 { bs3CpuInstr3_vpgatherdq_xmm0_ebx_less_2_plus_xmm1_x_1_xmm2_icebp_c32, X86_XCPT_DB, -2, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_32x1), s_aValues64_32x1 }, 15592 { bs3CpuInstr3_vpgatherdq_xmm0_ebx_plus_153_plus_xmm1_x_1_xmm2_icebp_c32, X86_XCPT_DB, 153, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_32x1), s_aValues64_32x1 }, 15593 { bs3CpuInstr3_vpgatherdq_xmm0_ebx_less_153_plus_xmm1_x_1_xmm2_icebp_c32, X86_XCPT_DB, -153, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_32x1), s_aValues64_32x1 }, 15594 { bs3CpuInstr3_vpgatherdq_ymm0_ebx_plus_0_plus_xmm0_x_1_ymm2_icebp_c32, X86_XCPT_UD, 0, T_AVX2_256, 0, 3, 0, 2, RT_ELEMENTS(s_aValuesUD), s_aValuesUD }, 15595 { bs3CpuInstr3_vpgatherdq_ymm0_ebx_plus_0_plus_xmm1_x_1_ymm0_icebp_c32, X86_XCPT_UD, 0, T_AVX2_256, 0, 3, 1, 0, RT_ELEMENTS(s_aValuesUD), s_aValuesUD }, 15596 { bs3CpuInstr3_vpgatherdq_ymm0_ebx_plus_0_plus_xmm1_x_1_ymm1_icebp_c32, X86_XCPT_UD, 0, T_AVX2_256, 0, 3, 1, 1, RT_ELEMENTS(s_aValuesUD), s_aValuesUD }, 15597 { bs3CpuInstr3_vpgatherdq_ymm0_ebx_plus_0_plus_xmm1_x_1_ymm2_icebp_c32, X86_XCPT_DB, 0, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_32x1), s_aValues64_32x1 }, 15598 { bs3CpuInstr3_vpgatherdq_ymm0_ebx_plus_0_plus_xmm1_x_2_ymm2_icebp_c32, X86_XCPT_DB, 0, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_32x2), s_aValues64_32x2 }, 15599 { bs3CpuInstr3_vpgatherdq_ymm0_ebx_plus_2_plus_xmm1_x_1_ymm2_icebp_c32, X86_XCPT_DB, 2, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_32x1), s_aValues64_32x1 }, 15600 { bs3CpuInstr3_vpgatherdq_ymm0_ebx_less_2_plus_xmm1_x_1_ymm2_icebp_c32, X86_XCPT_DB, -2, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_32x1), s_aValues64_32x1 }, 15601 { bs3CpuInstr3_vpgatherdq_ymm0_ebx_plus_153_plus_xmm1_x_1_ymm2_icebp_c32, X86_XCPT_DB, 153, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_32x1), s_aValues64_32x1 }, 15602 { bs3CpuInstr3_vpgatherdq_ymm0_ebx_less_153_plus_xmm1_x_1_ymm2_icebp_c32, X86_XCPT_DB, -153, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_32x1), s_aValues64_32x1 }, 15603 }; 15604 static BS3CPUINSTR3_TEST7_T const s_aTests64[] = 15605 { 15606 { bs3CpuInstr3_vgatherdpd_xmm0_ebx_plus_0_plus_xmm0_x_1_xmm2_icebp_c64, X86_XCPT_UD, 0, T_AVX2_128, 0, 3, 0, 2, RT_ELEMENTS(s_aValuesUD), s_aValuesUD }, 15607 { bs3CpuInstr3_vgatherdpd_xmm0_ebx_plus_0_plus_xmm1_x_1_xmm0_icebp_c64, X86_XCPT_UD, 0, T_AVX2_128, 0, 3, 1, 0, RT_ELEMENTS(s_aValuesUD), s_aValuesUD }, 15608 { bs3CpuInstr3_vgatherdpd_xmm0_ebx_plus_0_plus_xmm1_x_1_xmm1_icebp_c64, X86_XCPT_UD, 0, T_AVX2_128, 0, 3, 1, 1, RT_ELEMENTS(s_aValuesUD), s_aValuesUD }, 15609 { bs3CpuInstr3_vgatherdpd_xmm0_ebx_plus_0_plus_xmm1_x_1_xmm2_icebp_c64, X86_XCPT_DB, 0, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_32x1), s_aValues64_32x1 }, 15610 { bs3CpuInstr3_vgatherdpd_xmm0_ebx_plus_0_plus_xmm1_x_2_xmm2_icebp_c64, X86_XCPT_DB, 0, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_32x2), s_aValues64_32x2 }, 15611 { bs3CpuInstr3_vgatherdpd_xmm0_ebx_plus_2_plus_xmm1_x_1_xmm2_icebp_c64, X86_XCPT_DB, 2, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_32x1), s_aValues64_32x1 }, 15612 { bs3CpuInstr3_vgatherdpd_xmm0_ebx_less_2_plus_xmm1_x_1_xmm2_icebp_c64, X86_XCPT_DB, -2, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_32x1), s_aValues64_32x1 }, 15613 { bs3CpuInstr3_vgatherdpd_xmm0_ebx_plus_153_plus_xmm1_x_1_xmm2_icebp_c64, X86_XCPT_DB, 153, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_32x1), s_aValues64_32x1 }, 15614 { bs3CpuInstr3_vgatherdpd_xmm0_ebx_less_153_plus_xmm1_x_1_xmm2_icebp_c64, X86_XCPT_DB, -153, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_32x1), s_aValues64_32x1 }, 15615 { bs3CpuInstr3_vgatherdpd_xmm0_rbx_plus_0_plus_xmm1_x_1_xmm2_icebp_c64, X86_XCPT_DB, 0, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_32x1), s_aValues64_32x1 }, 15616 { bs3CpuInstr3_vgatherdpd_xmm8_r8d_plus_0_plus_xmm9_x_1_xmm10_icebp_c64, X86_XCPT_DB, 0, T_AVX2_128, 8, 8, 9, 10, RT_ELEMENTS(s_aValues64_32x1), s_aValues64_32x1 }, 15617 { bs3CpuInstr3_vgatherdpd_ymm0_ebx_plus_0_plus_xmm0_x_1_ymm2_icebp_c64, X86_XCPT_UD, 0, T_AVX2_256, 0, 3, 0, 2, RT_ELEMENTS(s_aValuesUD), s_aValuesUD }, 15618 { bs3CpuInstr3_vgatherdpd_ymm0_ebx_plus_0_plus_xmm1_x_1_ymm0_icebp_c64, X86_XCPT_UD, 0, T_AVX2_256, 0, 3, 1, 0, RT_ELEMENTS(s_aValuesUD), s_aValuesUD }, 15619 { bs3CpuInstr3_vgatherdpd_ymm0_ebx_plus_0_plus_xmm1_x_1_ymm1_icebp_c64, X86_XCPT_UD, 0, T_AVX2_256, 0, 3, 1, 1, RT_ELEMENTS(s_aValuesUD), s_aValuesUD }, 15620 { bs3CpuInstr3_vgatherdpd_ymm0_ebx_plus_0_plus_xmm1_x_1_ymm2_icebp_c64, X86_XCPT_DB, 0, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_32x1), s_aValues64_32x1 }, 15621 { bs3CpuInstr3_vgatherdpd_ymm0_ebx_plus_0_plus_xmm1_x_2_ymm2_icebp_c64, X86_XCPT_DB, 0, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_32x2), s_aValues64_32x2 }, 15622 { bs3CpuInstr3_vgatherdpd_ymm0_ebx_plus_2_plus_xmm1_x_1_ymm2_icebp_c64, X86_XCPT_DB, 2, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_32x1), s_aValues64_32x1 }, 15623 { bs3CpuInstr3_vgatherdpd_ymm0_ebx_less_2_plus_xmm1_x_1_ymm2_icebp_c64, X86_XCPT_DB, -2, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_32x1), s_aValues64_32x1 }, 15624 { bs3CpuInstr3_vgatherdpd_ymm0_ebx_plus_153_plus_xmm1_x_1_ymm2_icebp_c64, X86_XCPT_DB, 153, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_32x1), s_aValues64_32x1 }, 15625 { bs3CpuInstr3_vgatherdpd_ymm0_ebx_less_153_plus_xmm1_x_1_ymm2_icebp_c64, X86_XCPT_DB, -153, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_32x1), s_aValues64_32x1 }, 15626 { bs3CpuInstr3_vgatherdpd_ymm0_rbx_plus_0_plus_xmm1_x_1_ymm2_icebp_c64, X86_XCPT_DB, 0, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_32x1), s_aValues64_32x1 }, 15627 { bs3CpuInstr3_vgatherdpd_ymm8_r8d_plus_0_plus_xmm9_x_1_ymm10_icebp_c64, X86_XCPT_DB, 0, T_AVX2_256, 8, 8, 9, 10, RT_ELEMENTS(s_aValues64_32x1), s_aValues64_32x1 }, 15628 15629 { bs3CpuInstr3_vpgatherdq_xmm0_ebx_plus_0_plus_xmm0_x_1_xmm2_icebp_c64, X86_XCPT_UD, 0, T_AVX2_128, 0, 3, 0, 2, RT_ELEMENTS(s_aValuesUD), s_aValuesUD }, 15630 { bs3CpuInstr3_vpgatherdq_xmm0_ebx_plus_0_plus_xmm1_x_1_xmm0_icebp_c64, X86_XCPT_UD, 0, T_AVX2_128, 0, 3, 1, 0, RT_ELEMENTS(s_aValuesUD), s_aValuesUD }, 15631 { bs3CpuInstr3_vpgatherdq_xmm0_ebx_plus_0_plus_xmm1_x_1_xmm1_icebp_c64, X86_XCPT_UD, 0, T_AVX2_128, 0, 3, 1, 1, RT_ELEMENTS(s_aValuesUD), s_aValuesUD }, 15632 { bs3CpuInstr3_vpgatherdq_xmm0_ebx_plus_0_plus_xmm1_x_1_xmm2_icebp_c64, X86_XCPT_DB, 0, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_32x1), s_aValues64_32x1 }, 15633 { bs3CpuInstr3_vpgatherdq_xmm0_ebx_plus_0_plus_xmm1_x_2_xmm2_icebp_c64, X86_XCPT_DB, 0, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_32x2), s_aValues64_32x2 }, 15634 { bs3CpuInstr3_vpgatherdq_xmm0_ebx_plus_2_plus_xmm1_x_1_xmm2_icebp_c64, X86_XCPT_DB, 2, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_32x1), s_aValues64_32x1 }, 15635 { bs3CpuInstr3_vpgatherdq_xmm0_ebx_less_2_plus_xmm1_x_1_xmm2_icebp_c64, X86_XCPT_DB, -2, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_32x1), s_aValues64_32x1 }, 15636 { bs3CpuInstr3_vpgatherdq_xmm0_ebx_plus_153_plus_xmm1_x_1_xmm2_icebp_c64, X86_XCPT_DB, 153, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_32x1), s_aValues64_32x1 }, 15637 { bs3CpuInstr3_vpgatherdq_xmm0_ebx_less_153_plus_xmm1_x_1_xmm2_icebp_c64, X86_XCPT_DB, -153, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_32x1), s_aValues64_32x1 }, 15638 { bs3CpuInstr3_vpgatherdq_xmm0_rbx_plus_0_plus_xmm1_x_1_xmm2_icebp_c64, X86_XCPT_DB, 0, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_32x1), s_aValues64_32x1 }, 15639 { bs3CpuInstr3_vpgatherdq_xmm8_r8d_plus_0_plus_xmm9_x_1_xmm10_icebp_c64, X86_XCPT_DB, 0, T_AVX2_128, 8, 8, 9, 10, RT_ELEMENTS(s_aValues64_32x1), s_aValues64_32x1 }, 15640 { bs3CpuInstr3_vpgatherdq_ymm0_ebx_plus_0_plus_xmm0_x_1_ymm2_icebp_c64, X86_XCPT_UD, 0, T_AVX2_256, 0, 3, 0, 2, RT_ELEMENTS(s_aValuesUD), s_aValuesUD }, 15641 { bs3CpuInstr3_vpgatherdq_ymm0_ebx_plus_0_plus_xmm1_x_1_ymm0_icebp_c64, X86_XCPT_UD, 0, T_AVX2_256, 0, 3, 1, 0, RT_ELEMENTS(s_aValuesUD), s_aValuesUD }, 15642 { bs3CpuInstr3_vpgatherdq_ymm0_ebx_plus_0_plus_xmm1_x_1_ymm1_icebp_c64, X86_XCPT_UD, 0, T_AVX2_256, 0, 3, 1, 1, RT_ELEMENTS(s_aValuesUD), s_aValuesUD }, 15643 { bs3CpuInstr3_vpgatherdq_ymm0_ebx_plus_0_plus_xmm1_x_1_ymm2_icebp_c64, X86_XCPT_DB, 0, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_32x1), s_aValues64_32x1 }, 15644 { bs3CpuInstr3_vpgatherdq_ymm0_ebx_plus_0_plus_xmm1_x_2_ymm2_icebp_c64, X86_XCPT_DB, 0, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_32x2), s_aValues64_32x2 }, 15645 { bs3CpuInstr3_vpgatherdq_ymm0_ebx_plus_2_plus_xmm1_x_1_ymm2_icebp_c64, X86_XCPT_DB, 2, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_32x1), s_aValues64_32x1 }, 15646 { bs3CpuInstr3_vpgatherdq_ymm0_ebx_less_2_plus_xmm1_x_1_ymm2_icebp_c64, X86_XCPT_DB, -2, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_32x1), s_aValues64_32x1 }, 15647 { bs3CpuInstr3_vpgatherdq_ymm0_ebx_plus_153_plus_xmm1_x_1_ymm2_icebp_c64, X86_XCPT_DB, 153, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_32x1), s_aValues64_32x1 }, 15648 { bs3CpuInstr3_vpgatherdq_ymm0_ebx_less_153_plus_xmm1_x_1_ymm2_icebp_c64, X86_XCPT_DB, -153, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_32x1), s_aValues64_32x1 }, 15649 { bs3CpuInstr3_vpgatherdq_ymm0_rbx_plus_0_plus_xmm1_x_1_ymm2_icebp_c64, X86_XCPT_DB, 0, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_32x1), s_aValues64_32x1 }, 15650 { bs3CpuInstr3_vpgatherdq_ymm8_r8d_plus_0_plus_xmm9_x_1_ymm10_icebp_c64, X86_XCPT_DB, 0, T_AVX2_256, 8, 8, 9, 10, RT_ELEMENTS(s_aValues64_32x1), s_aValues64_32x1 }, 15651 }; 15652 static BS3CPUINSTR3_TEST7_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST7_MODES_INIT(s_aTests16, s_aTests32, s_aTests64); 15653 unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode); 15654 return bs3CpuInstr3_WorkerTestType7(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests, 15655 g_aXcptConfig5, RT_ELEMENTS(g_aXcptConfig5)); 15656 } 15657 15658 15659 /* 15660 * VGATHERQPD - Gather Packed Double Precision FP Values Using Signed Qword Indices 15661 * VPGATHERQQ - Gather Packed Qword Values Using Signed Qword Indices 15662 */ 15663 BS3_DECL_FAR(uint8_t) bs3CpuInstr3_vgatherqpd_vpgatherqq(uint8_t bMode) 15664 { 15665 static BS3CPUINSTR3_TEST7_VALUES_T const s_aValuesUD[] = 15666 { // Values don't matter, instruction is supposed to #UD! 15667 { 15668 /*mask*/ RTUINT256_INIT_C(0, 0, 0, 0), 15669 /*pmsk*/ RTUINT256_INIT_C(0, 0, 0, 0), 15670 /*offs*/ RTUINT256_INIT_C(0, 0, 0, 0), 15671 /*init*/ RTUINT256_INIT_C(0, 0, 0, 0), 15672 /* => */ RTUINT256_INIT_C(0, 0, 0, 0), 15673 /*flgs*/ 0 }, 15674 }; 15675 static BS3CPUINSTR3_TEST7_VALUES_T const s_aValues64_64x1X[] = 15676 { // 64-bit data slices and 64-bit indices times 1; only 2 indices (XMM's worth) 15677 { 15678 /*mask*/ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000), 15679 /*pmsk*/ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000), 15680 /*offs*/ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000), 15681 /*init*/ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000), 15682 /* => */ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000), 15683 /*flgs*/ BS3_TEST_F_NO_PF }, 15684 { 15685 /*mask*/ RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff), 15686 /*pmsk*/ RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff), 15687 /*offs*/ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000), 15688 /*init*/ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000), 15689 /* => */ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0006000400020000, 0x0006000400020000), 15690 /*flgs*/ 0 }, 15691 { 15692 /*mask*/ RTUINT256_INIT_C(0xffffffff00000000, 0x11111111eeeeeeee, 0xdddddddd22222222, 0x33333333cccccccc), 15693 /*pmsk*/ RTUINT256_INIT_C(0xffffffffffffffff, 0x0000000000000000, 0xffffffffffffffff, 0x0000000000000000), 15694 /*offs*/ RTUINT256_INIT_C(0x0000000000000399, 0x123456789abcdef0, 0xffffffffffffff77, 0x00000000000003ed), 15695 /*init*/ RTUINT256_INIT_C(0x7878787878787878, 0x7878787878787878, 0x7878787878787878, 0x7878787878787878), 15696 /* => */ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x7eff7cff7aff78ff, 0x7878787878787878), 15697 /*flgs*/ 0 }, 15698 }; 15699 static BS3CPUINSTR3_TEST7_VALUES_T const s_aValues64_64x1Y[] = 15700 { // 64-bit data slices and 64-bit indices times 1; 4 indices (YMM's worth) 15701 { 15702 /*mask*/ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000), 15703 /*pmsk*/ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000), 15704 /*offs*/ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000), 15705 /*init*/ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000), 15706 /* => */ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000), 15707 /*flgs*/ BS3_TEST_F_NO_PF }, 15708 { 15709 /*mask*/ RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff), 15710 /*pmsk*/ RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff), 15711 /*offs*/ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000), 15712 /*init*/ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000), 15713 /* => */ RTUINT256_INIT_C(0x0006000400020000, 0x0006000400020000, 0x0006000400020000, 0x0006000400020000), 15714 /*flgs*/ 0 }, 15715 { 15716 /*mask*/ RTUINT256_INIT_C(0xffffffff00000000, 0x11111111eeeeeeee, 0xdddddddd22222222, 0x33333333cccccccc), 15717 /*pmsk*/ RTUINT256_INIT_C(0xffffffffffffffff, 0x0000000000000000, 0xffffffffffffffff, 0x0000000000000000), 15718 /*offs*/ RTUINT256_INIT_C(0x0000000000000399, 0x123456789abcdef0, 0xffffffffffffff77, 0x00000000000003ed), 15719 /*init*/ RTUINT256_INIT_C(0x7878787878787878, 0x7878787878787878, 0x7878787878787878, 0x7878787878787878), 15720 /* => */ RTUINT256_INIT_C(0xa0039e039c039a03, 0x7878787878787878, 0x7eff7cff7aff78ff, 0x7878787878787878), 15721 /*flgs*/ 0 }, 15722 }; 15723 static BS3CPUINSTR3_TEST7_VALUES_T const s_aValues64_64x2X[] = 15724 { // 64-bit data slices and 64-bit indices times 2; only 2 indices (XMM's worth) 15725 { 15726 /*mask*/ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000), 15727 /*pmsk*/ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000), 15728 /*offs*/ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000), 15729 /*init*/ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000), 15730 /* => */ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000), 15731 /*flgs*/ BS3_TEST_F_NO_PF }, 15732 { 15733 /*mask*/ RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff), 15734 /*pmsk*/ RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff), 15735 /*offs*/ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000), 15736 /*init*/ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000), 15737 /* => */ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0006000400020000, 0x0006000400020000), 15738 /*flgs*/ 0 }, 15739 { 15740 /*mask*/ RTUINT256_INIT_C(0xffffffff00000000, 0x11111111eeeeeeee, 0xdddddddd22222222, 0x33333333cccccccc), 15741 /*pmsk*/ RTUINT256_INIT_C(0xffffffffffffffff, 0x0000000000000000, 0xffffffffffffffff, 0x0000000000000000), 15742 /*offs*/ RTUINT256_INIT_C(0x0000000000000199, 0x123456789abcdef0, 0xffffffffffffffc7, 0x00000000000000cd), 15743 /*init*/ RTUINT256_INIT_C(0x7878787878787878, 0x7878787878787878, 0x7878787878787878, 0x7878787878787878), 15744 /* => */ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0xff94ff92ff90ff8e, 0x7878787878787878), 15745 /*flgs*/ 0 }, 15746 }; 15747 static BS3CPUINSTR3_TEST7_VALUES_T const s_aValues64_64x2Y[] = 15748 { // 64-bit data slices and 64-bit indices times 2; 4 indices (YMM's worth) 15749 { 15750 /*mask*/ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000), 15751 /*pmsk*/ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000), 15752 /*offs*/ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000), 15753 /*init*/ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000), 15754 /* => */ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000), 15755 /*flgs*/ BS3_TEST_F_NO_PF }, 15756 { 15757 /*mask*/ RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff), 15758 /*pmsk*/ RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff), 15759 /*offs*/ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000), 15760 /*init*/ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000), 15761 /* => */ RTUINT256_INIT_C(0x0006000400020000, 0x0006000400020000, 0x0006000400020000, 0x0006000400020000), 15762 /*flgs*/ 0 }, 15763 { 15764 /*mask*/ RTUINT256_INIT_C(0xffffffff00000000, 0x11111111eeeeeeee, 0xdddddddd22222222, 0x33333333cccccccc), 15765 /*pmsk*/ RTUINT256_INIT_C(0xffffffffffffffff, 0x0000000000000000, 0xffffffffffffffff, 0x0000000000000000), 15766 /*offs*/ RTUINT256_INIT_C(0x0000000000000199, 0x123456789abcdef0, 0xffffffffffffffc7, 0x00000000000000cd), 15767 /*init*/ RTUINT256_INIT_C(0x7878787878787878, 0x7878787878787878, 0x7878787878787878, 0x7878787878787878), 15768 /* => */ RTUINT256_INIT_C(0x0338033603340332, 0x7878787878787878, 0xff94ff92ff90ff8e, 0x7878787878787878), 15769 /*flgs*/ 0 }, 15770 }; 15771 15772 static BS3CPUINSTR3_TEST7_T const s_aTests16[] = 15773 { // inst_worker_func, bXcpt, offset, inst_type, init/dest mm, mem_ptr gp, offs mm, mask/pmsk mm, 15774 { bs3CpuInstr3_vgatherqpd_xmm0_ebx_plus_0_plus_xmm0_x_1_xmm2_icebp_c16, X86_XCPT_UD, 0, T_AVX2_128, 0, 3, 0, 2, RT_ELEMENTS(s_aValuesUD), s_aValuesUD }, 15775 { bs3CpuInstr3_vgatherqpd_xmm0_ebx_plus_0_plus_xmm1_x_1_xmm0_icebp_c16, X86_XCPT_UD, 0, T_AVX2_128, 0, 3, 1, 0, RT_ELEMENTS(s_aValuesUD), s_aValuesUD }, 15776 { bs3CpuInstr3_vgatherqpd_xmm0_ebx_plus_0_plus_xmm1_x_1_xmm1_icebp_c16, X86_XCPT_UD, 0, T_AVX2_128, 0, 3, 1, 1, RT_ELEMENTS(s_aValuesUD), s_aValuesUD }, 15777 { bs3CpuInstr3_vgatherqpd_xmm0_ebx_plus_0_plus_xmm1_x_1_xmm2_icebp_c16, X86_XCPT_DB, 0, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_64x1X), s_aValues64_64x1X }, 15778 { bs3CpuInstr3_vgatherqpd_xmm0_ebx_plus_0_plus_xmm1_x_2_xmm2_icebp_c16, X86_XCPT_DB, 0, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_64x2X), s_aValues64_64x2X }, 15779 { bs3CpuInstr3_vgatherqpd_xmm0_ebx_plus_2_plus_xmm1_x_1_xmm2_icebp_c16, X86_XCPT_DB, 2, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_64x1X), s_aValues64_64x1X }, 15780 { bs3CpuInstr3_vgatherqpd_xmm0_ebx_less_2_plus_xmm1_x_1_xmm2_icebp_c16, X86_XCPT_DB, -2, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_64x1X), s_aValues64_64x1X }, 15781 { bs3CpuInstr3_vgatherqpd_xmm0_ebx_plus_153_plus_xmm1_x_1_xmm2_icebp_c16, X86_XCPT_DB, 153, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_64x1X), s_aValues64_64x1X }, 15782 { bs3CpuInstr3_vgatherqpd_xmm0_ebx_less_153_plus_xmm1_x_1_xmm2_icebp_c16, X86_XCPT_DB, -153, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_64x1X), s_aValues64_64x1X }, 15783 { bs3CpuInstr3_vgatherqpd_ymm0_ebx_plus_0_plus_ymm0_x_1_ymm2_icebp_c16, X86_XCPT_UD, 0, T_AVX2_256, 0, 3, 0, 2, RT_ELEMENTS(s_aValuesUD), s_aValuesUD }, 15784 { bs3CpuInstr3_vgatherqpd_ymm0_ebx_plus_0_plus_ymm1_x_1_ymm0_icebp_c16, X86_XCPT_UD, 0, T_AVX2_256, 0, 3, 1, 0, RT_ELEMENTS(s_aValuesUD), s_aValuesUD }, 15785 { bs3CpuInstr3_vgatherqpd_ymm0_ebx_plus_0_plus_ymm1_x_1_ymm1_icebp_c16, X86_XCPT_UD, 0, T_AVX2_256, 0, 3, 1, 1, RT_ELEMENTS(s_aValuesUD), s_aValuesUD }, 15786 { bs3CpuInstr3_vgatherqpd_ymm0_ebx_plus_0_plus_ymm1_x_1_ymm2_icebp_c16, X86_XCPT_DB, 0, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_64x1Y), s_aValues64_64x1Y }, 15787 { bs3CpuInstr3_vgatherqpd_ymm0_ebx_plus_0_plus_ymm1_x_2_ymm2_icebp_c16, X86_XCPT_DB, 0, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_64x2Y), s_aValues64_64x2Y }, 15788 { bs3CpuInstr3_vgatherqpd_ymm0_ebx_plus_2_plus_ymm1_x_1_ymm2_icebp_c16, X86_XCPT_DB, 2, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_64x1Y), s_aValues64_64x1Y }, 15789 { bs3CpuInstr3_vgatherqpd_ymm0_ebx_less_2_plus_ymm1_x_1_ymm2_icebp_c16, X86_XCPT_DB, -2, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_64x1Y), s_aValues64_64x1Y }, 15790 { bs3CpuInstr3_vgatherqpd_ymm0_ebx_plus_153_plus_ymm1_x_1_ymm2_icebp_c16, X86_XCPT_DB, 153, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_64x1Y), s_aValues64_64x1Y }, 15791 { bs3CpuInstr3_vgatherqpd_ymm0_ebx_less_153_plus_ymm1_x_1_ymm2_icebp_c16, X86_XCPT_DB, -153, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_64x1Y), s_aValues64_64x1Y }, 15792 15793 { bs3CpuInstr3_vpgatherqq_xmm0_ebx_plus_0_plus_xmm0_x_1_xmm2_icebp_c16, X86_XCPT_UD, 0, T_AVX2_128, 0, 3, 0, 2, RT_ELEMENTS(s_aValuesUD), s_aValuesUD }, 15794 { bs3CpuInstr3_vpgatherqq_xmm0_ebx_plus_0_plus_xmm1_x_1_xmm0_icebp_c16, X86_XCPT_UD, 0, T_AVX2_128, 0, 3, 1, 0, RT_ELEMENTS(s_aValuesUD), s_aValuesUD }, 15795 { bs3CpuInstr3_vpgatherqq_xmm0_ebx_plus_0_plus_xmm1_x_1_xmm1_icebp_c16, X86_XCPT_UD, 0, T_AVX2_128, 0, 3, 1, 1, RT_ELEMENTS(s_aValuesUD), s_aValuesUD }, 15796 { bs3CpuInstr3_vpgatherqq_xmm0_ebx_plus_0_plus_xmm1_x_1_xmm2_icebp_c16, X86_XCPT_DB, 0, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_64x1X), s_aValues64_64x1X }, 15797 { bs3CpuInstr3_vpgatherqq_xmm0_ebx_plus_0_plus_xmm1_x_2_xmm2_icebp_c16, X86_XCPT_DB, 0, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_64x2X), s_aValues64_64x2X }, 15798 { bs3CpuInstr3_vpgatherqq_xmm0_ebx_plus_2_plus_xmm1_x_1_xmm2_icebp_c16, X86_XCPT_DB, 2, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_64x1X), s_aValues64_64x1X }, 15799 { bs3CpuInstr3_vpgatherqq_xmm0_ebx_less_2_plus_xmm1_x_1_xmm2_icebp_c16, X86_XCPT_DB, -2, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_64x1X), s_aValues64_64x1X }, 15800 { bs3CpuInstr3_vpgatherqq_xmm0_ebx_plus_153_plus_xmm1_x_1_xmm2_icebp_c16, X86_XCPT_DB, 153, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_64x1X), s_aValues64_64x1X }, 15801 { bs3CpuInstr3_vpgatherqq_xmm0_ebx_less_153_plus_xmm1_x_1_xmm2_icebp_c16, X86_XCPT_DB, -153, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_64x1X), s_aValues64_64x1X }, 15802 { bs3CpuInstr3_vpgatherqq_ymm0_ebx_plus_0_plus_ymm0_x_1_ymm2_icebp_c16, X86_XCPT_UD, 0, T_AVX2_256, 0, 3, 0, 2, RT_ELEMENTS(s_aValuesUD), s_aValuesUD }, 15803 { bs3CpuInstr3_vpgatherqq_ymm0_ebx_plus_0_plus_ymm1_x_1_ymm0_icebp_c16, X86_XCPT_UD, 0, T_AVX2_256, 0, 3, 1, 0, RT_ELEMENTS(s_aValuesUD), s_aValuesUD }, 15804 { bs3CpuInstr3_vpgatherqq_ymm0_ebx_plus_0_plus_ymm1_x_1_ymm1_icebp_c16, X86_XCPT_UD, 0, T_AVX2_256, 0, 3, 1, 1, RT_ELEMENTS(s_aValuesUD), s_aValuesUD }, 15805 { bs3CpuInstr3_vpgatherqq_ymm0_ebx_plus_0_plus_ymm1_x_1_ymm2_icebp_c16, X86_XCPT_DB, 0, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_64x1Y), s_aValues64_64x1Y }, 15806 { bs3CpuInstr3_vpgatherqq_ymm0_ebx_plus_0_plus_ymm1_x_2_ymm2_icebp_c16, X86_XCPT_DB, 0, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_64x2Y), s_aValues64_64x2Y }, 15807 { bs3CpuInstr3_vpgatherqq_ymm0_ebx_plus_2_plus_ymm1_x_1_ymm2_icebp_c16, X86_XCPT_DB, 2, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_64x1Y), s_aValues64_64x1Y }, 15808 { bs3CpuInstr3_vpgatherqq_ymm0_ebx_less_2_plus_ymm1_x_1_ymm2_icebp_c16, X86_XCPT_DB, -2, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_64x1Y), s_aValues64_64x1Y }, 15809 { bs3CpuInstr3_vpgatherqq_ymm0_ebx_plus_153_plus_ymm1_x_1_ymm2_icebp_c16, X86_XCPT_DB, 153, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_64x1Y), s_aValues64_64x1Y }, 15810 { bs3CpuInstr3_vpgatherqq_ymm0_ebx_less_153_plus_ymm1_x_1_ymm2_icebp_c16, X86_XCPT_DB, -153, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_64x1Y), s_aValues64_64x1Y }, 15811 }; 15812 static BS3CPUINSTR3_TEST7_T const s_aTests32[] = 15813 { 15814 { bs3CpuInstr3_vgatherqpd_xmm0_ebx_plus_0_plus_xmm0_x_1_xmm2_icebp_c32, X86_XCPT_UD, 0, T_AVX2_128, 0, 3, 0, 2, RT_ELEMENTS(s_aValuesUD), s_aValuesUD }, 15815 { bs3CpuInstr3_vgatherqpd_xmm0_ebx_plus_0_plus_xmm1_x_1_xmm0_icebp_c32, X86_XCPT_UD, 0, T_AVX2_128, 0, 3, 1, 0, RT_ELEMENTS(s_aValuesUD), s_aValuesUD }, 15816 { bs3CpuInstr3_vgatherqpd_xmm0_ebx_plus_0_plus_xmm1_x_1_xmm1_icebp_c32, X86_XCPT_UD, 0, T_AVX2_128, 0, 3, 1, 1, RT_ELEMENTS(s_aValuesUD), s_aValuesUD }, 15817 { bs3CpuInstr3_vgatherqpd_xmm0_ebx_plus_0_plus_xmm1_x_1_xmm2_icebp_c32, X86_XCPT_DB, 0, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_64x1X), s_aValues64_64x1X }, 15818 { bs3CpuInstr3_vgatherqpd_xmm0_ebx_plus_0_plus_xmm1_x_2_xmm2_icebp_c32, X86_XCPT_DB, 0, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_64x2X), s_aValues64_64x2X }, 15819 { bs3CpuInstr3_vgatherqpd_xmm0_ebx_plus_2_plus_xmm1_x_1_xmm2_icebp_c32, X86_XCPT_DB, 2, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_64x1X), s_aValues64_64x1X }, 15820 { bs3CpuInstr3_vgatherqpd_xmm0_ebx_less_2_plus_xmm1_x_1_xmm2_icebp_c32, X86_XCPT_DB, -2, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_64x1X), s_aValues64_64x1X }, 15821 { bs3CpuInstr3_vgatherqpd_xmm0_ebx_plus_153_plus_xmm1_x_1_xmm2_icebp_c32, X86_XCPT_DB, 153, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_64x1X), s_aValues64_64x1X }, 15822 { bs3CpuInstr3_vgatherqpd_xmm0_ebx_less_153_plus_xmm1_x_1_xmm2_icebp_c32, X86_XCPT_DB, -153, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_64x1X), s_aValues64_64x1X }, 15823 { bs3CpuInstr3_vgatherqpd_ymm0_ebx_plus_0_plus_ymm0_x_1_ymm2_icebp_c32, X86_XCPT_UD, 0, T_AVX2_256, 0, 3, 0, 2, RT_ELEMENTS(s_aValuesUD), s_aValuesUD }, 15824 { bs3CpuInstr3_vgatherqpd_ymm0_ebx_plus_0_plus_ymm1_x_1_ymm0_icebp_c32, X86_XCPT_UD, 0, T_AVX2_256, 0, 3, 1, 0, RT_ELEMENTS(s_aValuesUD), s_aValuesUD }, 15825 { bs3CpuInstr3_vgatherqpd_ymm0_ebx_plus_0_plus_ymm1_x_1_ymm1_icebp_c32, X86_XCPT_UD, 0, T_AVX2_256, 0, 3, 1, 1, RT_ELEMENTS(s_aValuesUD), s_aValuesUD }, 15826 { bs3CpuInstr3_vgatherqpd_ymm0_ebx_plus_0_plus_ymm1_x_1_ymm2_icebp_c32, X86_XCPT_DB, 0, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_64x1Y), s_aValues64_64x1Y }, 15827 { bs3CpuInstr3_vgatherqpd_ymm0_ebx_plus_0_plus_ymm1_x_2_ymm2_icebp_c32, X86_XCPT_DB, 0, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_64x2Y), s_aValues64_64x2Y }, 15828 { bs3CpuInstr3_vgatherqpd_ymm0_ebx_plus_2_plus_ymm1_x_1_ymm2_icebp_c32, X86_XCPT_DB, 2, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_64x1Y), s_aValues64_64x1Y }, 15829 { bs3CpuInstr3_vgatherqpd_ymm0_ebx_less_2_plus_ymm1_x_1_ymm2_icebp_c32, X86_XCPT_DB, -2, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_64x1Y), s_aValues64_64x1Y }, 15830 { bs3CpuInstr3_vgatherqpd_ymm0_ebx_plus_153_plus_ymm1_x_1_ymm2_icebp_c32, X86_XCPT_DB, 153, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_64x1Y), s_aValues64_64x1Y }, 15831 { bs3CpuInstr3_vgatherqpd_ymm0_ebx_less_153_plus_ymm1_x_1_ymm2_icebp_c32, X86_XCPT_DB, -153, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_64x1Y), s_aValues64_64x1Y }, 15832 15833 { bs3CpuInstr3_vpgatherqq_xmm0_ebx_plus_0_plus_xmm0_x_1_xmm2_icebp_c32, X86_XCPT_UD, 0, T_AVX2_128, 0, 3, 0, 2, RT_ELEMENTS(s_aValuesUD), s_aValuesUD }, 15834 { bs3CpuInstr3_vpgatherqq_xmm0_ebx_plus_0_plus_xmm1_x_1_xmm0_icebp_c32, X86_XCPT_UD, 0, T_AVX2_128, 0, 3, 1, 0, RT_ELEMENTS(s_aValuesUD), s_aValuesUD }, 15835 { bs3CpuInstr3_vpgatherqq_xmm0_ebx_plus_0_plus_xmm1_x_1_xmm1_icebp_c32, X86_XCPT_UD, 0, T_AVX2_128, 0, 3, 1, 1, RT_ELEMENTS(s_aValuesUD), s_aValuesUD }, 15836 { bs3CpuInstr3_vpgatherqq_xmm0_ebx_plus_0_plus_xmm1_x_1_xmm2_icebp_c32, X86_XCPT_DB, 0, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_64x1X), s_aValues64_64x1X }, 15837 { bs3CpuInstr3_vpgatherqq_xmm0_ebx_plus_0_plus_xmm1_x_2_xmm2_icebp_c32, X86_XCPT_DB, 0, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_64x2X), s_aValues64_64x2X }, 15838 { bs3CpuInstr3_vpgatherqq_xmm0_ebx_plus_2_plus_xmm1_x_1_xmm2_icebp_c32, X86_XCPT_DB, 2, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_64x1X), s_aValues64_64x1X }, 15839 { bs3CpuInstr3_vpgatherqq_xmm0_ebx_less_2_plus_xmm1_x_1_xmm2_icebp_c32, X86_XCPT_DB, -2, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_64x1X), s_aValues64_64x1X }, 15840 { bs3CpuInstr3_vpgatherqq_xmm0_ebx_plus_153_plus_xmm1_x_1_xmm2_icebp_c32, X86_XCPT_DB, 153, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_64x1X), s_aValues64_64x1X }, 15841 { bs3CpuInstr3_vpgatherqq_xmm0_ebx_less_153_plus_xmm1_x_1_xmm2_icebp_c32, X86_XCPT_DB, -153, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_64x1X), s_aValues64_64x1X }, 15842 { bs3CpuInstr3_vpgatherqq_ymm0_ebx_plus_0_plus_ymm0_x_1_ymm2_icebp_c32, X86_XCPT_UD, 0, T_AVX2_256, 0, 3, 0, 2, RT_ELEMENTS(s_aValuesUD), s_aValuesUD }, 15843 { bs3CpuInstr3_vpgatherqq_ymm0_ebx_plus_0_plus_ymm1_x_1_ymm0_icebp_c32, X86_XCPT_UD, 0, T_AVX2_256, 0, 3, 1, 0, RT_ELEMENTS(s_aValuesUD), s_aValuesUD }, 15844 { bs3CpuInstr3_vpgatherqq_ymm0_ebx_plus_0_plus_ymm1_x_1_ymm1_icebp_c32, X86_XCPT_UD, 0, T_AVX2_256, 0, 3, 1, 1, RT_ELEMENTS(s_aValuesUD), s_aValuesUD }, 15845 { bs3CpuInstr3_vpgatherqq_ymm0_ebx_plus_0_plus_ymm1_x_1_ymm2_icebp_c32, X86_XCPT_DB, 0, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_64x1Y), s_aValues64_64x1Y }, 15846 { bs3CpuInstr3_vpgatherqq_ymm0_ebx_plus_0_plus_ymm1_x_2_ymm2_icebp_c32, X86_XCPT_DB, 0, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_64x2Y), s_aValues64_64x2Y }, 15847 { bs3CpuInstr3_vpgatherqq_ymm0_ebx_plus_2_plus_ymm1_x_1_ymm2_icebp_c32, X86_XCPT_DB, 2, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_64x1Y), s_aValues64_64x1Y }, 15848 { bs3CpuInstr3_vpgatherqq_ymm0_ebx_less_2_plus_ymm1_x_1_ymm2_icebp_c32, X86_XCPT_DB, -2, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_64x1Y), s_aValues64_64x1Y }, 15849 { bs3CpuInstr3_vpgatherqq_ymm0_ebx_plus_153_plus_ymm1_x_1_ymm2_icebp_c32, X86_XCPT_DB, 153, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_64x1Y), s_aValues64_64x1Y }, 15850 { bs3CpuInstr3_vpgatherqq_ymm0_ebx_less_153_plus_ymm1_x_1_ymm2_icebp_c32, X86_XCPT_DB, -153, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_64x1Y), s_aValues64_64x1Y }, 15851 }; 15852 static BS3CPUINSTR3_TEST7_T const s_aTests64[] = 15853 { 15854 { bs3CpuInstr3_vgatherqpd_xmm0_ebx_plus_0_plus_xmm0_x_1_xmm2_icebp_c64, X86_XCPT_UD, 0, T_AVX2_128, 0, 3, 0, 2, RT_ELEMENTS(s_aValuesUD), s_aValuesUD }, 15855 { bs3CpuInstr3_vgatherqpd_xmm0_ebx_plus_0_plus_xmm1_x_1_xmm0_icebp_c64, X86_XCPT_UD, 0, T_AVX2_128, 0, 3, 1, 0, RT_ELEMENTS(s_aValuesUD), s_aValuesUD }, 15856 { bs3CpuInstr3_vgatherqpd_xmm0_ebx_plus_0_plus_xmm1_x_1_xmm1_icebp_c64, X86_XCPT_UD, 0, T_AVX2_128, 0, 3, 1, 1, RT_ELEMENTS(s_aValuesUD), s_aValuesUD }, 15857 { bs3CpuInstr3_vgatherqpd_xmm0_ebx_plus_0_plus_xmm1_x_1_xmm2_icebp_c64, X86_XCPT_DB, 0, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_64x1X), s_aValues64_64x1X }, 15858 { bs3CpuInstr3_vgatherqpd_xmm0_ebx_plus_0_plus_xmm1_x_2_xmm2_icebp_c64, X86_XCPT_DB, 0, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_64x2X), s_aValues64_64x2X }, 15859 { bs3CpuInstr3_vgatherqpd_xmm0_ebx_plus_2_plus_xmm1_x_1_xmm2_icebp_c64, X86_XCPT_DB, 2, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_64x1X), s_aValues64_64x1X }, 15860 { bs3CpuInstr3_vgatherqpd_xmm0_ebx_less_2_plus_xmm1_x_1_xmm2_icebp_c64, X86_XCPT_DB, -2, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_64x1X), s_aValues64_64x1X }, 15861 { bs3CpuInstr3_vgatherqpd_xmm0_ebx_plus_153_plus_xmm1_x_1_xmm2_icebp_c64, X86_XCPT_DB, 153, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_64x1X), s_aValues64_64x1X }, 15862 { bs3CpuInstr3_vgatherqpd_xmm0_ebx_less_153_plus_xmm1_x_1_xmm2_icebp_c64, X86_XCPT_DB, -153, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_64x1X), s_aValues64_64x1X }, 15863 { bs3CpuInstr3_vgatherqpd_xmm0_rbx_plus_0_plus_xmm1_x_1_xmm2_icebp_c64, X86_XCPT_DB, 0, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_64x1X), s_aValues64_64x1X }, 15864 { bs3CpuInstr3_vgatherqpd_xmm8_r8d_plus_0_plus_xmm9_x_1_xmm10_icebp_c64, X86_XCPT_DB, 0, T_AVX2_128, 8, 8, 9, 10, RT_ELEMENTS(s_aValues64_64x1X), s_aValues64_64x1X }, 15865 { bs3CpuInstr3_vgatherqpd_ymm0_ebx_plus_0_plus_ymm0_x_1_ymm2_icebp_c64, X86_XCPT_UD, 0, T_AVX2_256, 0, 3, 0, 2, RT_ELEMENTS(s_aValuesUD), s_aValuesUD }, 15866 { bs3CpuInstr3_vgatherqpd_ymm0_ebx_plus_0_plus_ymm1_x_1_ymm0_icebp_c64, X86_XCPT_UD, 0, T_AVX2_256, 0, 3, 1, 0, RT_ELEMENTS(s_aValuesUD), s_aValuesUD }, 15867 { bs3CpuInstr3_vgatherqpd_ymm0_ebx_plus_0_plus_ymm1_x_1_ymm1_icebp_c64, X86_XCPT_UD, 0, T_AVX2_256, 0, 3, 1, 1, RT_ELEMENTS(s_aValuesUD), s_aValuesUD }, 15868 { bs3CpuInstr3_vgatherqpd_ymm0_ebx_plus_0_plus_ymm1_x_1_ymm2_icebp_c64, X86_XCPT_DB, 0, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_64x1Y), s_aValues64_64x1Y }, 15869 { bs3CpuInstr3_vgatherqpd_ymm0_ebx_plus_0_plus_ymm1_x_2_ymm2_icebp_c64, X86_XCPT_DB, 0, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_64x2Y), s_aValues64_64x2Y }, 15870 { bs3CpuInstr3_vgatherqpd_ymm0_ebx_plus_2_plus_ymm1_x_1_ymm2_icebp_c64, X86_XCPT_DB, 2, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_64x1Y), s_aValues64_64x1Y }, 15871 { bs3CpuInstr3_vgatherqpd_ymm0_ebx_less_2_plus_ymm1_x_1_ymm2_icebp_c64, X86_XCPT_DB, -2, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_64x1Y), s_aValues64_64x1Y }, 15872 { bs3CpuInstr3_vgatherqpd_ymm0_ebx_plus_153_plus_ymm1_x_1_ymm2_icebp_c64, X86_XCPT_DB, 153, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_64x1Y), s_aValues64_64x1Y }, 15873 { bs3CpuInstr3_vgatherqpd_ymm0_ebx_less_153_plus_ymm1_x_1_ymm2_icebp_c64, X86_XCPT_DB, -153, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_64x1Y), s_aValues64_64x1Y }, 15874 { bs3CpuInstr3_vgatherqpd_ymm0_rbx_plus_0_plus_ymm1_x_1_ymm2_icebp_c64, X86_XCPT_DB, 0, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_64x1Y), s_aValues64_64x1Y }, 15875 { bs3CpuInstr3_vgatherqpd_ymm8_r8d_plus_0_plus_ymm9_x_1_ymm10_icebp_c64, X86_XCPT_DB, 0, T_AVX2_256, 8, 8, 9, 10, RT_ELEMENTS(s_aValues64_64x1Y), s_aValues64_64x1Y }, 15876 15877 { bs3CpuInstr3_vpgatherqq_xmm0_ebx_plus_0_plus_xmm0_x_1_xmm2_icebp_c64, X86_XCPT_UD, 0, T_AVX2_128, 0, 3, 0, 2, RT_ELEMENTS(s_aValuesUD), s_aValuesUD }, 15878 { bs3CpuInstr3_vpgatherqq_xmm0_ebx_plus_0_plus_xmm1_x_1_xmm0_icebp_c64, X86_XCPT_UD, 0, T_AVX2_128, 0, 3, 1, 0, RT_ELEMENTS(s_aValuesUD), s_aValuesUD }, 15879 { bs3CpuInstr3_vpgatherqq_xmm0_ebx_plus_0_plus_xmm1_x_1_xmm1_icebp_c64, X86_XCPT_UD, 0, T_AVX2_128, 0, 3, 1, 1, RT_ELEMENTS(s_aValuesUD), s_aValuesUD }, 15880 { bs3CpuInstr3_vpgatherqq_xmm0_ebx_plus_0_plus_xmm1_x_1_xmm2_icebp_c64, X86_XCPT_DB, 0, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_64x1X), s_aValues64_64x1X }, 15881 { bs3CpuInstr3_vpgatherqq_xmm0_ebx_plus_0_plus_xmm1_x_2_xmm2_icebp_c64, X86_XCPT_DB, 0, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_64x2X), s_aValues64_64x2X }, 15882 { bs3CpuInstr3_vpgatherqq_xmm0_ebx_plus_2_plus_xmm1_x_1_xmm2_icebp_c64, X86_XCPT_DB, 2, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_64x1X), s_aValues64_64x1X }, 15883 { bs3CpuInstr3_vpgatherqq_xmm0_ebx_less_2_plus_xmm1_x_1_xmm2_icebp_c64, X86_XCPT_DB, -2, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_64x1X), s_aValues64_64x1X }, 15884 { bs3CpuInstr3_vpgatherqq_xmm0_ebx_plus_153_plus_xmm1_x_1_xmm2_icebp_c64, X86_XCPT_DB, 153, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_64x1X), s_aValues64_64x1X }, 15885 { bs3CpuInstr3_vpgatherqq_xmm0_ebx_less_153_plus_xmm1_x_1_xmm2_icebp_c64, X86_XCPT_DB, -153, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_64x1X), s_aValues64_64x1X }, 15886 { bs3CpuInstr3_vpgatherqq_xmm0_rbx_plus_0_plus_xmm1_x_1_xmm2_icebp_c64, X86_XCPT_DB, 0, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_64x1X), s_aValues64_64x1X }, 15887 { bs3CpuInstr3_vpgatherqq_xmm8_r8d_plus_0_plus_xmm9_x_1_xmm10_icebp_c64, X86_XCPT_DB, 0, T_AVX2_128, 8, 8, 9, 10, RT_ELEMENTS(s_aValues64_64x1X), s_aValues64_64x1X }, 15888 { bs3CpuInstr3_vpgatherqq_ymm0_ebx_plus_0_plus_ymm0_x_1_ymm2_icebp_c64, X86_XCPT_UD, 0, T_AVX2_256, 0, 3, 0, 2, RT_ELEMENTS(s_aValuesUD), s_aValuesUD }, 15889 { bs3CpuInstr3_vpgatherqq_ymm0_ebx_plus_0_plus_ymm1_x_1_ymm0_icebp_c64, X86_XCPT_UD, 0, T_AVX2_256, 0, 3, 1, 0, RT_ELEMENTS(s_aValuesUD), s_aValuesUD }, 15890 { bs3CpuInstr3_vpgatherqq_ymm0_ebx_plus_0_plus_ymm1_x_1_ymm1_icebp_c64, X86_XCPT_UD, 0, T_AVX2_256, 0, 3, 1, 1, RT_ELEMENTS(s_aValuesUD), s_aValuesUD }, 15891 { bs3CpuInstr3_vpgatherqq_ymm0_ebx_plus_0_plus_ymm1_x_1_ymm2_icebp_c64, X86_XCPT_DB, 0, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_64x1Y), s_aValues64_64x1Y }, 15892 { bs3CpuInstr3_vpgatherqq_ymm0_ebx_plus_0_plus_ymm1_x_2_ymm2_icebp_c64, X86_XCPT_DB, 0, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_64x2Y), s_aValues64_64x2Y }, 15893 { bs3CpuInstr3_vpgatherqq_ymm0_ebx_plus_2_plus_ymm1_x_1_ymm2_icebp_c64, X86_XCPT_DB, 2, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_64x1Y), s_aValues64_64x1Y }, 15894 { bs3CpuInstr3_vpgatherqq_ymm0_ebx_less_2_plus_ymm1_x_1_ymm2_icebp_c64, X86_XCPT_DB, -2, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_64x1Y), s_aValues64_64x1Y }, 15895 { bs3CpuInstr3_vpgatherqq_ymm0_ebx_plus_153_plus_ymm1_x_1_ymm2_icebp_c64, X86_XCPT_DB, 153, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_64x1Y), s_aValues64_64x1Y }, 15896 { bs3CpuInstr3_vpgatherqq_ymm0_ebx_less_153_plus_ymm1_x_1_ymm2_icebp_c64, X86_XCPT_DB, -153, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_64x1Y), s_aValues64_64x1Y }, 15897 { bs3CpuInstr3_vpgatherqq_ymm0_rbx_plus_0_plus_ymm1_x_1_ymm2_icebp_c64, X86_XCPT_DB, 0, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_64x1Y), s_aValues64_64x1Y }, 15898 { bs3CpuInstr3_vpgatherqq_ymm8_r8d_plus_0_plus_ymm9_x_1_ymm10_icebp_c64, X86_XCPT_DB, 0, T_AVX2_256, 8, 8, 9, 10, RT_ELEMENTS(s_aValues64_64x1Y), s_aValues64_64x1Y }, 15899 }; 15900 static BS3CPUINSTR3_TEST7_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST7_MODES_INIT(s_aTests16, s_aTests32, s_aTests64); 15901 unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode); 15902 return bs3CpuInstr3_WorkerTestType7(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests, 15903 g_aXcptConfig5, RT_ELEMENTS(g_aXcptConfig5)); 15904 } 15905 14734 15906 14735 15907 /** … … 14940 16112 { "vmaskmovps/vmaskmovpd/vpmaskmovd/vpmaskmovq", bs3CpuInstr3_vmaskmovps_d_vpmaskmovd_q, 0 }, 14941 16113 #endif 16114 #if defined(ALL_TESTS) 16115 { "vgatherdps/vpgatherdd", bs3CpuInstr3_vgatherdps_vpgatherdd, 0 }, 16116 { "vgatherqps/vpgatherqd", bs3CpuInstr3_vgatherqps_vpgatherqd, 0 }, 16117 { "vgatherdpd/vpgatherdq", bs3CpuInstr3_vgatherdpd_vpgatherdq, 0 }, 16118 { "vgatherqpd/vpgatherqq", bs3CpuInstr3_vgatherqpd_vpgatherqq, 0 }, 16119 #endif 14942 16120 }; 14943 16121 Bs3TestInit("bs3-cpu-instr-3");
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