Changeset 10567 in vbox for trunk/src/VBox

Timestamp:

Jul 12, 2008 3:29:13 PM (16 years ago)

Author:

vboxsync

Message:

Expose cpuid 0x80000007 (AMD - Advanced Power Management (TSC invariant)) and 0x80000008 (virtual & physical address size) to the guest.

Location:

trunk/src/VBox/VMM

Files:

• CPUM.cpp (modified) (3 diffs)
• TM.cpp (modified) (1 diff)

trunk/src/VBox/VMM/CPUM.cpp

@@ -348 +348 @@
      * Intel returns values of the highest standard function, while AMD
      * returns zeros. VIA on the other hand seems to returning nothing or
-     * perhaps some random garbage, we don't try duplicate this behavior.
+     * perhaps some random garbage, we don't try to duplicate this behavior.
      */
     ASMCpuId(pCPUM->aGuestCpuIdStd[0].eax + 10,
@@ -363 +363 @@
      */
 
+    /* Cpuid 0x800000007: 
+     * AMD:               EAX, EBX, ECX - reserved
+     *                    EDX: Advanced Power Management Information
+     * Intel:             Reserved
+     */
+    if (pCPUM->aGuestCpuIdExt[0].eax >= UINT32_C(0x80000007))
+    {
+        Assert(pVM->cpum.s.enmCPUVendor != CPUMCPUVENDOR_INVALID);
+
+        pCPUM->aGuestCpuIdExt[7].eax = pCPUM->aGuestCpuIdExt[7].ebx = pCPUM->aGuestCpuIdExt[7].ecx = 0;
+
+        if (pVM->cpum.s.enmCPUVendor == CPUMCPUVENDOR_AMD)
+        {
+            /* Only expose the TSC invariant capability bit to the guest. */
+            pCPUM->aGuestCpuIdExt[7].edx    &= 0
+                                            //| X86_CPUID_AMD_ADVPOWER_EDX_TS
+                                            //| X86_CPUID_AMD_ADVPOWER_EDX_FID
+                                            //| X86_CPUID_AMD_ADVPOWER_EDX_VID
+                                            //| X86_CPUID_AMD_ADVPOWER_EDX_TTP
+                                            //| X86_CPUID_AMD_ADVPOWER_EDX_TM
+                                            //| X86_CPUID_AMD_ADVPOWER_EDX_STC
+                                            //| X86_CPUID_AMD_ADVPOWER_EDX_MC
+                                            //| X86_CPUID_AMD_ADVPOWER_EDX_HWPSTATE
+                                            | X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR
+                                            | 0;
+        }
+        else
+            pCPUM->aGuestCpuIdExt[7].edx    = 0;
+    }
+
+    /* Cpuid 0x800000008:
+     * AMD:               EBX, EDX - reserved
+     *                    EAX: Virtual/Physical address Size
+     *                    ECX: Number of cores + APICIdCoreIdSize
+     * Intel:             EAX: Virtual/Physical address Size
+     *                    EBX, ECX, EDX - reserved
+     */
+    if (pCPUM->aGuestCpuIdExt[0].eax >= UINT32_C(0x80000008))
+    {
+        /* Only expose the virtual and physical address sizes to the guest. (EAX completely) */
+        pCPUM->aGuestCpuIdExt[8].ebx = pCPUM->aGuestCpuIdExt[8].edx = 0;  /* reserved */
+        /* Set APICIdCoreIdSize to zero (use legacy method to determine the number of cores per cpu)
+         * NC (0-7) Number of cores; 0 equals 1 core */
+        pCPUM->aGuestCpuIdExt[8].ecx = 0;
+    }
+
     /*
      * Limit it the number of entries and fill the remaining with the defaults.
@@ -375 +421 @@
         pCPUM->aGuestCpuIdStd[i] = pCPUM->GuestCpuIdDef;
 
-    if (pCPUM->aGuestCpuIdExt[0].eax > UINT32_C(0x80000006))
-        pCPUM->aGuestCpuIdExt[0].eax = UINT32_C(0x80000006);
+    if (pCPUM->aGuestCpuIdExt[0].eax > UINT32_C(0x80000008))
+        pCPUM->aGuestCpuIdExt[0].eax = UINT32_C(0x80000008);
     for (i = pCPUM->aGuestCpuIdExt[0].eax >= UINT32_C(0x80000000)
            ? pCPUM->aGuestCpuIdExt[0].eax - UINT32_C(0x80000000) + 1

trunk/src/VBox/VMM/TM.cpp

@@ -567 +567 @@
 
                 ASMCpuId(0x80000007, &uEAX, &uEBX, &uECX, &uEDX);
-                if (   (uEDX & RT_BIT(8)) /* TscInvariant */
+                if (   (uEDX & X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR) /* TscInvariant */
                     && pGip->u32Mode == SUPGIPMODE_SYNC_TSC /* no fixed tsc if the gip timer is in async mode */)
                     return true;