Changeset 105670 in vbox for trunk/src/VBox/Devices/EFI/FirmwareNew/MdeModulePkg/Bus
- Timestamp:
- Aug 14, 2024 1:16:30 PM (8 months ago)
- svn:sync-xref-src-repo-rev:
- 164367
- Location:
- trunk/src/VBox/Devices/EFI/FirmwareNew
- Files:
-
- 29 added
- 35 edited
Legend:
- Unmodified
- Added
- Removed
-
trunk/src/VBox/Devices/EFI/FirmwareNew
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trunk/src/VBox/Devices/EFI/FirmwareNew/MdeModulePkg/Bus/Ata/AtaBusDxe/AtaBus.c
r99404 r105670 1484 1484 1485 1485 @param This Indicates a pointer to the calling context. 1486 @param MediaId ID of the medium to receive data from. 1486 @param MediaId ID of the medium to receive data from. If there is no 1487 block IO protocol supported by the physical device, the 1488 value of MediaId is undefined. 1487 1489 @param Timeout The timeout, in 100ns units, to use for the execution 1488 1490 of the security protocol command. A Timeout value of 0 … … 1601 1603 1602 1604 @param This Indicates a pointer to the calling context. 1603 @param MediaId ID of the medium to receive data from. 1605 @param MediaId ID of the medium to receive data from. If there is no 1606 block IO protocol supported by the physical device, the 1607 value of MediaId is undefined. 1604 1608 @param Timeout The timeout, in 100ns units, to use for the execution 1605 1609 of the security protocol command. A Timeout value of 0 -
trunk/src/VBox/Devices/EFI/FirmwareNew/MdeModulePkg/Bus/Ata/AtaBusDxe/AtaBus.h
r101291 r105670 928 928 929 929 @param This Indicates a pointer to the calling context. 930 @param MediaId ID of the medium to receive data from. 930 @param MediaId ID of the medium to receive data from. If there is no 931 block IO protocol supported by the physical device, the 932 value of MediaId is undefined. 931 933 @param Timeout The timeout, in 100ns units, to use for the execution 932 934 of the security protocol command. A Timeout value of 0 … … 1008 1010 1009 1011 @param This Indicates a pointer to the calling context. 1010 @param MediaId ID of the medium to receive data from. 1012 @param MediaId ID of the medium to receive data from. If there is no 1013 block IO protocol supported by the physical device, the 1014 value of MediaId is undefined. 1011 1015 @param Timeout The timeout, in 100ns units, to use for the execution 1012 1016 of the security protocol command. A Timeout value of 0 -
trunk/src/VBox/Devices/EFI/FirmwareNew/MdeModulePkg/Bus/Ata/AtaBusDxe/AtaPassThruExecute.c
r101291 r105670 363 363 // 364 364 if ((PhyLogicSectorSupport & BIT12) != 0) { 365 BlockMedia->BlockSize = (UINT32)((( IdentifyData->logic_sector_size_hi << 16) | IdentifyData->logic_sector_size_lo) * sizeof (UINT16));365 BlockMedia->BlockSize = (UINT32)(((UINT32)(IdentifyData->logic_sector_size_hi << 16) | IdentifyData->logic_sector_size_lo) * sizeof (UINT16)); 366 366 } 367 367 -
trunk/src/VBox/Devices/EFI/FirmwareNew/MdeModulePkg/Bus/Isa/Ps2KeyboardDxe/Ps2KbdTextIn.c
r99404 r105670 259 259 @param Key The output buffer for key value 260 260 261 @retval EFI_SUCCESS success to read key stroke 261 @retval EFI_SUCCESS success to read key stroke 262 @retval EFI_UNSUPPORTED The device does not support the ability to read keystroke data. 262 263 **/ 263 264 EFI_STATUS … … 434 435 hardware errors. 435 436 @retval EFI_INVALID_PARAMETER KeyData is NULL. 437 @retval EFI_UNSUPPORTED The device does not support the ability to read keystroke data. 436 438 437 439 **/ -
trunk/src/VBox/Devices/EFI/FirmwareNew/MdeModulePkg/Bus/Isa/Ps2KeyboardDxe/Ps2Keyboard.h
r99404 r105670 339 339 340 340 @retval EFI_SUCCESS success to read key stroke 341 @retval EFI_UNSUPPORTED The device does not support the ability to read keystroke data. 341 342 **/ 342 343 EFI_STATUS … … 442 443 hardware errors. 443 444 @retval EFI_INVALID_PARAMETER - KeyData is NULL. 445 @retval EFI_UNSUPPORTED - The device does not support the ability to read 446 keystroke data. 444 447 445 448 **/ -
trunk/src/VBox/Devices/EFI/FirmwareNew/MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressBlockIo.c
r101291 r105670 1700 1700 1701 1701 @param This Indicates a pointer to the calling context. 1702 @param MediaId ID of the medium to receive data from. 1702 @param MediaId ID of the medium to receive data from. If there is no 1703 block IO protocol supported by the physical device, the 1704 value of MediaId is undefined. 1703 1705 @param Timeout The timeout, in 100ns units, to use for the execution 1704 1706 of the security protocol command. A Timeout value of 0 … … 1813 1815 1814 1816 @param This Indicates a pointer to the calling context. 1815 @param MediaId ID of the medium to receive data from. 1817 @param MediaId ID of the medium to receive data from. If there is no 1818 block IO protocol supported by the physical device, the 1819 value of MediaId is undefined. 1816 1820 @param Timeout The timeout, in 100ns units, to use for the execution 1817 1821 of the security protocol command. A Timeout value of 0 -
trunk/src/VBox/Devices/EFI/FirmwareNew/MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressBlockIo.h
r99404 r105670 290 290 291 291 @param This Indicates a pointer to the calling context. 292 @param MediaId ID of the medium to receive data from. 292 @param MediaId ID of the medium to receive data from. If there is no 293 block IO protocol supported by the physical device, the 294 value of MediaId is undefined. 293 295 @param Timeout The timeout, in 100ns units, to use for the execution 294 296 of the security protocol command. A Timeout value of 0 … … 370 372 371 373 @param This Indicates a pointer to the calling context. 372 @param MediaId ID of the medium to receive data from. 374 @param MediaId ID of the medium to receive data from. If there is no 375 block IO protocol supported by the physical device, the 376 value of MediaId is undefined. 373 377 @param Timeout The timeout, in 100ns units, to use for the execution 374 378 of the security protocol command. A Timeout value of 0 -
trunk/src/VBox/Devices/EFI/FirmwareNew/MdeModulePkg/Bus/Pci/NvmExpressPei/NvmExpressPeiS3.c
r99404 r105670 63 63 } 64 64 65 if (S3InitDevices == NULL) {66 return Skip;67 }68 69 65 // 70 66 // Only need to initialize the controllers that exist in the device list. -
trunk/src/VBox/Devices/EFI/FirmwareNew/MdeModulePkg/Bus/Pci/PciBusDxe/PciIo.c
r101291 r105670 1025 1025 } 1026 1026 1027 mIoMmuProtocol->SetAttribute (1028 mIoMmuProtocol,1029 PciIoDevice->Handle,1030 *Mapping,1031 IoMmuAttribute1032 );1027 Status = mIoMmuProtocol->SetAttribute ( 1028 mIoMmuProtocol, 1029 PciIoDevice->Handle, 1030 *Mapping, 1031 IoMmuAttribute 1032 ); 1033 1033 } 1034 1034 } -
trunk/src/VBox/Devices/EFI/FirmwareNew/MdeModulePkg/Bus/Pci/PciBusDxe/PciOptionRomSupport.c
r99404 r105670 507 507 RomImageSize = RomImageSize + RomPcir->ImageLength * 512; 508 508 RomBarOffset = RomBarOffset + RomPcir->ImageLength * 512; 509 } while (((Indicator & 0x80) == 0x00) && ((RomBarOffset - RomBar) < RomSize) );509 } while (((Indicator & 0x80) == 0x00) && ((RomBarOffset - RomBar) < RomSize) && (RomImageSize > 0)); 510 510 511 511 // … … 513 513 // of the legacy length and the PCIR Image Length 514 514 // 515 if ( CodeType == PCI_CODE_TYPE_PCAT_IMAGE) {515 if ((RomImageSize > 0) && (CodeType == PCI_CODE_TYPE_PCAT_IMAGE)) { 516 516 RomImageSize = MAX (RomImageSize, LegacyImageLength); 517 517 } -
trunk/src/VBox/Devices/EFI/FirmwareNew/MdeModulePkg/Bus/Pci/UhciDxe/UhciSched.c
r99404 r105670 198 198 199 199 /** 200 Convert the poll rate to the maxi um 2^n that is smaller200 Convert the poll rate to the maximum 2^n that is smaller 201 201 than Interval. 202 202 … … 214 214 215 215 ASSERT (Interval != 0); 216 217 // 218 // To safeguard RELEASE mode wherein ASSERT is effectively not there, 219 // if inadvertently Interval is still 0 here, treat it the same as 1. 220 // 221 if (Interval == 0) { 222 Interval = 1; 223 } 216 224 217 225 // -
trunk/src/VBox/Devices/EFI/FirmwareNew/MdeModulePkg/Bus/Pci/UhciDxe/UsbHcMem.c
r99404 r105670 251 251 252 252 ASSERT ((Block != NULL)); 253 254 if (Block == NULL) { 255 return 0; 256 } 257 253 258 // 254 259 // calculate the pci memory address for host memory address. … … 537 542 ASSERT (Block != NULL); 538 543 544 if (Block == NULL) { 545 return; 546 } 547 539 548 // 540 549 // Release the current memory block if it is empty and not the head -
trunk/src/VBox/Devices/EFI/FirmwareNew/MdeModulePkg/Bus/Pci/XhciDxe/UsbHcMem.c
r99404 r105670 227 227 @param Mem The pointer to host memory. 228 228 @param Size The size of the memory region. 229 @param Alignment Alignment the size to USBHC_MEM_UNIT bytes. 229 230 230 231 @return The pci memory address … … 235 236 IN USBHC_MEM_POOL *Pool, 236 237 IN VOID *Mem, 237 IN UINTN Size 238 IN UINTN Size, 239 IN BOOLEAN Alignment 238 240 ) 239 241 { … … 244 246 UINTN Offset; 245 247 246 Head = Pool->Head; 247 AllocSize = USBHC_MEM_ROUND (Size); 248 Head = Pool->Head; 249 if (Alignment) { 250 AllocSize = USBHC_MEM_ROUND (Size); 251 } else { 252 AllocSize = Size; 253 } 248 254 249 255 if (Mem == NULL) { … … 276 282 @param Mem The pointer to pci memory. 277 283 @param Size The size of the memory region. 284 @param Alignment Alignment the size to USBHC_MEM_UNIT bytes. 278 285 279 286 @return The host memory address … … 284 291 IN USBHC_MEM_POOL *Pool, 285 292 IN VOID *Mem, 286 IN UINTN Size 293 IN UINTN Size, 294 IN BOOLEAN Alignment 287 295 ) 288 296 { … … 293 301 UINTN Offset; 294 302 295 Head = Pool->Head; 296 AllocSize = USBHC_MEM_ROUND (Size); 303 Head = Pool->Head; 304 if (Alignment) { 305 AllocSize = USBHC_MEM_ROUND (Size); 306 } else { 307 AllocSize = Size; 308 } 297 309 298 310 if (Mem == NULL) { -
trunk/src/VBox/Devices/EFI/FirmwareNew/MdeModulePkg/Bus/Pci/XhciDxe/UsbHcMem.h
r99404 r105670 130 130 @param Mem The pointer to host memory. 131 131 @param Size The size of the memory region. 132 @param Alignment Alignment the size to USBHC_MEM_UNIT bytes. 132 133 133 134 @return The pci memory address … … 138 139 IN USBHC_MEM_POOL *Pool, 139 140 IN VOID *Mem, 140 IN UINTN Size 141 IN UINTN Size, 142 IN BOOLEAN Alignment 141 143 ); 142 144 … … 147 149 @param Mem The pointer to pci memory. 148 150 @param Size The size of the memory region. 151 @param Alignment Alignment the size to USBHC_MEM_UNIT bytes. 149 152 150 153 @return The host memory address … … 155 158 IN USBHC_MEM_POOL *Pool, 156 159 IN VOID *Mem, 157 IN UINTN Size 160 IN UINTN Size, 161 IN BOOLEAN Alignment 158 162 ); 159 163 -
trunk/src/VBox/Devices/EFI/FirmwareNew/MdeModulePkg/Bus/Pci/XhciDxe/Xhci.c
r101291 r105670 2 2 The XHCI controller driver. 3 3 4 Copyright (c) 2011 - 2022, Intel Corporation. All rights reserved.<BR> 4 (C) Copyright 2023 Hewlett Packard Enterprise Development LP<BR> 5 Copyright (c) 2011 - 2023, Intel Corporation. All rights reserved.<BR> 5 6 SPDX-License-Identifier: BSD-2-Clause-Patent 6 7 … … 85 86 0x0 86 87 }; 88 89 static UINT64 mXhciPerformanceCounterStartValue; 90 static UINT64 mXhciPerformanceCounterEndValue; 91 static UINT64 mXhciPerformanceCounterFrequency; 92 static BOOLEAN mXhciPerformanceCounterValuesCached = FALSE; 87 93 88 94 /** … … 820 826 *DataLength = Urb->Completed; 821 827 822 if ((*TransferResult == EFI_USB_ERR_STALL) || (*TransferResult == EFI_USB_ERR_BABBLE)) { 828 // 829 // Based on XHCI spec 4.8.3, software should do the reset endpoint while USB Transaction occur. 830 // 831 if ((*TransferResult == EFI_USB_ERR_STALL) || (*TransferResult == EFI_USB_ERR_BABBLE) || (*TransferResult == EDKII_USB_ERR_TRANSACTION)) { 823 832 ASSERT (Status == EFI_DEVICE_ERROR); 824 833 RecoveryStatus = XhcRecoverHaltedEndpoint (Xhc, Urb); … … 2295 2304 return EFI_SUCCESS; 2296 2305 } 2306 2307 /** 2308 Converts a time in nanoseconds to a performance counter tick count. 2309 2310 @param Time The time in nanoseconds to be converted to performance counter ticks. 2311 @return Time in nanoseconds converted to ticks. 2312 **/ 2313 UINT64 2314 XhcConvertTimeToTicks ( 2315 IN UINT64 Time 2316 ) 2317 { 2318 UINT64 Ticks; 2319 UINT64 Remainder; 2320 UINT64 Divisor; 2321 UINTN Shift; 2322 2323 // Cache the return values to avoid repeated calls to GetPerformanceCounterProperties () 2324 if (!mXhciPerformanceCounterValuesCached) { 2325 mXhciPerformanceCounterFrequency = GetPerformanceCounterProperties ( 2326 &mXhciPerformanceCounterStartValue, 2327 &mXhciPerformanceCounterEndValue 2328 ); 2329 2330 mXhciPerformanceCounterValuesCached = TRUE; 2331 } 2332 2333 // Prevent returning a tick value of 0, unless Time is already 0 2334 if (0 == mXhciPerformanceCounterFrequency) { 2335 return Time; 2336 } 2337 2338 // Nanoseconds per second 2339 Divisor = 1000000000; 2340 2341 // 2342 // Frequency 2343 // Ticks = ------------- x Time 2344 // 1,000,000,000 2345 // 2346 Ticks = MultU64x64 ( 2347 DivU64x64Remainder ( 2348 mXhciPerformanceCounterFrequency, 2349 Divisor, 2350 &Remainder 2351 ), 2352 Time 2353 ); 2354 2355 // 2356 // Ensure (Remainder * Time) will not overflow 64-bit. 2357 // 2358 // HighBitSet64 (Remainder) + 1 + HighBitSet64 (Time) + 1 <= 64 2359 // 2360 Shift = MAX (0, HighBitSet64 (Remainder) + HighBitSet64 (Time) - 62); 2361 Remainder = RShiftU64 (Remainder, (UINTN)Shift); 2362 Divisor = RShiftU64 (Divisor, (UINTN)Shift); 2363 Ticks += DivU64x64Remainder (MultU64x64 (Remainder, Time), Divisor, NULL); 2364 2365 return Ticks; 2366 } 2367 2368 /** 2369 Computes and returns the elapsed ticks since PreviousTick. The 2370 value of PreviousTick is overwritten with the current performance 2371 counter value. 2372 2373 @param PreviousTick Pointer to PreviousTick count. 2374 @return The elapsed ticks since PreviousCount. PreviousCount is 2375 overwritten with the current performance counter value. 2376 **/ 2377 UINT64 2378 XhcGetElapsedTicks ( 2379 IN OUT UINT64 *PreviousTick 2380 ) 2381 { 2382 UINT64 CurrentTick; 2383 UINT64 Delta; 2384 2385 CurrentTick = GetPerformanceCounter (); 2386 2387 // 2388 // Determine if the counter is counting up or down 2389 // 2390 if (mXhciPerformanceCounterStartValue < mXhciPerformanceCounterEndValue) { 2391 // 2392 // Counter counts upwards, check for an overflow condition 2393 // 2394 if (*PreviousTick > CurrentTick) { 2395 Delta = (mXhciPerformanceCounterEndValue - *PreviousTick) + CurrentTick; 2396 } else { 2397 Delta = CurrentTick - *PreviousTick; 2398 } 2399 } else { 2400 // 2401 // Counter counts downwards, check for an underflow condition 2402 // 2403 if (*PreviousTick < CurrentTick) { 2404 Delta = (mXhciPerformanceCounterStartValue - CurrentTick) + *PreviousTick; 2405 } else { 2406 Delta = *PreviousTick - CurrentTick; 2407 } 2408 } 2409 2410 // 2411 // Set PreviousTick to CurrentTick 2412 // 2413 *PreviousTick = CurrentTick; 2414 2415 return Delta; 2416 } -
trunk/src/VBox/Devices/EFI/FirmwareNew/MdeModulePkg/Bus/Pci/XhciDxe/Xhci.h
r99404 r105670 3 3 Provides some data structure definitions used by the XHCI host controller driver. 4 4 5 (C) Copyright 2023 Hewlett Packard Enterprise Development LP<BR> 5 6 Copyright (c) 2011 - 2017, Intel Corporation. All rights reserved.<BR> 6 7 Copyright (c) Microsoft Corporation.<BR> … … 27 28 #include <Library/DebugLib.h> 28 29 #include <Library/ReportStatusCodeLib.h> 30 #include <Library/TimerLib.h> 31 #include <Library/PcdLib.h> 29 32 30 33 #include <IndustryStandard/Pci.h> … … 37 40 #include "ComponentName.h" 38 41 #include "UsbHcMem.h" 42 43 // 44 // Converts a count from microseconds to nanoseconds 45 // 46 #define XHC_MICROSECOND_TO_NANOSECOND(Time) (MultU64x32((Time), 1000)) 39 47 40 48 // … … 721 729 ); 722 730 731 /** 732 Converts a time in nanoseconds to a performance counter tick count. 733 734 @param Time The time in nanoseconds to be converted to performance counter ticks. 735 @return Time in nanoseconds converted to ticks. 736 **/ 737 UINT64 738 XhcConvertTimeToTicks ( 739 UINT64 Time 740 ); 741 742 /** 743 Computes and returns the elapsed ticks since PreviousTick. The 744 value of PreviousTick is overwritten with the current performance 745 counter value. 746 747 @param PreviousTick Pointer to PreviousTick count. 748 @return The elapsed ticks since PreviousCount. PreviousCount is 749 overwritten with the current performance counter value. 750 **/ 751 UINT64 752 XhcGetElapsedTicks ( 753 IN OUT UINT64 *PreviousTick 754 ); 755 723 756 #endif -
trunk/src/VBox/Devices/EFI/FirmwareNew/MdeModulePkg/Bus/Pci/XhciDxe/XhciDxe.inf
r80721 r105670 4 4 # Control, Bulk, Interrupt and Isochronous requests to those attached usb LS/FS/HS/SS devices. 5 5 # 6 # (C) Copyright 2023 Hewlett Packard Enterprise Development LP<BR> 6 7 # Copyright (c) 2011 - 2018, Intel Corporation. All rights reserved.<BR> 7 8 # … … 45 46 [Packages] 46 47 MdePkg/MdePkg.dec 48 MdeModulePkg/MdeModulePkg.dec 47 49 48 50 [LibraryClasses] … … 55 57 DebugLib 56 58 ReportStatusCodeLib 59 TimerLib 60 PcdLib 57 61 58 62 [Guids] … … 63 67 gEfiUsb2HcProtocolGuid ## BY_START 64 68 69 [Pcd] 70 gEfiMdeModulePkgTokenSpaceGuid.PcdDelayXhciHCReset ## CONSUMES 71 65 72 # [Event] 66 73 # EVENT_TYPE_PERIODIC_TIMER ## CONSUMES -
trunk/src/VBox/Devices/EFI/FirmwareNew/MdeModulePkg/Bus/Pci/XhciDxe/XhciReg.c
r99404 r105670 3 3 The XHCI register operation routines. 4 4 5 (C) Copyright 2023 Hewlett Packard Enterprise Development LP<BR> 5 6 Copyright (c) 2011 - 2017, Intel Corporation. All rights reserved.<BR> 6 7 SPDX-License-Identifier: BSD-2-Clause-Patent … … 418 419 to become set (or clear). 419 420 420 @param Xhc The XHCI Instance. 421 @param Offset The offset of the operation register. 422 @param Bit The bit of the register to wait for. 423 @param WaitToSet Wait the bit to set or clear. 424 @param Timeout The time to wait before abort (in millisecond, ms). 425 426 @retval EFI_SUCCESS The bit successfully changed by host controller. 427 @retval EFI_TIMEOUT The time out occurred. 428 @retval EFI_OUT_OF_RESOURCES Memory for the timer event could not be allocated. 421 @param Xhc The XHCI Instance. 422 @param Offset The offset of the operation register. 423 @param Bit The bit of the register to wait for. 424 @param WaitToSet Wait the bit to set or clear. 425 @param Timeout The time to wait before abort (in millisecond, ms). 426 427 @retval EFI_SUCCESS The bit successfully changed by host controller. 428 @retval EFI_TIMEOUT The time out occurred. 429 429 430 430 **/ … … 438 438 ) 439 439 { 440 EFI_STATUS Status;441 EFI_EVENT TimeoutEvent;442 443 TimeoutEvent = NULL;440 UINT64 TimeoutTicks; 441 UINT64 ElapsedTicks; 442 UINT64 TicksDelta; 443 UINT64 CurrentTick; 444 444 445 445 if (Timeout == 0) { … … 447 447 } 448 448 449 Status = gBS->CreateEvent ( 450 EVT_TIMER, 451 TPL_CALLBACK, 452 NULL, 453 NULL, 454 &TimeoutEvent 455 ); 456 457 if (EFI_ERROR (Status)) { 458 goto DONE; 459 } 460 461 Status = gBS->SetTimer ( 462 TimeoutEvent, 463 TimerRelative, 464 EFI_TIMER_PERIOD_MILLISECONDS (Timeout) 465 ); 466 467 if (EFI_ERROR (Status)) { 468 goto DONE; 469 } 470 449 TimeoutTicks = XhcConvertTimeToTicks (XHC_MICROSECOND_TO_NANOSECOND (Timeout * XHC_1_MILLISECOND)); 450 ElapsedTicks = 0; 451 CurrentTick = GetPerformanceCounter (); 471 452 do { 472 453 if (XHC_REG_BIT_IS_SET (Xhc, Offset, Bit) == WaitToSet) { 473 Status = EFI_SUCCESS; 474 goto DONE; 454 return EFI_SUCCESS; 475 455 } 476 456 477 457 gBS->Stall (XHC_1_MICROSECOND); 478 } while (EFI_ERROR (gBS->CheckEvent (TimeoutEvent)));479 480 Status = EFI_TIMEOUT;481 482 DONE: 483 if (TimeoutEvent != NULL) { 484 gBS->CloseEvent (TimeoutEvent);485 } 486 487 return Status;458 TicksDelta = XhcGetElapsedTicks (&CurrentTick); 459 // Ensure that ElapsedTicks is always incremented to avoid indefinite hangs 460 if (TicksDelta == 0) { 461 TicksDelta = XhcConvertTimeToTicks (XHC_MICROSECOND_TO_NANOSECOND (XHC_1_MICROSECOND)); 462 } 463 464 ElapsedTicks += TicksDelta; 465 } while (ElapsedTicks < TimeoutTicks); 466 467 return EFI_TIMEOUT; 488 468 } 489 469 … … 885 865 // The below is a workaround to solve such problem. 886 866 // 887 gBS->Stall ( XHC_1_MILLISECOND);867 gBS->Stall (PcdGet16 (PcdDelayXhciHCReset)); 888 868 Status = XhcWaitOpRegBit (Xhc, XHC_USBCMD_OFFSET, XHC_USBCMD_RESET, FALSE, Timeout); 889 869 -
trunk/src/VBox/Devices/EFI/FirmwareNew/MdeModulePkg/Bus/Pci/XhciDxe/XhciSched.c
r101291 r105670 3 3 XHCI transfer scheduling routines. 4 4 5 (C) Copyright 2023 Hewlett Packard Enterprise Development LP<BR> 5 6 Copyright (c) 2011 - 2020, Intel Corporation. All rights reserved.<BR> 6 7 Copyright (c) Microsoft Corporation.<BR> … … 589 590 // So divide it to two 32-bytes width register access. 590 591 // 591 DcbaaPhy = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Dcbaa, Entries );592 DcbaaPhy = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Dcbaa, Entries, TRUE); 592 593 XhcWriteOpReg (Xhc, XHC_DCBAAP_OFFSET, XHC_LOW_32BIT (DcbaaPhy)); 593 594 XhcWriteOpReg (Xhc, XHC_DCBAAP_OFFSET + 4, XHC_HIGH_32BIT (DcbaaPhy)); … … 608 609 // 609 610 CmdRing = (UINT64)(UINTN)Xhc->CmdRing.RingSeg0; 610 CmdRingPhy = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, (VOID *)(UINTN)CmdRing, sizeof (TRB_TEMPLATE) * CMD_RING_TRB_NUMBER );611 CmdRingPhy = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, (VOID *)(UINTN)CmdRing, sizeof (TRB_TEMPLATE) * CMD_RING_TRB_NUMBER, TRUE); 611 612 ASSERT ((CmdRingPhy & 0x3F) == 0); 612 613 CmdRingPhy |= XHC_CRCR_RCS; … … 810 811 EventRing->EventRingEnqueue = (TRB_TEMPLATE *)EventRing->EventRingSeg0; 811 812 812 DequeuePhy = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Buf, Size );813 DequeuePhy = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Buf, Size, TRUE); 813 814 814 815 // … … 830 831 ERSTBase->RingTrbSize = EVENT_RING_TRB_NUMBER; 831 832 832 ERSTPhy = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, ERSTBase, Size );833 ERSTPhy = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, ERSTBase, Size, TRUE); 833 834 834 835 // … … 914 915 EndTrb = (LINK_TRB *)((UINTN)Buf + sizeof (TRB_TEMPLATE) * (TrbNum - 1)); 915 916 EndTrb->Type = TRB_TYPE_LINK; 916 PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Buf, sizeof (TRB_TEMPLATE) * TrbNum );917 PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Buf, sizeof (TRB_TEMPLATE) * TrbNum, TRUE); 917 918 EndTrb->PtrLo = XHC_LOW_32BIT (PhyAddr); 918 919 EndTrb->PtrHi = XHC_HIGH_32BIT (PhyAddr); … … 1046 1047 LinkTrb = (LINK_TRB *)CheckedTrb; 1047 1048 PhyAddr = (EFI_PHYSICAL_ADDRESS)(LinkTrb->PtrLo | LShiftU64 ((UINT64)LinkTrb->PtrHi, 32)); 1048 CheckedTrb = (TRB_TEMPLATE *)(UINTN)UsbHcGetHostAddrForPciAddr (Xhc->MemPool, (VOID *)(UINTN)PhyAddr, sizeof (TRB_TEMPLATE) );1049 CheckedTrb = (TRB_TEMPLATE *)(UINTN)UsbHcGetHostAddrForPciAddr (Xhc->MemPool, (VOID *)(UINTN)PhyAddr, sizeof (TRB_TEMPLATE), FALSE); 1049 1050 ASSERT (CheckedTrb == Urb->Ring->RingSeg0); 1050 1051 } … … 1155 1156 // 1156 1157 PhyAddr = (EFI_PHYSICAL_ADDRESS)(EvtTrb->TRBPtrLo | LShiftU64 ((UINT64)EvtTrb->TRBPtrHi, 32)); 1157 TRBPtr = (TRB_TEMPLATE *)(UINTN)UsbHcGetHostAddrForPciAddr (Xhc->MemPool, (VOID *)(UINTN)PhyAddr, sizeof (TRB_TEMPLATE) );1158 TRBPtr = (TRB_TEMPLATE *)(UINTN)UsbHcGetHostAddrForPciAddr (Xhc->MemPool, (VOID *)(UINTN)PhyAddr, sizeof (TRB_TEMPLATE), FALSE); 1158 1159 1159 1160 // … … 1192 1193 goto EXIT; 1193 1194 1195 // 1196 // Based on XHCI spec 4.8.3, software should do the reset endpoint while USB Transaction occur. 1197 // 1194 1198 case TRB_COMPLETION_USB_TRANSACTION_ERROR: 1195 CheckedUrb->Result |= E FI_USB_ERR_TIMEOUT;1199 CheckedUrb->Result |= EDKII_USB_ERR_TRANSACTION; 1196 1200 CheckedUrb->Finished = TRUE; 1197 1201 DEBUG ((DEBUG_ERROR, "XhcCheckUrbResult: TRANSACTION_ERROR! Completecode = %x\n", EvtTrb->Completecode)); … … 1260 1264 XhcDequeue = (UINT64)(LShiftU64 ((UINT64)High, 32) | Low); 1261 1265 1262 PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Xhc->EventRing.EventRingDequeue, sizeof (TRB_TEMPLATE) );1266 PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Xhc->EventRing.EventRingDequeue, sizeof (TRB_TEMPLATE), FALSE); 1263 1267 1264 1268 if ((XhcDequeue & (~0x0F)) != (PhyAddr & (~0x0F))) { … … 1277 1281 Execute the transfer by polling the URB. This is a synchronous operation. 1278 1282 1279 @param Xhc The XHCI Instance. 1280 @param CmdTransfer The executed URB is for cmd transfer or not. 1281 @param Urb The URB to execute. 1282 @param Timeout The time to wait before abort, in millisecond. 1283 1284 @return EFI_DEVICE_ERROR The transfer failed due to transfer error. 1285 @return EFI_TIMEOUT The transfer failed due to time out. 1286 @return EFI_SUCCESS The transfer finished OK. 1287 @retval EFI_OUT_OF_RESOURCES Memory for the timer event could not be allocated. 1283 @param Xhc The XHCI Instance. 1284 @param CmdTransfer The executed URB is for cmd transfer or not. 1285 @param Urb The URB to execute. 1286 @param Timeout The time to wait before abort, in millisecond. 1287 1288 @return EFI_DEVICE_ERROR The transfer failed due to transfer error. 1289 @return EFI_TIMEOUT The transfer failed due to time out. 1290 @return EFI_SUCCESS The transfer finished OK. 1288 1291 1289 1292 **/ … … 1300 1303 UINT8 Dci; 1301 1304 BOOLEAN Finished; 1302 EFI_EVENT TimeoutEvent; 1305 UINT64 TimeoutTicks; 1306 UINT64 ElapsedTicks; 1307 UINT64 TicksDelta; 1308 UINT64 CurrentTick; 1303 1309 BOOLEAN IndefiniteTimeout; 1304 1310 1305 1311 Status = EFI_SUCCESS; 1306 1312 Finished = FALSE; 1307 TimeoutEvent = NULL;1308 1313 IndefiniteTimeout = FALSE; 1309 1314 … … 1323 1328 if (Timeout == 0) { 1324 1329 IndefiniteTimeout = TRUE; 1325 goto RINGDOORBELL; 1326 } 1327 1328 Status = gBS->CreateEvent ( 1329 EVT_TIMER, 1330 TPL_CALLBACK, 1331 NULL, 1332 NULL, 1333 &TimeoutEvent 1334 ); 1335 1336 if (EFI_ERROR (Status)) { 1337 goto DONE; 1338 } 1339 1340 Status = gBS->SetTimer ( 1341 TimeoutEvent, 1342 TimerRelative, 1343 EFI_TIMER_PERIOD_MILLISECONDS (Timeout) 1344 ); 1345 1346 if (EFI_ERROR (Status)) { 1347 goto DONE; 1348 } 1349 1350 RINGDOORBELL: 1330 } 1331 1351 1332 XhcRingDoorBell (Xhc, SlotId, Dci); 1333 1334 TimeoutTicks = XhcConvertTimeToTicks ( 1335 XHC_MICROSECOND_TO_NANOSECOND ( 1336 Timeout * XHC_1_MILLISECOND 1337 ) 1338 ); 1339 ElapsedTicks = 0; 1340 CurrentTick = GetPerformanceCounter (); 1352 1341 1353 1342 do { … … 1358 1347 1359 1348 gBS->Stall (XHC_1_MICROSECOND); 1360 } while (IndefiniteTimeout || EFI_ERROR (gBS->CheckEvent (TimeoutEvent))); 1361 1362 DONE: 1363 if (EFI_ERROR (Status)) { 1364 Urb->Result = EFI_USB_ERR_NOTEXECUTE; 1365 } else if (!Finished) { 1349 TicksDelta = XhcGetElapsedTicks (&CurrentTick); 1350 // Ensure that ElapsedTicks is always incremented to avoid indefinite hangs 1351 if (TicksDelta == 0) { 1352 TicksDelta = XhcConvertTimeToTicks (XHC_MICROSECOND_TO_NANOSECOND (XHC_1_MICROSECOND)); 1353 } 1354 1355 ElapsedTicks += TicksDelta; 1356 } while (IndefiniteTimeout || ElapsedTicks < TimeoutTicks); 1357 1358 if (!Finished) { 1366 1359 Urb->Result = EFI_USB_ERR_TIMEOUT; 1367 1360 Status = EFI_TIMEOUT; 1368 1361 } else if (Urb->Result != EFI_USB_NOERROR) { 1369 1362 Status = EFI_DEVICE_ERROR; 1370 }1371 1372 if (TimeoutEvent != NULL) {1373 gBS->CloseEvent (TimeoutEvent);1374 1363 } 1375 1364 … … 2123 2112 2124 2113 /** 2114 Set Command abort 2115 2116 @param Xhc The XHCI Instance. 2117 @param SlotId The slot id to be disabled. 2118 2119 **/ 2120 VOID 2121 XhcCmdRingCmdAbort ( 2122 IN USB_XHCI_INSTANCE *Xhc, 2123 IN UINT8 SlotId 2124 ) 2125 { 2126 // 2127 // Set XHC_CRCR_CA bit in XHC_CRCR_OFFSET to abort command. 2128 // 2129 DEBUG ((DEBUG_INFO, "Command Ring Control set Command Abort, SlotId: %d\n", SlotId)); 2130 XhcSetOpRegBit (Xhc, XHC_CRCR_OFFSET, XHC_CRCR_CA); 2131 } 2132 2133 /** 2125 2134 Assign and initialize the device slot for a new device. 2126 2135 … … 2281 2290 Xhc->MemPool, 2282 2291 ((TRANSFER_RING *)(UINTN)Xhc->UsbDevContext[SlotId].EndpointTransferRing[0])->RingSeg0, 2283 sizeof (TRB_TEMPLATE) * TR_RING_TRB_NUMBER 2292 sizeof (TRB_TEMPLATE) * TR_RING_TRB_NUMBER, 2293 TRUE 2284 2294 ); 2285 2295 InputContext->EP[0].PtrLo = XHC_LOW_32BIT (PhyAddr) | BIT0; … … 2299 2309 // a pointer to the Output Device Context data structure (6.2.1). 2300 2310 // 2301 PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, OutputContext, sizeof (DEVICE_CONTEXT) );2311 PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, OutputContext, sizeof (DEVICE_CONTEXT), TRUE); 2302 2312 // 2303 2313 // Fill DCBAA with PCI device address … … 2314 2324 gBS->Stall (XHC_RESET_RECOVERY_DELAY); 2315 2325 ZeroMem (&CmdTrbAddr, sizeof (CmdTrbAddr)); 2316 PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Xhc->UsbDevContext[SlotId].InputContext, sizeof (INPUT_CONTEXT) );2326 PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Xhc->UsbDevContext[SlotId].InputContext, sizeof (INPUT_CONTEXT), TRUE); 2317 2327 CmdTrbAddr.PtrLo = XHC_LOW_32BIT (PhyAddr); 2318 2328 CmdTrbAddr.PtrHi = XHC_HIGH_32BIT (PhyAddr); … … 2332 2342 } else { 2333 2343 DEBUG ((DEBUG_ERROR, " Slot %d address not assigned successfully. Status = %r\n", SlotId, Status)); 2344 // 2345 // Software may abort the execution of Address Device Command when command failed 2346 // due to timeout by following XHCI spec. 4.6.1.2. 2347 // 2348 if (Status == EFI_TIMEOUT) { 2349 XhcCmdRingCmdAbort (Xhc, SlotId); 2350 } 2351 2334 2352 XhcDisableSlotCmd (Xhc, SlotId); 2335 2353 } … … 2497 2515 Xhc->MemPool, 2498 2516 ((TRANSFER_RING *)(UINTN)Xhc->UsbDevContext[SlotId].EndpointTransferRing[0])->RingSeg0, 2499 sizeof (TRB_TEMPLATE) * TR_RING_TRB_NUMBER 2517 sizeof (TRB_TEMPLATE) * TR_RING_TRB_NUMBER, 2518 TRUE 2500 2519 ); 2501 2520 InputContext->EP[0].PtrLo = XHC_LOW_32BIT (PhyAddr) | BIT0; … … 2515 2534 // a pointer to the Output Device Context data structure (6.2.1). 2516 2535 // 2517 PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, OutputContext, sizeof (DEVICE_CONTEXT_64) );2536 PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, OutputContext, sizeof (DEVICE_CONTEXT_64), TRUE); 2518 2537 // 2519 2538 // Fill DCBAA with PCI device address … … 2530 2549 gBS->Stall (XHC_RESET_RECOVERY_DELAY); 2531 2550 ZeroMem (&CmdTrbAddr, sizeof (CmdTrbAddr)); 2532 PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Xhc->UsbDevContext[SlotId].InputContext, sizeof (INPUT_CONTEXT_64) );2551 PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Xhc->UsbDevContext[SlotId].InputContext, sizeof (INPUT_CONTEXT_64), TRUE); 2533 2552 CmdTrbAddr.PtrLo = XHC_LOW_32BIT (PhyAddr); 2534 2553 CmdTrbAddr.PtrHi = XHC_HIGH_32BIT (PhyAddr); … … 2548 2567 } else { 2549 2568 DEBUG ((DEBUG_ERROR, " Slot %d address not assigned successfully. Status = %r\n", SlotId, Status)); 2569 // 2570 // Software may abort the execution of Address Device Command when command failed 2571 // due to timeout by following XHCI spec. 4.6.1.2. 2572 // 2573 if (Status == EFI_TIMEOUT) { 2574 XhcCmdRingCmdAbort (Xhc, SlotId); 2575 } 2576 2550 2577 XhcDisableSlotCmd64 (Xhc, SlotId); 2551 2578 } … … 2965 2992 Xhc->MemPool, 2966 2993 ((TRANSFER_RING *)(UINTN)Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1])->RingSeg0, 2967 sizeof (TRB_TEMPLATE) * TR_RING_TRB_NUMBER 2994 sizeof (TRB_TEMPLATE) * TR_RING_TRB_NUMBER, 2995 TRUE 2968 2996 ); 2969 2997 PhyAddr &= ~((EFI_PHYSICAL_ADDRESS)0x0F); … … 3167 3195 Xhc->MemPool, 3168 3196 ((TRANSFER_RING *)(UINTN)Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1])->RingSeg0, 3169 sizeof (TRB_TEMPLATE) * TR_RING_TRB_NUMBER 3197 sizeof (TRB_TEMPLATE) * TR_RING_TRB_NUMBER, 3198 TRUE 3170 3199 ); 3171 3200 PhyAddr &= ~((EFI_PHYSICAL_ADDRESS)0x0F); … … 3249 3278 // 3250 3279 ZeroMem (&CmdTrbCfgEP, sizeof (CmdTrbCfgEP)); 3251 PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, InputContext, sizeof (INPUT_CONTEXT) );3280 PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, InputContext, sizeof (INPUT_CONTEXT), TRUE); 3252 3281 CmdTrbCfgEP.PtrLo = XHC_LOW_32BIT (PhyAddr); 3253 3282 CmdTrbCfgEP.PtrHi = XHC_HIGH_32BIT (PhyAddr); … … 3340 3369 // 3341 3370 ZeroMem (&CmdTrbCfgEP, sizeof (CmdTrbCfgEP)); 3342 PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, InputContext, sizeof (INPUT_CONTEXT_64) );3371 PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, InputContext, sizeof (INPUT_CONTEXT_64), TRUE); 3343 3372 CmdTrbCfgEP.PtrLo = XHC_LOW_32BIT (PhyAddr); 3344 3373 CmdTrbCfgEP.PtrHi = XHC_HIGH_32BIT (PhyAddr); … … 3514 3543 // 3515 3544 ZeroMem (&CmdSetTRDeq, sizeof (CmdSetTRDeq)); 3516 PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Urb->Ring->RingEnqueue, sizeof (CMD_SET_TR_DEQ_POINTER) );3545 PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Urb->Ring->RingEnqueue, sizeof (CMD_SET_TR_DEQ_POINTER), FALSE); 3517 3546 CmdSetTRDeq.PtrLo = XHC_LOW_32BIT (PhyAddr) | Urb->Ring->RingPCS; 3518 3547 CmdSetTRDeq.PtrHi = XHC_HIGH_32BIT (PhyAddr); … … 3714 3743 // 3715 3744 ZeroMem (&CmdTrbCfgEP, sizeof (CmdTrbCfgEP)); 3716 PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, InputContext, sizeof (INPUT_CONTEXT) );3745 PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, InputContext, sizeof (INPUT_CONTEXT), TRUE); 3717 3746 CmdTrbCfgEP.PtrLo = XHC_LOW_32BIT (PhyAddr); 3718 3747 CmdTrbCfgEP.PtrHi = XHC_HIGH_32BIT (PhyAddr); … … 3920 3949 // 3921 3950 ZeroMem (&CmdTrbCfgEP, sizeof (CmdTrbCfgEP)); 3922 PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, InputContext, sizeof (INPUT_CONTEXT_64) );3951 PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, InputContext, sizeof (INPUT_CONTEXT_64), TRUE); 3923 3952 CmdTrbCfgEP.PtrLo = XHC_LOW_32BIT (PhyAddr); 3924 3953 CmdTrbCfgEP.PtrHi = XHC_HIGH_32BIT (PhyAddr); … … 3987 4016 3988 4017 ZeroMem (&CmdTrbEvalu, sizeof (CmdTrbEvalu)); 3989 PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, InputContext, sizeof (INPUT_CONTEXT) );4018 PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, InputContext, sizeof (INPUT_CONTEXT), TRUE); 3990 4019 CmdTrbEvalu.PtrLo = XHC_LOW_32BIT (PhyAddr); 3991 4020 CmdTrbEvalu.PtrHi = XHC_HIGH_32BIT (PhyAddr); … … 4048 4077 4049 4078 ZeroMem (&CmdTrbEvalu, sizeof (CmdTrbEvalu)); 4050 PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, InputContext, sizeof (INPUT_CONTEXT_64) );4079 PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, InputContext, sizeof (INPUT_CONTEXT_64), TRUE); 4051 4080 CmdTrbEvalu.PtrLo = XHC_LOW_32BIT (PhyAddr); 4052 4081 CmdTrbEvalu.PtrHi = XHC_HIGH_32BIT (PhyAddr); … … 4117 4146 4118 4147 ZeroMem (&CmdTrbCfgEP, sizeof (CmdTrbCfgEP)); 4119 PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, InputContext, sizeof (INPUT_CONTEXT) );4148 PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, InputContext, sizeof (INPUT_CONTEXT), TRUE); 4120 4149 CmdTrbCfgEP.PtrLo = XHC_LOW_32BIT (PhyAddr); 4121 4150 CmdTrbCfgEP.PtrHi = XHC_HIGH_32BIT (PhyAddr); … … 4186 4215 4187 4216 ZeroMem (&CmdTrbCfgEP, sizeof (CmdTrbCfgEP)); 4188 PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, InputContext, sizeof (INPUT_CONTEXT_64) );4217 PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, InputContext, sizeof (INPUT_CONTEXT_64), TRUE); 4189 4218 CmdTrbCfgEP.PtrLo = XHC_LOW_32BIT (PhyAddr); 4190 4219 CmdTrbCfgEP.PtrHi = XHC_HIGH_32BIT (PhyAddr); -
trunk/src/VBox/Devices/EFI/FirmwareNew/MdeModulePkg/Bus/Pci/XhciDxe/XhciSched.h
r99404 r105670 80 80 81 81 // 82 // USB Transfer Results Internal Definition 83 // Based on XHCI spec 4.8.3, software should do the reset endpoint while USB Transaction occur. 84 // Add the error code for USB Transaction error since UEFI spec don't have the related definition. 85 // 86 #define EDKII_USB_ERR_TRANSACTION 0x200 87 88 // 82 89 // The topology string used to present usb device location 83 90 // -
trunk/src/VBox/Devices/EFI/FirmwareNew/MdeModulePkg/Bus/Pci/XhciPei/UsbHcMem.c
r99404 r105670 191 191 @param Mem The pointer to host memory. 192 192 @param Size The size of the memory region. 193 @param Alignment Alignment the size to USBHC_MEM_UNIT bytes. 193 194 194 195 @return The pci memory address … … 199 200 IN USBHC_MEM_POOL *Pool, 200 201 IN VOID *Mem, 201 IN UINTN Size 202 IN UINTN Size, 203 IN BOOLEAN Alignment 202 204 ) 203 205 { … … 208 210 UINTN Offset; 209 211 210 Head = Pool->Head; 211 AllocSize = USBHC_MEM_ROUND (Size); 212 Head = Pool->Head; 213 if (Alignment) { 214 AllocSize = USBHC_MEM_ROUND (Size); 215 } else { 216 AllocSize = Size; 217 } 212 218 213 219 if (Mem == NULL) { … … 240 246 @param Mem The pointer to pci memory. 241 247 @param Size The size of the memory region. 248 @param Alignment Alignment the size to USBHC_MEM_UNIT bytes. 242 249 243 250 @return The host memory address … … 248 255 IN USBHC_MEM_POOL *Pool, 249 256 IN VOID *Mem, 250 IN UINTN Size 257 IN UINTN Size, 258 IN BOOLEAN Alignment 251 259 ) 252 260 { … … 257 265 UINTN Offset; 258 266 259 Head = Pool->Head; 260 AllocSize = USBHC_MEM_ROUND (Size); 267 Head = Pool->Head; 268 if (Alignment) { 269 AllocSize = USBHC_MEM_ROUND (Size); 270 } else { 271 AllocSize = Size; 272 } 261 273 262 274 if (Mem == NULL) { -
trunk/src/VBox/Devices/EFI/FirmwareNew/MdeModulePkg/Bus/Pci/XhciPei/UsbHcMem.h
r99404 r105670 69 69 @param Mem The pointer to host memory. 70 70 @param Size The size of the memory region. 71 @param Alignment Alignment the size to USBHC_MEM_UNIT bytes. 71 72 72 73 @return The pci memory address … … 77 78 IN USBHC_MEM_POOL *Pool, 78 79 IN VOID *Mem, 79 IN UINTN Size 80 IN UINTN Size, 81 IN BOOLEAN Alignment 80 82 ); 81 83 … … 86 88 @param Mem The pointer to pci memory. 87 89 @param Size The size of the memory region. 90 @param Alignment Alignment the size to USBHC_MEM_UNIT bytes. 88 91 89 92 @return The host memory address … … 94 97 IN USBHC_MEM_POOL *Pool, 95 98 IN VOID *Mem, 96 IN UINTN Size 99 IN UINTN Size, 100 IN BOOLEAN Alignment 97 101 ); 98 102 -
trunk/src/VBox/Devices/EFI/FirmwareNew/MdeModulePkg/Bus/Pci/XhciPei/XhciSched.c
r99404 r105670 676 676 // 677 677 PhyAddr = (EFI_PHYSICAL_ADDRESS)(EvtTrb->TRBPtrLo | LShiftU64 ((UINT64)EvtTrb->TRBPtrHi, 32)); 678 TRBPtr = (TRB_TEMPLATE *)(UINTN)UsbHcGetHostAddrForPciAddr (Xhc->MemPool, (VOID *)(UINTN)PhyAddr, sizeof (TRB_TEMPLATE) );678 TRBPtr = (TRB_TEMPLATE *)(UINTN)UsbHcGetHostAddrForPciAddr (Xhc->MemPool, (VOID *)(UINTN)PhyAddr, sizeof (TRB_TEMPLATE), FALSE); 679 679 680 680 // … … 767 767 XhcDequeue = (UINT64)(LShiftU64 ((UINT64)High, 32) | Low); 768 768 769 PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Xhc->EventRing.EventRingDequeue, sizeof (TRB_TEMPLATE) );769 PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Xhc->EventRing.EventRingDequeue, sizeof (TRB_TEMPLATE), FALSE); 770 770 771 771 if ((XhcDequeue & (~0x0F)) != (PhyAddr & (~0x0F))) { … … 1214 1214 Xhc->MemPool, 1215 1215 ((TRANSFER_RING *)(UINTN)Xhc->UsbDevContext[SlotId].EndpointTransferRing[0])->RingSeg0, 1216 sizeof (TRB_TEMPLATE) * TR_RING_TRB_NUMBER 1216 sizeof (TRB_TEMPLATE) * TR_RING_TRB_NUMBER, 1217 TRUE 1217 1218 ); 1218 1219 InputContext->EP[0].PtrLo = XHC_LOW_32BIT (PhyAddr) | BIT0; … … 1232 1233 // a pointer to the Output Device Context data structure (6.2.1). 1233 1234 // 1234 PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, OutputContext, sizeof (DEVICE_CONTEXT) );1235 PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, OutputContext, sizeof (DEVICE_CONTEXT), TRUE); 1235 1236 // 1236 1237 // Fill DCBAA with PCI device address … … 1247 1248 MicroSecondDelay (XHC_RESET_RECOVERY_DELAY); 1248 1249 ZeroMem (&CmdTrbAddr, sizeof (CmdTrbAddr)); 1249 PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Xhc->UsbDevContext[SlotId].InputContext, sizeof (INPUT_CONTEXT) );1250 PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Xhc->UsbDevContext[SlotId].InputContext, sizeof (INPUT_CONTEXT), TRUE); 1250 1251 CmdTrbAddr.PtrLo = XHC_LOW_32BIT (PhyAddr); 1251 1252 CmdTrbAddr.PtrHi = XHC_HIGH_32BIT (PhyAddr); … … 1428 1429 Xhc->MemPool, 1429 1430 ((TRANSFER_RING *)(UINTN)Xhc->UsbDevContext[SlotId].EndpointTransferRing[0])->RingSeg0, 1430 sizeof (TRB_TEMPLATE) * TR_RING_TRB_NUMBER 1431 sizeof (TRB_TEMPLATE) * TR_RING_TRB_NUMBER, 1432 TRUE 1431 1433 ); 1432 1434 InputContext->EP[0].PtrLo = XHC_LOW_32BIT (PhyAddr) | BIT0; … … 1446 1448 // a pointer to the Output Device Context data structure (6.2.1). 1447 1449 // 1448 PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, OutputContext, sizeof (DEVICE_CONTEXT_64) );1450 PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, OutputContext, sizeof (DEVICE_CONTEXT_64), TRUE); 1449 1451 // 1450 1452 // Fill DCBAA with PCI device address … … 1461 1463 MicroSecondDelay (XHC_RESET_RECOVERY_DELAY); 1462 1464 ZeroMem (&CmdTrbAddr, sizeof (CmdTrbAddr)); 1463 PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Xhc->UsbDevContext[SlotId].InputContext, sizeof (INPUT_CONTEXT_64) );1465 PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Xhc->UsbDevContext[SlotId].InputContext, sizeof (INPUT_CONTEXT_64), TRUE); 1464 1466 CmdTrbAddr.PtrLo = XHC_LOW_32BIT (PhyAddr); 1465 1467 CmdTrbAddr.PtrHi = XHC_HIGH_32BIT (PhyAddr); … … 1883 1885 Xhc->MemPool, 1884 1886 ((TRANSFER_RING *)(UINTN)Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1])->RingSeg0, 1885 sizeof (TRB_TEMPLATE) * TR_RING_TRB_NUMBER 1887 sizeof (TRB_TEMPLATE) * TR_RING_TRB_NUMBER, 1888 TRUE 1886 1889 ); 1887 1890 PhyAddr &= ~((EFI_PHYSICAL_ADDRESS)0x0F); … … 1902 1905 // 1903 1906 ZeroMem (&CmdTrbCfgEP, sizeof (CmdTrbCfgEP)); 1904 PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, InputContext, sizeof (INPUT_CONTEXT) );1907 PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, InputContext, sizeof (INPUT_CONTEXT), TRUE); 1905 1908 CmdTrbCfgEP.PtrLo = XHC_LOW_32BIT (PhyAddr); 1906 1909 CmdTrbCfgEP.PtrHi = XHC_HIGH_32BIT (PhyAddr); … … 2109 2112 Xhc->MemPool, 2110 2113 ((TRANSFER_RING *)(UINTN)Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1])->RingSeg0, 2111 sizeof (TRB_TEMPLATE) * TR_RING_TRB_NUMBER 2114 sizeof (TRB_TEMPLATE) * TR_RING_TRB_NUMBER, 2115 TRUE 2112 2116 ); 2113 2117 … … 2130 2134 // 2131 2135 ZeroMem (&CmdTrbCfgEP, sizeof (CmdTrbCfgEP)); 2132 PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, InputContext, sizeof (INPUT_CONTEXT_64) );2136 PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, InputContext, sizeof (INPUT_CONTEXT_64), TRUE); 2133 2137 CmdTrbCfgEP.PtrLo = XHC_LOW_32BIT (PhyAddr); 2134 2138 CmdTrbCfgEP.PtrHi = XHC_HIGH_32BIT (PhyAddr); … … 2185 2189 2186 2190 ZeroMem (&CmdTrbEvalu, sizeof (CmdTrbEvalu)); 2187 PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, InputContext, sizeof (INPUT_CONTEXT) );2191 PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, InputContext, sizeof (INPUT_CONTEXT), TRUE); 2188 2192 CmdTrbEvalu.PtrLo = XHC_LOW_32BIT (PhyAddr); 2189 2193 CmdTrbEvalu.PtrHi = XHC_HIGH_32BIT (PhyAddr); … … 2240 2244 2241 2245 ZeroMem (&CmdTrbEvalu, sizeof (CmdTrbEvalu)); 2242 PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, InputContext, sizeof (INPUT_CONTEXT_64) );2246 PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, InputContext, sizeof (INPUT_CONTEXT_64), TRUE); 2243 2247 CmdTrbEvalu.PtrLo = XHC_LOW_32BIT (PhyAddr); 2244 2248 CmdTrbEvalu.PtrHi = XHC_HIGH_32BIT (PhyAddr); … … 2309 2313 2310 2314 ZeroMem (&CmdTrbCfgEP, sizeof (CmdTrbCfgEP)); 2311 PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, InputContext, sizeof (INPUT_CONTEXT) );2315 PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, InputContext, sizeof (INPUT_CONTEXT), TRUE); 2312 2316 CmdTrbCfgEP.PtrLo = XHC_LOW_32BIT (PhyAddr); 2313 2317 CmdTrbCfgEP.PtrHi = XHC_HIGH_32BIT (PhyAddr); … … 2378 2382 2379 2383 ZeroMem (&CmdTrbCfgEP, sizeof (CmdTrbCfgEP)); 2380 PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, InputContext, sizeof (INPUT_CONTEXT_64) );2384 PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, InputContext, sizeof (INPUT_CONTEXT_64), TRUE); 2381 2385 CmdTrbCfgEP.PtrLo = XHC_LOW_32BIT (PhyAddr); 2382 2386 CmdTrbCfgEP.PtrHi = XHC_HIGH_32BIT (PhyAddr); … … 2523 2527 // 2524 2528 ZeroMem (&CmdSetTRDeq, sizeof (CmdSetTRDeq)); 2525 PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Urb->Ring->RingEnqueue, sizeof (CMD_SET_TR_DEQ_POINTER) );2529 PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Urb->Ring->RingEnqueue, sizeof (CMD_SET_TR_DEQ_POINTER), FALSE); 2526 2530 CmdSetTRDeq.PtrLo = XHC_LOW_32BIT (PhyAddr) | Urb->Ring->RingPCS; 2527 2531 CmdSetTRDeq.PtrHi = XHC_HIGH_32BIT (PhyAddr); … … 2683 2687 ZeroMem (Buf, Size); 2684 2688 2685 DequeuePhy = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Buf, Size );2689 DequeuePhy = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Buf, Size, TRUE); 2686 2690 2687 2691 EventRing->EventRingSeg0 = Buf; … … 2708 2712 ERSTBase->RingTrbSize = EVENT_RING_TRB_NUMBER; 2709 2713 2710 ERSTPhy = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Buf, Size );2714 ERSTPhy = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Buf, Size, TRUE); 2711 2715 2712 2716 // … … 2856 2860 EndTrb = (LINK_TRB *)((UINTN)Buf + sizeof (TRB_TEMPLATE) * (TrbNum - 1)); 2857 2861 EndTrb->Type = TRB_TYPE_LINK; 2858 PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Buf, sizeof (TRB_TEMPLATE) * TrbNum );2862 PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Buf, sizeof (TRB_TEMPLATE) * TrbNum, TRUE); 2859 2863 EndTrb->PtrLo = XHC_LOW_32BIT (PhyAddr); 2860 2864 EndTrb->PtrHi = XHC_HIGH_32BIT (PhyAddr); … … 2989 2993 // So divide it to two 32-bytes width register access. 2990 2994 // 2991 DcbaaPhy = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Dcbaa, Size );2995 DcbaaPhy = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Dcbaa, Size, TRUE); 2992 2996 XhcPeiWriteOpReg (Xhc, XHC_DCBAAP_OFFSET, XHC_LOW_32BIT (DcbaaPhy)); 2993 2997 XhcPeiWriteOpReg (Xhc, XHC_DCBAAP_OFFSET + 4, XHC_HIGH_32BIT (DcbaaPhy)); … … 3007 3011 // So we set RCS as inverted PCS init value to let Command Ring empty 3008 3012 // 3009 CmdRingPhy = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Xhc->CmdRing.RingSeg0, sizeof (TRB_TEMPLATE) * CMD_RING_TRB_NUMBER );3013 CmdRingPhy = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Xhc->CmdRing.RingSeg0, sizeof (TRB_TEMPLATE) * CMD_RING_TRB_NUMBER, TRUE); 3010 3014 ASSERT ((CmdRingPhy & 0x3F) == 0); 3011 3015 CmdRingPhy |= XHC_CRCR_RCS; -
trunk/src/VBox/Devices/EFI/FirmwareNew/MdeModulePkg/Bus/Scsi/ScsiDiskDxe/ScsiDisk.c
r101291 r105670 1898 1898 1899 1899 @param This Indicates a pointer to the calling context. 1900 @param MediaId ID of the medium to receive data from. 1900 @param MediaId ID of the medium to receive data from. If there is no 1901 block IO protocol supported by the physical device, the 1902 value of MediaId is undefined. 1901 1903 @param Timeout The timeout, in 100ns units, to use for the execution 1902 1904 of the security protocol command. A Timeout value of 0 … … 2120 2122 2121 2123 @param This Indicates a pointer to the calling context. 2122 @param MediaId ID of the medium to receive data from. 2124 @param MediaId ID of the medium to receive data from. If there is no 2125 block IO protocol supported by the physical device, the 2126 value of MediaId is undefined. 2123 2127 @param Timeout The timeout, in 100ns units, to use for the execution 2124 2128 of the security protocol command. A Timeout value of 0 -
trunk/src/VBox/Devices/EFI/FirmwareNew/MdeModulePkg/Bus/Scsi/ScsiDiskDxe/ScsiDisk.h
r101291 r105670 678 678 679 679 @param This Indicates a pointer to the calling context. 680 @param MediaId ID of the medium to receive data from. 680 @param MediaId ID of the medium to receive data from. If there is no 681 block IO protocol supported by the physical device, the 682 value of MediaId is undefined. 681 683 @param Timeout The timeout, in 100ns units, to use for the execution 682 684 of the security protocol command. A Timeout value of 0 … … 752 754 753 755 @param This Indicates a pointer to the calling context. 754 @param MediaId ID of the medium to receive data from. 756 @param MediaId ID of the medium to receive data from. If there is no 757 block IO protocol supported by the physical device, the 758 value of MediaId is undefined. 755 759 @param Timeout The timeout, in 100ns units, to use for the execution 756 760 of the security protocol command. A Timeout value of 0 -
trunk/src/VBox/Devices/EFI/FirmwareNew/MdeModulePkg/Bus/Sd/EmmcDxe/EmmcBlockIo.c
r99404 r105670 1268 1268 1269 1269 @param[in] This Indicates a pointer to the calling context. 1270 @param[in] MediaId ID of the medium to receive data from. 1270 @param[in] MediaId ID of the medium to receive data from. If there is no 1271 block IO protocol supported by the physical device, the 1272 value of MediaId is undefined. 1271 1273 @param[in] Timeout The timeout, in 100ns units, to use for the execution 1272 1274 of the security protocol command. A Timeout value of 0 … … 1455 1457 1456 1458 @param This Indicates a pointer to the calling context. 1457 @param MediaId ID of the medium to receive data from. 1459 @param MediaId ID of the medium to receive data from. If there is no 1460 block IO protocol supported by the physical device, the 1461 value of MediaId is undefined. 1458 1462 @param Timeout The timeout, in 100ns units, to use for the execution 1459 1463 of the security protocol command. A Timeout value of 0 … … 1556 1560 1557 1561 @param This Indicates a pointer to the calling context. 1558 @param MediaId ID of the medium to receive data from. 1562 @param MediaId ID of the medium to receive data from. If there is no 1563 block IO protocol supported by the physical device, the 1564 value of MediaId is undefined. 1559 1565 @param Timeout The timeout, in 100ns units, to use for the execution 1560 1566 of the security protocol command. A Timeout value of 0 -
trunk/src/VBox/Devices/EFI/FirmwareNew/MdeModulePkg/Bus/Sd/EmmcDxe/EmmcBlockIo.h
r99404 r105670 251 251 252 252 @param[in] This Indicates a pointer to the calling context. 253 @param[in] MediaId ID of the medium to receive data from. 253 @param[in] MediaId ID of the medium to receive data from. If there is no 254 block IO protocol supported by the physical device, the 255 value of MediaId is undefined. 254 256 @param[in] Timeout The timeout, in 100ns units, to use for the execution 255 257 of the security protocol command. A Timeout value of 0 … … 338 340 339 341 @param This Indicates a pointer to the calling context. 340 @param MediaId ID of the medium to receive data from. 342 @param MediaId ID of the medium to receive data from. If there is no 343 block IO protocol supported by the physical device, the 344 value of MediaId is undefined. 341 345 @param Timeout The timeout, in 100ns units, to use for the execution 342 346 of the security protocol command. A Timeout value of 0 … … 418 422 419 423 @param This Indicates a pointer to the calling context. 420 @param MediaId ID of the medium to receive data from. 424 @param MediaId ID of the medium to receive data from. If there is no 425 block IO protocol supported by the physical device, the 426 value of MediaId is undefined. 421 427 @param Timeout The timeout, in 100ns units, to use for the execution 422 428 of the security protocol command. A Timeout value of 0 -
trunk/src/VBox/Devices/EFI/FirmwareNew/MdeModulePkg/Bus/Usb/UsbKbDxe/EfiKey.c
r99404 r105670 693 693 @retval EFI_DEVICE_ERROR The keystroke information was not returned due to 694 694 hardware errors. 695 @retval EFI_UNSUPPORTED The device does not support the ability to read keystroke data. 695 696 696 697 **/ … … 976 977 hardware errors. 977 978 @retval EFI_INVALID_PARAMETER KeyData is NULL. 979 @retval EFI_UNSUPPORTED The device does not support the ability to read keystroke data. 978 980 979 981 **/ -
trunk/src/VBox/Devices/EFI/FirmwareNew/MdeModulePkg/Bus/Usb/UsbKbDxe/EfiKey.h
r99404 r105670 413 413 @retval EFI_DEVICE_ERROR The keystroke information was not returned due to 414 414 hardware errors. 415 @retval EFI_UNSUPPORTED The device does not support the ability to read keystroke data. 415 416 416 417 **/ … … 467 468 hardware errors. 468 469 @retval EFI_INVALID_PARAMETER KeyData is NULL. 470 @retval EFI_UNSUPPORTED The device does not support the ability to read keystroke data. 469 471 470 472 **/ -
trunk/src/VBox/Devices/EFI/FirmwareNew/MdeModulePkg/Bus/Usb/UsbNetwork/NetworkCommon/PxeFunction.c
r101291 r105670 830 830 831 831 Nic->UsbEth->UsbEthFunDescriptor (Nic->UsbEth, &UsbEthFunDescriptor); 832 if ((UsbEthFunDescriptor.NumberMcFilters << 1) == 0) {832 if ((UsbEthFunDescriptor.NumberMcFilters & MAC_FILTERS_MASK) == 0) { 833 833 Nic->RxFilter |= PXE_OPFLAGS_RECEIVE_FILTER_ALL_MULTICAST; 834 834 Nic->UsbEth->SetUsbEthPacketFilter (Nic->UsbEth, Nic->RxFilter); -
trunk/src/VBox/Devices/EFI/FirmwareNew/MdeModulePkg/Bus/Usb/UsbNetwork/UsbCdcEcm/UsbEcmFunction.c
r101291 r105670 629 629 } 630 630 631 if ((UsbEthFunDescriptor.NumberMcFilters << 1) == 0) {631 if ((UsbEthFunDescriptor.NumberMcFilters & MAC_FILTERS_MASK) == 0) { 632 632 return EFI_UNSUPPORTED; 633 633 } … … 770 770 Count = sizeof (gTable)/sizeof (gTable[0]); 771 771 772 for (Index = 0; ( gTable[Index].Src != 0) && (Index < Count); Index++) {772 for (Index = 0; (Index < Count) && (gTable[Index].Src != 0); Index++) { 773 773 if (gTable[Index].Src & Value) { 774 774 *CdcFilter |= gTable[Index].Dst; -
trunk/src/VBox/Devices/EFI/FirmwareNew/MdeModulePkg/Bus/Usb/UsbNetwork/UsbCdcNcm/UsbNcmFunction.c
r101291 r105670 715 715 } 716 716 717 if ((UsbEthFunDescriptor.NumberMcFilters << 1) == 0) {717 if ((UsbEthFunDescriptor.NumberMcFilters & MAC_FILTERS_MASK) == 0) { 718 718 return EFI_UNSUPPORTED; 719 719 } … … 856 856 Count = sizeof (gTable)/sizeof (gTable[0]); 857 857 858 for (Index = 0; ( gTable[Index].Src != 0) && (Index < Count); Index++) {858 for (Index = 0; (Index < Count) && (gTable[Index].Src != 0); Index++) { 859 859 if (gTable[Index].Src & Value) { 860 860 *CdcFilter |= gTable[Index].Dst; -
trunk/src/VBox/Devices/EFI/FirmwareNew/MdeModulePkg/Bus/Usb/UsbNetwork/UsbRndis/UsbRndis.c
r101291 r105670 41 41 42 42 // Check specific device/RNDIS and CDC-DATA 43 if (((InterfaceDescriptor.InterfaceClass == 0x2) &&44 (InterfaceDescriptor.InterfaceSubClass == 0x2) &&45 (InterfaceDescriptor.InterfaceProtocol == 0xFF)) || \46 ((InterfaceDescriptor.InterfaceClass == 0xEF) &&47 (InterfaceDescriptor.InterfaceSubClass == 0x4) &&48 (InterfaceDescriptor.InterfaceProtocol == 0x1)) || \49 ((InterfaceDescriptor.InterfaceClass == 0xA) &&50 (InterfaceDescriptor.InterfaceSubClass == 0x0) &&51 (InterfaceDescriptor.InterfaceProtocol == 0x00))43 if (((InterfaceDescriptor.InterfaceClass == USB_CDC_CLASS) && 44 (InterfaceDescriptor.InterfaceSubClass == USB_CDC_ACM_SUBCLASS) && 45 (InterfaceDescriptor.InterfaceProtocol == USB_VENDOR_PROTOCOL)) || \ 46 ((InterfaceDescriptor.InterfaceClass == USB_MISC_CLASS) && 47 (InterfaceDescriptor.InterfaceSubClass == USB_RNDIS_SUBCLASS) && 48 (InterfaceDescriptor.InterfaceProtocol == USB_RNDIS_ETHERNET_PROTOCOL)) || \ 49 ((InterfaceDescriptor.InterfaceClass == USB_CDC_DATA_CLASS) && 50 (InterfaceDescriptor.InterfaceSubClass == USB_CDC_DATA_SUBCLASS) && 51 (InterfaceDescriptor.InterfaceProtocol == USB_NO_CLASS_PROTOCOL)) 52 52 ) 53 53 { … … 80 80 81 81 // Check for specific device/RNDIS and CDC-DATA 82 if (((InterfaceDescriptor.InterfaceClass == 0x2) &&83 (InterfaceDescriptor.InterfaceSubClass == 0x2) &&84 (InterfaceDescriptor.InterfaceProtocol == 0xFF)) || \85 ((InterfaceDescriptor.InterfaceClass == 0xEF) &&86 (InterfaceDescriptor.InterfaceSubClass == 0x4) &&87 (InterfaceDescriptor.InterfaceProtocol == 0x1))82 if (((InterfaceDescriptor.InterfaceClass == USB_CDC_CLASS) && 83 (InterfaceDescriptor.InterfaceSubClass == USB_CDC_ACM_SUBCLASS) && 84 (InterfaceDescriptor.InterfaceProtocol == USB_VENDOR_PROTOCOL)) || \ 85 ((InterfaceDescriptor.InterfaceClass == USB_MISC_CLASS) && 86 (InterfaceDescriptor.InterfaceSubClass == USB_RNDIS_SUBCLASS) && 87 (InterfaceDescriptor.InterfaceProtocol == USB_RNDIS_ETHERNET_PROTOCOL)) 88 88 ) 89 89 { … … 156 156 157 157 // Check for CDC-DATA 158 if ((InterfaceDescriptor.InterfaceClass == 0xA) &&159 (InterfaceDescriptor.InterfaceSubClass == 0x0) &&160 (InterfaceDescriptor.InterfaceProtocol == 0x0))158 if ((InterfaceDescriptor.InterfaceClass == USB_CDC_DATA_CLASS) && 159 (InterfaceDescriptor.InterfaceSubClass == USB_CDC_DATA_SUBCLASS) && 160 (InterfaceDescriptor.InterfaceProtocol == USB_NO_CLASS_PROTOCOL)) 161 161 { 162 162 return TRUE; … … 189 189 190 190 // Check for Rndis 191 if ((InterfaceDescriptor.InterfaceClass == 0x2) &&192 (InterfaceDescriptor.InterfaceSubClass == 0x2) &&193 (InterfaceDescriptor.InterfaceProtocol == 0xFF))191 if ((InterfaceDescriptor.InterfaceClass == USB_CDC_CLASS) && 192 (InterfaceDescriptor.InterfaceSubClass == USB_CDC_ACM_SUBCLASS) && 193 (InterfaceDescriptor.InterfaceProtocol == USB_VENDOR_PROTOCOL)) 194 194 { 195 195 return TRUE; -
trunk/src/VBox/Devices/EFI/FirmwareNew/MdeModulePkg/Bus/Usb/UsbNetwork/UsbRndis/UsbRndisFunction.c
r101291 r105670 662 662 } 663 663 664 if ((UsbEthFunDescriptor.NumberMcFilters << 1) == 0) {664 if ((UsbEthFunDescriptor.NumberMcFilters & MAC_FILTERS_MASK) == 0) { 665 665 return EFI_UNSUPPORTED; 666 666 } … … 804 804 Count = sizeof (gTable)/sizeof (gTable[0]); 805 805 806 for (Index = 0; ( gTable[Index].Src != 0) && (Index < Count); Index++) {806 for (Index = 0; (Index < Count) && (gTable[Index].Src != 0); Index++) { 807 807 if (gTable[Index].Src & Value) { 808 808 *CdcFilter |= gTable[Index].Dst; … … 857 857 858 858 Nic->UsbEth->UsbEthFunDescriptor (Nic->UsbEth, &UsbEthFunDescriptor); 859 if ((UsbEthFunDescriptor.NumberMcFilters << 1) == 0) {859 if ((UsbEthFunDescriptor.NumberMcFilters & MAC_FILTERS_MASK) == 0) { 860 860 Nic->RxFilter |= PXE_OPFLAGS_RECEIVE_FILTER_ALL_MULTICAST; 861 861 DEBUG ((DEBUG_INFO, "SetUsbEthPacketFilter Nic %lx Nic->UsbEth %lx ", Nic, Nic->UsbEth));
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