Changeset 105685 in vbox for trunk

Timestamp:

Aug 15, 2024 12:31:27 PM (5 months ago)

Author:

vboxsync

Message:

include/iprt/armv8.h: Additional system register identifiers, bugref:10747

File:

• trunk/include/iprt/armv8.h (modified) (4 diffs)

trunk/include/iprt/armv8.h

@@ -299 +299 @@
 /** @name System register IDs.
  * @{ */
+/** OSDTRRX_EL1 register - RW. */
+#define ARMV8_AARCH64_SYSREG_OSDTRRX_EL1            ARMV8_AARCH64_SYSREG_ID_CREATE(2, 0, 0, 0, 2)
 /** MDSCR_EL1 - RW. */
 #define ARMV8_AARCH64_SYSREG_MDSCR_EL1              ARMV8_AARCH64_SYSREG_ID_CREATE(2, 0, 0, 2, 2)
@@ -311 +313 @@
 /** MDCCINT_EL1 register - RW. */
 #define ARMV8_AARCH64_SYSREG_MDCCINT_EL1            ARMV8_AARCH64_SYSREG_ID_CREATE(2, 0, 0, 2, 0)
+/** OSDTRTX_EL1 register - RW. */
+#define ARMV8_AARCH64_SYSREG_OSDTRTX_EL1            ARMV8_AARCH64_SYSREG_ID_CREATE(2, 0, 0, 3, 2)
+/** OSECCR_EL1 register - RW. */
+#define ARMV8_AARCH64_SYSREG_OSECCR_EL1             ARMV8_AARCH64_SYSREG_ID_CREATE(2, 0, 0, 6, 2)
+/** MDRAR_EL1 register - RO. */
+#define ARMV8_AARCH64_SYSREG_MDRAR_EL1              ARMV8_AARCH64_SYSREG_ID_CREATE(2, 0, 1, 0, 0)
 /** OSLAR_EL1 register - WO. */
 #define ARMV8_AARCH64_SYSREG_OSLAR_EL1              ARMV8_AARCH64_SYSREG_ID_CREATE(2, 0, 1, 0, 4)
@@ -589 +597 @@
 #define ARMV8_AARCH64_SYSREG_FPSR                   ARMV8_AARCH64_SYSREG_ID_CREATE(3, 3, 4, 4, 1)
 
+/** ICC_SRE_EL2 register - RW. */
+#define ARMV8_AARCH64_SYSREG_ICC_SRE_EL2            ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 12,  9, 5)
+
 /** TPIDR_EL0 register - RW. */
 #define ARMV8_AARCH64_SYSREG_TPIDR_EL0              ARMV8_AARCH64_SYSREG_ID_CREATE(3, 3, 13,  0, 2)
@@ -599 +610 @@
 #define ARMV8_AARCH64_SYSREG_CNTVCT_EL0             ARMV8_AARCH64_SYSREG_ID_CREATE(3, 3, 14,  0, 2)
 
+/** CNTP_TVAL_EL0 register - RW. */
+#define ARMV8_AARCH64_SYSREG_CNTP_TVAL_EL0          ARMV8_AARCH64_SYSREG_ID_CREATE(3, 3, 14,  2, 0)
+/** CNTP_CTL_EL0 register - RW. */
+#define ARMV8_AARCH64_SYSREG_CNTP_CTL_EL0           ARMV8_AARCH64_SYSREG_ID_CREATE(3, 3, 14,  2, 1)
+/** CNTP_CVAL_EL0 register - RW. */
+#define ARMV8_AARCH64_SYSREG_CNTP_CVAL_EL0          ARMV8_AARCH64_SYSREG_ID_CREATE(3, 3, 14,  2, 2)
+
 /** CNTV_CTL_EL0 register - RW. */
 #define ARMV8_AARCH64_SYSREG_CNTV_CTL_EL0           ARMV8_AARCH64_SYSREG_ID_CREATE(3, 3, 14,  3, 1)
+
+/** VPIDR_EL2 register - RW. */
+#define ARMV8_AARCH64_SYSREG_VPIDR_EL2              ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4,  0,  0, 0)
+/** VMPIDR_EL2 register - RW. */
+#define ARMV8_AARCH64_SYSREG_VMPIDR_EL2             ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4,  0,  0, 5)
+
+/** SCTLR_EL2 register - RW. */
+#define ARMV8_AARCH64_SYSREG_SCTLR_EL2              ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4,  1,  0, 0)
+/** ACTLR_EL2 register - RW. */
+#define ARMV8_AARCH64_SYSREG_ACTLR_EL2              ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4,  1,  0, 1)
+
+/** HCR_EL2 register - RW. */
+#define ARMV8_AARCH64_SYSREG_HCR_EL2                ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4,  1,  1, 0)
+/** MDCR_EL2 register - RW. */
+#define ARMV8_AARCH64_SYSREG_MDCR_EL2               ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4,  1,  1, 1)
+/** CPTR_EL2 register - RW. */
+#define ARMV8_AARCH64_SYSREG_CPTR_EL2               ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4,  1,  1, 2)
+/** HSTR_EL2 register - RW. */
+#define ARMV8_AARCH64_SYSREG_HSTR_EL2               ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4,  1,  1, 3)
+/** HFGRTR_EL2 register - RW. */
+#define ARMV8_AARCH64_SYSREG_HFGRTR_EL2             ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4,  1,  1, 4)
+/** HFGWTR_EL2 register - RW. */
+#define ARMV8_AARCH64_SYSREG_HFGWTR_EL2             ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4,  1,  1, 5)
+/** HFGITR_EL2 register - RW. */
+#define ARMV8_AARCH64_SYSREG_HFGITR_EL2             ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4,  1,  1, 6)
+/** HACR_EL2 register - RW. */
+#define ARMV8_AARCH64_SYSREG_HACR_EL2               ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4,  1,  1, 7)
+
+/** ZCR_EL2 register - RW. */
+#define ARMV8_AARCH64_SYSREG_ZCR_EL2                ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4,  1,  2, 0)
+/** TRFCR_EL2 register - RW. */
+#define ARMV8_AARCH64_SYSREG_TRFCR_EL2              ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4,  1,  2, 1)
+/** HCRX_EL2 register - RW. */
+#define ARMV8_AARCH64_SYSREG_HCRX_EL2               ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4,  1,  2, 2)
+
+/** SDER32_EL2 register - RW. */
+#define ARMV8_AARCH64_SYSREG_SDER32_EL2             ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4,  1,  3, 0)
+
+/** TTBR0_EL2 register - RW. */
+#define ARMV8_AARCH64_SYSREG_TTBR0_EL2              ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4,  2,  0, 0)
+/** TTBR1_EL2 register - RW. */
+#define ARMV8_AARCH64_SYSREG_TTBR1_EL2              ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4,  2,  0, 1)
+/** TCR_EL2 register - RW. */
+#define ARMV8_AARCH64_SYSREG_TCR_EL2                ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4,  2,  0, 2)
+
+/** VTTBR_EL2 register - RW. */
+#define ARMV8_AARCH64_SYSREG_VTTBR_EL2              ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4,  2,  1, 0)
+/** VTCR_EL2 register - RW. */
+#define ARMV8_AARCH64_SYSREG_VTCR_EL2               ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4,  2,  1, 2)
+
+/** VNCR_EL2 register - RW. */
+#define ARMV8_AARCH64_SYSREG_VNCR_EL2               ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4,  2,  2, 0)
+
+/** VSTTBR_EL2 register - RW. */
+#define ARMV8_AARCH64_SYSREG_VSTTBR_EL2             ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4,  2,  6, 0)
+/** VSTCR_EL2 register - RW. */
+#define ARMV8_AARCH64_SYSREG_VSTCR_EL2              ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4,  2,  6, 2)
+
+/** DACR32_EL2 register - RW. */
+#define ARMV8_AARCH64_SYSREG_DACR32_EL2             ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4,  3,  0, 0)
+
+/** HDFGRTR_EL2 register - RW. */
+#define ARMV8_AARCH64_SYSREG_HDFGRTR_EL2            ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4,  3,  1, 4)
+/** HDFGWTR_EL2 register - RW. */
+#define ARMV8_AARCH64_SYSREG_HDFGWTR_EL2            ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4,  3,  1, 5)
+/** HAFGRTR_EL2 register - RW. */
+#define ARMV8_AARCH64_SYSREG_HAFGRTR_EL2            ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4,  3,  1, 6)
+
+/** SPSR_EL2 register - RW. */
+#define ARMV8_AARCH64_SYSREG_SPSR_EL2               ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4,  4,  0, 0)
+/** ELR_EL2 register - RW. */
+#define ARMV8_AARCH64_SYSREG_ELR_EL2                ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4,  4,  0, 1)
+
+/** SP_EL1 register - RW. */
+#define ARMV8_AARCH64_SYSREG_SP_EL1                 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4,  4,  1, 0)
+
+/** IFSR32_EL2 register - RW. */
+#define ARMV8_AARCH64_SYSREG_IFSR32_EL2             ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4,  5,  0, 1)
+
+/** AFSR0_EL2 register - RW. */
+#define ARMV8_AARCH64_SYSREG_AFSR0_EL2              ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4,  5,  1, 0)
+/** AFSR1_EL2 register - RW. */
+#define ARMV8_AARCH64_SYSREG_AFSR1_EL2              ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4,  5,  1, 1)
+
+/** ESR_EL2 register - RW. */
+#define ARMV8_AARCH64_SYSREG_ESR_EL2                ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4,  5,  2, 0)
+/** VSESR_EL2 register - RW. */
+#define ARMV8_AARCH64_SYSREG_VSESR_EL2              ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4,  5,  2, 3)
+
+/** FPEXC32_EL2 register - RW. */
+#define ARMV8_AARCH64_SYSREG_FPEXC32_EL2            ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4,  5,  3, 0)
+
+/** TFSR_EL2 register - RW. */
+#define ARMV8_AARCH64_SYSREG_TFSR_EL2               ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4,  5,  6, 0)
+
+/** FAR_EL2 register - RW. */
+#define ARMV8_AARCH64_SYSREG_FAR_EL2                ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4,  6,  0, 0)
+/** HPFAR_EL2 register - RW. */
+#define ARMV8_AARCH64_SYSREG_HPFAR_EL2              ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4,  6,  0, 4)
+
+/** PMSCR_EL2 register - RW. */
+#define ARMV8_AARCH64_SYSREG_PMSCR_EL2              ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4,  9,  9, 0)
+
+/** MAIR_EL2 register - RW. */
+#define ARMV8_AARCH64_SYSREG_MAIR_EL2               ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 10,  2, 0)
+
+/** AMAIR_EL2 register - RW. */
+#define ARMV8_AARCH64_SYSREG_AMAIR_EL2              ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 10,  3, 0)
+
+/** MPAMHCR_EL2 register - RW. */
+#define ARMV8_AARCH64_SYSREG_MPAMHCR_EL2            ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 10,  4, 0)
+/** MPAMVPMV_EL2 register - RW. */
+#define ARMV8_AARCH64_SYSREG_MPAMVPMV_EL2           ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 10,  4, 1)
+
+/** MPAM2_EL2 register - RW. */
+#define ARMV8_AARCH64_SYSREG_MPAM2_EL2              ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 10,  5, 0)
+
+/** MPAMVPM0_EL2 register - RW. */
+#define ARMV8_AARCH64_SYSREG_MPAMVPM0_EL2           ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 10,  6, 0)
+/** MPAMVPM1_EL2 register - RW. */
+#define ARMV8_AARCH64_SYSREG_MPAMVPM1_EL2           ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 10,  6, 1)
+/** MPAMVPM2_EL2 register - RW. */
+#define ARMV8_AARCH64_SYSREG_MPAMVPM2_EL2           ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 10,  6, 2)
+/** MPAMVPM3_EL2 register - RW. */
+#define ARMV8_AARCH64_SYSREG_MPAMVPM3_EL2           ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 10,  6, 3)
+/** MPAMVPM4_EL2 register - RW. */
+#define ARMV8_AARCH64_SYSREG_MPAMVPM4_EL2           ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 10,  6, 4)
+/** MPAMVPM5_EL2 register - RW. */
+#define ARMV8_AARCH64_SYSREG_MPAMVPM5_EL2           ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 10,  6, 5)
+/** MPAMVPM6_EL2 register - RW. */
+#define ARMV8_AARCH64_SYSREG_MPAMVPM6_EL2           ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 10,  6, 6)
+/** MPAMVPM7_EL2 register - RW. */
+#define ARMV8_AARCH64_SYSREG_MPAMVPM7_EL2           ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 10,  6, 7)
+
+/** VBAR_EL2 register - RW. */
+#define ARMV8_AARCH64_SYSREG_VBAR_EL2               ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 12,  0, 0)
+/** RVBAR_EL2 register - RW. */
+#define ARMV8_AARCH64_SYSREG_RVBAR_EL2              ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 12,  0, 1)
+/** RMR_EL2 register - RW. */
+#define ARMV8_AARCH64_SYSREG_RMR_EL2                ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 12,  0, 2)
+
+/** VDISR_EL2 register - RW. */
+#define ARMV8_AARCH64_SYSREG_VDISR_EL2              ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 12,  1, 1)
+
+/** CONTEXTIDR_EL2 register - RW. */
+#define ARMV8_AARCH64_SYSREG_CONTEXTIDR_EL2         ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 13,  0, 1)
+/** TPIDR_EL2 register - RW. */
+#define ARMV8_AARCH64_SYSREG_TPIDR_EL2              ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 13,  0, 2)
+/** SCXTNUM_EL2 register - RW. */
+#define ARMV8_AARCH64_SYSREG_SCXTNUM_EL2            ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 13,  0, 7)
+
+/** CNTVOFF_EL2 register - RW. */
+#define ARMV8_AARCH64_SYSREG_CNTVOFF_EL2            ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 14,  0, 3)
+/** CNTPOFF_EL2 register - RW. */
+#define ARMV8_AARCH64_SYSREG_CNTPOFF_EL2            ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 14,  0, 6)
+
+/** CNTHCTL_EL2 register - RW. */
+#define ARMV8_AARCH64_SYSREG_CNTHCTL_EL2            ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 14,  1, 0)
+
+/** CNTHP_TVAL_EL2 register - RW. */
+#define ARMV8_AARCH64_SYSREG_CNTHP_TVAL_EL2         ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 14,  2, 0)
+/** CNTHP_CTL_EL2 register - RW. */
+#define ARMV8_AARCH64_SYSREG_CNTHP_CTL_EL2          ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 14,  2, 1)
+/** CNTHP_CVAL_EL2 register - RW. */
+#define ARMV8_AARCH64_SYSREG_CNTHP_CVAL_EL2         ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 14,  2, 2)
+
+/** CNTHV_TVAL_EL2 register - RW. */
+#define ARMV8_AARCH64_SYSREG_CNTHV_TVAL_EL2         ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 14,  3, 0)
+/** CNTHV_CTL_EL2 register - RW. */
+#define ARMV8_AARCH64_SYSREG_CNTHV_CTL_EL2          ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 14,  3, 1)
+/** CNTHV_CVAL_EL2 register - RW. */
+#define ARMV8_AARCH64_SYSREG_CNTHV_CVAL_EL2         ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 14,  3, 2)
+
+/** CNTHVS_TVAL_EL2 register - RW. */
+#define ARMV8_AARCH64_SYSREG_CNTHVS_TVAL_EL2        ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 14,  4, 0)
+/** CNTHVS_CTL_EL2 register - RW. */
+#define ARMV8_AARCH64_SYSREG_CNTHVS_CTL_EL2         ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 14,  4, 1)
+/** CNTHVS_CVAL_EL2 register - RW. */
+#define ARMV8_AARCH64_SYSREG_CNTHVS_CVAL_EL2        ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 14,  4, 2)
+
+/** CNTHPS_TVAL_EL2 register - RW. */
+#define ARMV8_AARCH64_SYSREG_CNTHPS_TVAL_EL2        ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 14,  5, 0)
+/** CNTHPS_CTL_EL2 register - RW. */
+#define ARMV8_AARCH64_SYSREG_CNTHPS_CTL_EL2         ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 14,  5, 1)
+/** CNTHPS_CVAL_EL2 register - RW. */
+#define ARMV8_AARCH64_SYSREG_CNTHPS_CVAL_EL2        ARMV8_AARCH64_SYSREG_ID_CREATE(3, 4, 14,  5, 2)
+
+/** SP_EL2 register - RW. */
+#define ARMV8_AARCH64_SYSREG_SP_EL2                 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 6,  4,  1, 0)
 /** @} */