Changeset 105721 in vbox

Timestamp:

Aug 19, 2024 11:12:33 AM (6 months ago)

Author:

vboxsync

Message:

ValidationKit/bootsectors: bugref:10658 SIMD FP testcase: [v]mulsd (W.I.P)

File:

• trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-4.c32 (modified) (1 diff)

trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-4.c32

@@ -7031 +7031 @@
              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN,
              /*xcpt?    */ false, false },
-    /** @todo Denormals, Invalids, Underflow, Precision; Rounding, FZ etc. */
+    /*
+     * Denormals.
+     */
+    /*25*/{ { /*src2     */ { FP64_DENORM_MAX(0), FP64_0(0),           FP64_DENORM_MIN(0), FP64_0(0)          } },
+            { /*src1     */ { FP64_0(0),          FP64_DENORM_MIN(0),  FP64_0(0),          FP64_DENORM_MAX(0) } },
+            { /* =>      */ { FP64_0(0),          FP64_DENORM_MIN(0), FP64_0(0),          FP64_DENORM_MAX(0) } },
+             /*mxcsr:in */ 0,
+             /*128:out  */ X86_MXCSR_DE,
+             /*256:out  */ X86_MXCSR_DE,
+             /*xcpt?    */ true, true },
+          { { /*src2     */ { FP64_0(0),          FP64_0(0),           FP64_RAND_V2(0), FP64_RAND_V1(1) } },
+            { /*src1     */ { FP64_DENORM_MIN(0), FP64_DENORM_MIN(0),  FP64_RAND_V1(1), FP64_RAND_V3(0) } },
+            { /* =>      */ { FP64_0(0),          FP64_DENORM_MIN(0),  FP64_RAND_V1(1), FP64_RAND_V3(0) } },
+             /*mxcsr:in */ X86_MXCSR_FZ,
+             /*128:out  */ X86_MXCSR_FZ | X86_MXCSR_DE,
+             /*256:out  */ X86_MXCSR_FZ | X86_MXCSR_DE,
+             /*xcpt?    */ true, true },
+          { { /*src2     */ { FP64_DENORM_MAX(0), FP64_RAND_V3(0), FP64_RAND_V2(0), FP64_RAND_V1(1) } },
+            { /*src1     */ { FP64_DENORM_MIN(0), FP64_RAND_V1(1), FP64_RAND_V1(1), FP64_RAND_V3(0) } },
+            { /* =>      */ { FP64_0(0),          FP64_RAND_V1(1), FP64_RAND_V1(1), FP64_RAND_V3(0) } },
+             /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ,
+             /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ,
+             /*256:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ,
+             /*xcpt?    */ false, false },
+          { { /*src2     */ { FP64_DENORM_MAX(0), FP64_RAND_V2(0), FP64_RAND_V2(0), FP64_RAND_V1(1) } },
+            { /*src1     */ { FP64_1(0),          FP64_RAND_V0(1), FP64_RAND_V1(0), FP64_RAND_V3(1) } },
+            { /* =>      */ { FP64_0(0),          FP64_RAND_V0(1), FP64_RAND_V1(0), FP64_RAND_V3(1) } },
+              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ,
+              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ,
+              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ,
+              /*xcpt?    */ false, false },
+          { { /*src2     */ { FP64_DENORM_MIN(1), FP64_RAND_V2(0), FP64_RAND_V3(0), FP64_RAND_V1(1) } },
+            { /*src1     */ { FP64_DENORM_MAX(1), FP64_RAND_V1(1), FP64_RAND_V2(0), FP64_RAND_V2(1) } },
+            { /* =>      */ { FP64_0(0),          FP64_RAND_V1(1), FP64_RAND_V2(0), FP64_RAND_V2(1) } },
+              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
+              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
+              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
+              /*xcpt?    */ false, false },
+          { { /*src2     */ { FP64_1(0),       FP64_RAND_V3(0), FP64_RAND_V3(0), FP64_RAND_V1(1) } },
+            { /*src1     */ { FP64_NORM_V0(0), FP64_RAND_V0(1), FP64_RAND_V1(0), FP64_RAND_V2(1) } },
+            { /* =>      */ { FP64_NORM_V0(0), FP64_RAND_V0(1), FP64_RAND_V1(0), FP64_RAND_V2(1) } },
+              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
+              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
+              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_UP | X86_MXCSR_DE | X86_MXCSR_UE | X86_MXCSR_PE,
+              /*xcpt?    */ false, false },
+          { { /*src2     */ { FP64_DENORM_MAX(0), FP64_RAND_V2(0), FP64_RAND_V3(0), FP64_RAND_V1(0) } },
+            { /*src1     */ { FP64_DENORM_MAX(0), FP64_RAND_V1(1), FP64_RAND_V2(0), FP64_RAND_V0(0) } },
+            { /* =>      */ { FP64_0(0),          FP64_RAND_V1(1), FP64_RAND_V2(0), FP64_RAND_V0(0) } },
+              /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
+              /*128:out  */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_DE,
+              /*256:out  */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_DE,
+              /*xcpt?    */ true, true },
+          { { /*src2     */ { FP64_DENORM_MIN(0), FP64_DENORM_MAX(0), FP64_DENORM_MAX(0), FP64_DENORM_MAX(0) } },
+            { /*src1     */ { FP64_DENORM_MIN(0), FP64_DENORM_MIN(0), FP64_DENORM_MAX(1), FP64_DENORM_MIN(1) } },
+            { /* =>      */ { FP64_0(0),          FP64_DENORM_MIN(0), FP64_DENORM_MAX(1), FP64_DENORM_MIN(1) } },
+              /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
+              /*128:out  */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_DE,
+              /*256:out  */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_DE,
+              /*xcpt?    */ true, true },
+    /** @todo Invalids, Underflow, Precision; Rounding, FZ etc. */
     };