Changeset 105796 in vbox for trunk/src/VBox/Disassembler

Timestamp:

Aug 21, 2024 8:06:23 PM (8 months ago)

Author:

vboxsync

svn:sync-xref-src-repo-rev:

164508

Message:

Disassembler/ARMv8: Start some very simple alias conversion for orr -> mov and subs -> cmp which are the most common, bugref:10394

Location:

trunk/src/VBox/Disassembler

Files:

• DisasmCore-armv8.cpp (modified) (2 diffs)
• testcase/tstDisasmArmv8-1-asm.S (modified) (2 diffs)

trunk/src/VBox/Disassembler/DisasmCore-armv8.cpp

@@ -458 +458 @@
 
 
+/**
+ * Looks for possible alias conversions for the given disassembler state.
+ *
+ * @param   pDis        The disassembler state to process.
+ */
+static void disArmV8A64InsnAliasesProcess(PDISSTATE pDis)
+{
+#define DIS_ARMV8_ALIAS(a_Name) s_DisArmv8Alias ## a_Name
+#define DIS_ARMV8_ALIAS_CREATE(a_Name, a_szOpcode, a_uOpcode, a_fOpType) static const DISOPCODE DIS_ARMV8_ALIAS(a_Name) = OP(a_szOpcode, 0, 0, 0, a_uOpcode, 0, 0, 0, a_fOpType)
+#define DIS_ARMV8_ALIAS_REF(a_Name) &DIS_ARMV8_ALIAS(a_Name)
+    switch (pDis->pCurInstr->uOpcode)
+    {
+        case OP_ARMV8_A64_ORR:
+        {
+            /* Check for possible MOV conversion for the register variant when: shift is None and the first source is the zero register. */
+            Assert(pDis->aParams[1].armv8.enmType == kDisArmv8OpParmGpr);
+
+            if (   pDis->aParams[2].armv8.enmType == kDisArmv8OpParmGpr
+                && pDis->aParams[2].armv8.enmShift == kDisArmv8OpParmShiftNone
+                && pDis->aParams[1].armv8.Reg.idxGenReg == ARMV8_A64_REG_XZR)
+            {
+                DIS_ARMV8_ALIAS_CREATE(Mov, "mov", OP_ARMV8_A64_MOV, DISOPTYPE_HARMLESS);
+                pDis->pCurInstr  = DIS_ARMV8_ALIAS_REF(Mov);
+                pDis->aParams[1] = pDis->aParams[2];
+                pDis->aParams[2].armv8.enmType = kDisArmv8OpParmNone;
+            }
+            /** @todo Immediate variant. */
+            break;
+        }
+        case OP_ARMV8_A64_SUBS:
+        {
+            Assert(pDis->aParams[0].armv8.enmType == kDisArmv8OpParmGpr);
+            if (pDis->aParams[0].armv8.Reg.idxGenReg == ARMV8_A64_REG_XZR)
+            {
+                DIS_ARMV8_ALIAS_CREATE(Cmp, "cmp", OP_ARMV8_A64_CMP, DISOPTYPE_HARMLESS);
+                pDis->pCurInstr  = DIS_ARMV8_ALIAS_REF(Cmp);
+                pDis->aParams[0] = pDis->aParams[1];
+                pDis->aParams[1] = pDis->aParams[2];
+                pDis->aParams[2].armv8.enmType = kDisArmv8OpParmNone;
+            }
+            break;
+        }
+        default:
+            break; /* No conversion */
+    }
+#undef DIS_ARMV8_ALIAS_REF
+#undef DIS_ARMV8_ALIAS_CREATE
+#undef DIS_ARMV8_ALIAS
+}
+
+
 static int disArmV8A64ParseInstruction(PDISSTATE pDis, uint32_t u32Insn, PCDISARMV8OPCODE pOp, PCDISARMV8INSNCLASS pInsnClass)
 {
@@ -500 +551 @@
 
     /* If parameter parsing returned an invalid opcode error the encoding is invalid. */
-    if (rc == VERR_DIS_INVALID_OPCODE)
+    if (RT_SUCCESS(rc)) /** @todo Introduce flag to switch alias conversion on/off. */
+        disArmV8A64InsnAliasesProcess(pDis);
+    else if (rc == VERR_DIS_INVALID_OPCODE)
     {
         pDis->pCurInstr = &g_ArmV8A64InvalidOpcode[0];

trunk/src/VBox/Disassembler/testcase/tstDisasmArmv8-1-asm.S

@@ -177 +177 @@
         ; ROR is reserved
 
-;       mov x0, x1 @todo Aliases are not supported right now.
-;       mov w0, w1
+        ; Aliases of subs -> cmp
+        cmp x0, x1
+        cmp w0, w1
+        cmp x0, x1, LSL #1
+        cmp w0, w1, LSL #1
 
         ; Logical instructions
@@ -189 +192 @@
         orr  x0,  x0,  #0xffff
         orr  w0,  wzr, #0xffff
+
+        mov x0, x1 ; Alias of orr
+        mov w0, w1 ; Alias of orr
 
         eor  x0,  x0,  #0x00ffff00