Changeset 105810 in vbox for trunk/src

Timestamp:

Aug 22, 2024 8:26:22 AM (9 months ago)

Author:

vboxsync

svn:sync-xref-src-repo-rev:

164523

Message:

Disassembler/ARMv8: Implement disassembly of ccmp/ccmn register variants and add testcases, bugref:10394

Location:

trunk/src/VBox/Disassembler

Files:

• DisasmCore-armv8.cpp (modified) (1 diff)
• DisasmFormatArmV8.cpp (modified) (1 diff)
• DisasmTables-armv8-a64.cpp (modified) (2 diffs)
• testcase/tstDisasmArmv8-1-asm.S (modified) (1 diff)

trunk/src/VBox/Disassembler/DisasmCore-armv8.cpp

@@ -301 +301 @@
 {
     RT_NOREF(pInsnClass, pParam, pf64Bit);
-    pDis->armv8.enmCond = (DISARMV8INSTRCOND)disArmV8ExtractBitVecFromInsn(u32Insn, pInsnParm->idxBitStart, pInsnParm->cBits);
+    Assert(pInsnParm->cBits <= 4);
+    if (pParam)
+    {
+        /* Conditional as a parameter (CCMP/CCMN). */
+        Assert(pParam->armv8.enmType == kDisArmv8OpParmCond);
+        pParam->armv8.Reg.enmCond = (DISARMV8INSTRCOND)disArmV8ExtractBitVecFromInsn(u32Insn, pInsnParm->idxBitStart, pInsnParm->cBits);
+    }
+    else /* Conditional for the base instruction. */
+        pDis->armv8.enmCond = (DISARMV8INSTRCOND)disArmV8ExtractBitVecFromInsn(u32Insn, pInsnParm->idxBitStart, pInsnParm->cBits);
     return VINF_SUCCESS;
 }

trunk/src/VBox/Disassembler/DisasmFormatArmV8.cpp

@@ -730 +730 @@
                     break;
                 }
+                case kDisArmv8OpParmCond:
+                {
+                    Assert((uint16_t)pParam->armv8.Reg.enmCond < RT_ELEMENTS(g_aszArmV8Cond));
+                    PUT_STR(g_aszArmV8Cond[pParam->armv8.Reg.enmCond], sizeof(g_aszArmV8Cond[0]) - 1);
+                    break;
+                }
                 default:
                     AssertFailed();

trunk/src/VBox/Disassembler/DisasmTables-armv8-a64.cpp

@@ -463 +463 @@
 
 
-
 DIS_ARMV8_DECODE_MAP_DEFINE_BEGIN(AddSubExtReg)
     DIS_ARMV8_DECODE_MAP_INVALID_ENTRY, /** @todo */
@@ -481 +480 @@
 
 
+/* CCMN/CCMP */
+DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(CondCmpReg)
+    DIS_ARMV8_OP(0x3a400000, "ccmn",            OP_ARMV8_A64_CCMN,      DISOPTYPE_HARMLESS),
+    DIS_ARMV8_OP(0x7a400000, "ccmp",            OP_ARMV8_A64_CCMP,      DISOPTYPE_HARMLESS)
+DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(CondCmpReg)
+    DIS_ARMV8_INSN_DECODE(kDisParmParseReg,            5,  5, 0 /*idxParam*/),
+    DIS_ARMV8_INSN_DECODE(kDisParmParseReg,           16,  5, 1 /*idxParam*/),
+    DIS_ARMV8_INSN_DECODE(kDisParmParseImm,            0,  4, 2 /*idxParam*/),
+    DIS_ARMV8_INSN_DECODE(kDisParmParseCond,          12,  4, 3 /*idxParam*/),
+DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END_PARAMS_4(CondCmpReg, 0x7fe00c10 /*fFixedInsn*/, DISARMV8INSNCLASS_F_SF,
+                                                kDisArmV8OpcDecodeNop, RT_BIT_32(30), 30,
+                                                kDisArmv8OpParmGpr, kDisArmv8OpParmGpr, kDisArmv8OpParmImm, kDisArmv8OpParmCond);
+
+
+/**
+ * C4.1.95 - Data Processing - Register
+ *
+ * The conditional compare instructions differentiate between register and immediate
+ * variant based on the 11th bit (part of op3).
+ */
+DIS_ARMV8_DECODE_MAP_DEFINE_BEGIN(CondCmp)
+    DIS_ARMV8_DECODE_MAP_ENTRY(CondCmpReg),          /* Conditional compare register */
+    DIS_ARMV8_DECODE_MAP_INVALID_ENTRY,              /** @todo Conditional compare immediate */
+DIS_ARMV8_DECODE_MAP_DEFINE_END(CondCmp, RT_BIT_32(11), 11);
+
+
+/*
+ * C4.1.95 - Data Processing - Register
+ *
+ * The op1 field is already decoded in the previous step and is 1 when being here,
+ * leaving us with the following possible values:
+ *
+ *     Bit  24 23 22 21
+ *     +-------------------------------------------
+ *           0  0  0  0 Add/subtract with carry / Rotate right into flags / Evaluate into flags (depending on op3)
+ *           0  0  0  1 UNALLOC
+ *           0  0  1  0 Conditional compare (register / immediate)
+ *           0  0  1  1 UNALLOC
+ *           0  1  0  0 Conditional select
+ *           0  1  0  1 UNALLOC
+ *           0  1  1  0 Data processing (2-source or 1-source depending on op0).
+ *           0  1  1  1 UNALLOC
+ *           1  x  x  x Data processing 3-source
+ */
 DIS_ARMV8_DECODE_MAP_DEFINE_BEGIN(DataProcReg)
-    DIS_ARMV8_DECODE_MAP_INVALID_ENTRY,
-DIS_ARMV8_DECODE_MAP_DEFINE_END(DataProcReg, RT_BIT_32(24), 24);
+    DIS_ARMV8_DECODE_MAP_INVALID_ENTRY,             /** @todo Add/subtract with carry. */
+    DIS_ARMV8_DECODE_MAP_INVALID_ENTRY,
+    DIS_ARMV8_DECODE_MAP_ENTRY(CondCmp),            /** @todo Conditional compare. */
+    DIS_ARMV8_DECODE_MAP_INVALID_ENTRY,
+    DIS_ARMV8_DECODE_MAP_INVALID_ENTRY,             /** @todo Conditional select. */
+    DIS_ARMV8_DECODE_MAP_INVALID_ENTRY,
+    DIS_ARMV8_DECODE_MAP_INVALID_ENTRY,             /** @todo Data Processing 2-source/1-source. */
+    DIS_ARMV8_DECODE_MAP_INVALID_ENTRY,
+    DIS_ARMV8_DECODE_MAP_INVALID_ENTRY,             /** @todo Data Processing 3-source. */
+    DIS_ARMV8_DECODE_MAP_INVALID_ENTRY,             /** @todo Data Processing 3-source. */
+    DIS_ARMV8_DECODE_MAP_INVALID_ENTRY,             /** @todo Data Processing 3-source. */
+    DIS_ARMV8_DECODE_MAP_INVALID_ENTRY,             /** @todo Data Processing 3-source. */
+    DIS_ARMV8_DECODE_MAP_INVALID_ENTRY,             /** @todo Data Processing 3-source. */
+    DIS_ARMV8_DECODE_MAP_INVALID_ENTRY,             /** @todo Data Processing 3-source. */
+    DIS_ARMV8_DECODE_MAP_INVALID_ENTRY,             /** @todo Data Processing 3-source. */
+    DIS_ARMV8_DECODE_MAP_INVALID_ENTRY,             /** @todo Data Processing 3-source. */
+DIS_ARMV8_DECODE_MAP_DEFINE_END(DataProcReg, RT_BIT_32(21) | RT_BIT_32(22) | RT_BIT_32(23) | RT_BIT_32(24), 21);
 
 

trunk/src/VBox/Disassembler/testcase/tstDisasmArmv8-1-asm.S

@@ -390 +390 @@
         str w0, [x28, #16380]
 
+        ; Conditional compare
+        ccmp x0, x1, #0x3, eq
+        ccmp w0, w1, #0xf, eq
+        ccmp x0, x1, #0x3, ne
+        ccmp w0, w1, #0xf, ne
+        ccmp x0, x1, #0x3, cs
+        ccmp w0, w1, #0xf, cc
+        ccmp x0, x1, #0x3, mi
+        ccmp w0, w1, #0xf, mi
+        ccmp x0, x1, #0x3, pl
+        ccmp w0, w1, #0xf, vs
+        ccmp x0, x1, #0x3, vc
+        ccmp w0, w1, #0xf, vc
+        ccmp x0, x1, #0x3, hi
+        ccmp w0, w1, #0xf, hi
+        ccmp x0, x1, #0x3, ls
+        ccmp w0, w1, #0xf, ls
+        ccmp x0, x1, #0x3, ge
+        ccmp w0, w1, #0xf, ge
+        ccmp x0, x1, #0x3, lt
+        ccmp w0, w1, #0xf, lt
+        ccmp x0, x1, #0x3, gt
+        ccmp w0, w1, #0xf, gt
+        ccmp x0, x1, #0x3, le
+        ccmp w0, w1, #0xf, le
+        ccmp x0, x1, #0x3, al
+        ccmp w0, w1, #0xf, al
+
+        ccmn x0, x1, #0x3, eq
+        ccmn w0, w1, #0xf, eq
+        ccmn x0, x1, #0x3, ne
+        ccmn w0, w1, #0xf, ne
+        ccmn x0, x1, #0x3, cs
+        ccmn w0, w1, #0xf, cc
+        ccmn x0, x1, #0x3, mi
+        ccmn w0, w1, #0xf, mi
+        ccmn x0, x1, #0x3, pl
+        ccmn w0, w1, #0xf, vs
+        ccmn x0, x1, #0x3, vc
+        ccmn w0, w1, #0xf, vc
+        ccmn x0, x1, #0x3, hi
+        ccmn w0, w1, #0xf, hi
+        ccmn x0, x1, #0x3, ls
+        ccmn w0, w1, #0xf, ls
+        ccmn x0, x1, #0x3, ge
+        ccmn w0, w1, #0xf, ge
+        ccmn x0, x1, #0x3, lt
+        ccmn w0, w1, #0xf, lt
+        ccmn x0, x1, #0x3, gt
+        ccmn w0, w1, #0xf, gt
+        ccmn x0, x1, #0x3, le
+        ccmn w0, w1, #0xf, le
+        ccmn x0, x1, #0x3, al
+        ccmn w0, w1, #0xf, al
+
         ;
         ; Keep last so the testcase can catch errors in