Changeset 105836 in vbox for trunk/src/VBox/ValidationKit

Timestamp:

Aug 23, 2024 6:12:22 AM (3 months ago)

Author:

vboxsync

Message:

ValidationKit/bootsectors: bugref:10658 SIMD FP testcase: [v]mulps.

File:

• trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-4.c32 (modified) (1 diff)

trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-4.c32

@@ -6134 +6134 @@
              /*256:out  */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
              /*xcpt?    */ false, false },
-    /** @todo Normals, Denormals, Overflow/Precision, Invalids, Underflow, Precision;
+    /*
+     * Normals.
+     */
+    /*12*/{ { /*src2     */ { FP32_V(0, 0x600000, 0x7f)/*1.7500*/, FP32_NORM_V0(0), FP32_NORM_V1(0), FP32_NORM_V2(1), FP32_1(1),       FP32_1(0),       FP32_1(1),       FP32_NORM_V6(1) } },
+            { /*src1     */ { FP32_V(0, 0,        0x7d)/*0.2500*/, FP32_1(0),       FP32_1(1),       FP32_0(0),       FP32_NORM_V0(1), FP32_NORM_V3(0), FP32_NORM_V4(0), FP32_1(0)       } },
+            { /* =>      */ { FP32_V(0, 0x600000, 0x7d)/*0.4375*/, FP32_NORM_V0(0), FP32_NORM_V1(1), FP32_0(1),       FP32_NORM_V0(0), FP32_NORM_V3(0), FP32_NORM_V4(1), FP32_NORM_V6(1) } },
+              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
+              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
+              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
+              /*xcpt?    */ false, false },
+          { { /*src2     */ { FP32_V(0, 0x61e000, 0x89)/*   1807*/, FP32_V(0, 0x61e000, 0x89)/*   1807*/, FP32_V(0, 0x4a30b8, 0x8f)/* 103521.4375*/, FP32_V(0, 0x1a5200, 0x8c)/*     9876.5*/, FP32_V(0, 0x23b6a0, 0x8e)/*41910.625000*/, FP32_V(0, 0x23b6a0, 0x8e)/*41910.625000*/, FP32_V(0, 0,        0x7d)/*0.2500*/, FP32_V(0, 0x504000, 0x8a)/*    3332*/ } },
+            { /*src1     */ { FP32_V(0, 0x504000, 0x8a)/*   3332*/, FP32_V(0, 0x504000, 0x8a)/*   3332*/, FP32_V(0, 0x600000, 0x82)/*     14.0000*/, FP32_V(1, 0x1a4000, 0x89)/*    -1234.0*/, FP32_V(0, 0,        0x7c)/*    0.125000*/, FP32_V(0, 0,        0x7c)/*    0.125000*/, FP32_V(0, 0x600000, 0x7f)/*1.7500*/, FP32_V(1, 0x61e000, 0x89)/*   -1807*/ } },
+            { /* =>      */ { FP32_V(0, 0x37be78, 0x95)/*6020924*/, FP32_V(0, 0x37be78, 0x95)/*6020924*/, FP32_V(0, 0x30eaa1, 0x93)/*1449300.1250*/, FP32_V(1, 0x39f7d1, 0x96)/*-12187601.0*/, FP32_V(0, 0x23b6a0, 0x8b)/* 5238.828125*/, FP32_V(0, 0x23b6a0, 0x8b)/* 5238.828125*/, FP32_V(0, 0x600000, 0x7d)/*0.4375*/, FP32_V(1, 0x37be78, 0x95)/*-6020924*/ } },
+              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
+              /*128:out  */ X86_MXCSR_XCPT_MASK,
+              /*256:out  */ X86_MXCSR_XCPT_MASK,
+              /*xcpt?    */ false, false },
+          { { /*src2     */ { FP32_NORM_SAFE_INT_MAX(0), FP32_1(0),                 FP32_NORM_SAFE_INT_MAX(1), FP32_1(1),                 FP32_NORM_SAFE_INT_MIN(1), FP32_1(1),                 FP32_NORM_SAFE_INT_MIN(0), FP32_0(1)                 } },
+            { /*src1     */ { FP32_1(0),                 FP32_NORM_SAFE_INT_MIN(0), FP32_1(0),                 FP32_NORM_SAFE_INT_MAX(1), FP32_1(0),                 FP32_NORM_SAFE_INT_MIN(1), FP32_0(0),                 FP32_NORM_SAFE_INT_MAX(0) } },
+            { /* =>      */ { FP32_NORM_SAFE_INT_MAX(0), FP32_NORM_SAFE_INT_MIN(0), FP32_NORM_SAFE_INT_MAX(1), FP32_NORM_SAFE_INT_MAX(0), FP32_NORM_SAFE_INT_MIN(1), FP32_NORM_SAFE_INT_MIN(0), FP32_0(0),                 FP32_0(1)                 } },
+              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
+              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
+              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
+              /*xcpt?    */ false, false },
+          { { /*src2     */ { FP32_NORM_MAX(0), FP32_1(0),        FP32_NORM_MAX(1), FP32_1(1),        FP32_NORM_MIN(0), FP32_NORM_MIN(0), FP32_1(0),        FP32_1(1)        } },
+            { /*src1     */ { FP32_1(0),        FP32_NORM_MAX(1), FP32_1(0),        FP32_NORM_MAX(1), FP32_1(0),        FP32_1(1),        FP32_NORM_MIN(1), FP32_NORM_MIN(1) } },
+            { /* =>      */ { FP32_NORM_MAX(0), FP32_NORM_MAX(1), FP32_NORM_MAX(1), FP32_NORM_MAX(0), FP32_NORM_MIN(0), FP32_NORM_MIN(1), FP32_NORM_MIN(1), FP32_NORM_MIN(0) } },
+              /*mxcsr:in */ 0,
+              /*128:out  */ 0,
+              /*256:out  */ 0,
+              /*xcpt?    */ false, false },
+    /** @todo More Normals. */
+    /** @todo Denormals, Overflow/Precision, Invalids, Underflow, Precision;
      *        Rounding, FZ etc. */
     };