VirtualBox

Ignore:
Timestamp:
Aug 25, 2024 1:39:38 PM (3 months ago)
Author:
vboxsync
Message:

Disassembler/ARMv8: Implement decoding of the ldr/str (pre-/post-indexed) variant instructions and add testcases, bugref:10394

File:
1 edited

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Unmodified
Added
Removed
  • trunk/src/VBox/Disassembler/DisasmTables-armv8-a64.cpp

    r105857 r105858  
    792792
    793793/*
     794 * STP/LDP/STGP/LDPSW - pre-indexed variant.
     795 *
     796 * Note: The opc,L bitfields are concatenated to form an index.
     797 */
     798DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(LdStRegPairPreIndex)
     799 DIS_ARMV8_OP_EX(0x29800000, "stp",             OP_ARMV8_A64_STP,       DISOPTYPE_HARMLESS, DISARMV8INSNCLASS_F_FORCED_32BIT),
     800 DIS_ARMV8_OP_EX(0x29c00000, "ldp",             OP_ARMV8_A64_LDP,       DISOPTYPE_HARMLESS, DISARMV8INSNCLASS_F_FORCED_32BIT),
     801    INVALID_OPCODE,
     802    INVALID_OPCODE,
     803 DIS_ARMV8_OP_EX(0xa9800000, "stp",             OP_ARMV8_A64_STP,       DISOPTYPE_HARMLESS, DISARMV8INSNCLASS_F_FORCED_64BIT),
     804 DIS_ARMV8_OP_EX(0xa9c00000, "ldp",             OP_ARMV8_A64_LDP,       DISOPTYPE_HARMLESS, DISARMV8INSNCLASS_F_FORCED_64BIT),
     805    INVALID_OPCODE,
     806    INVALID_OPCODE,
     807DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(LdStRegPairPreIndex)
     808    DIS_ARMV8_INSN_DECODE(kDisParmParseReg,            0,  5, 0 /*idxParam*/),
     809    DIS_ARMV8_INSN_DECODE(kDisParmParseReg,           10,  5, 1 /*idxParam*/),
     810    DIS_ARMV8_INSN_DECODE(kDisParmParseReg,            5,  5, 2 /*idxParam*/),
     811    DIS_ARMV8_INSN_DECODE(kDisParmParseSImmMemOff,    15,  7, 2 /*idxParam*/),
     812    DIS_ARMV8_INSN_DECODE(kDisParmParseSetPreIndexed,  0,  0, 2 /*idxParam*/),
     813DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END_PARAMS_3(LdStRegPairPreIndex, 0xffc00000 /*fFixedInsn*/, 0 /*fClass*/,
     814                                                kDisArmV8OpcDecodeCollate,
     815                                                RT_BIT_32(22) | RT_BIT_32(30) | RT_BIT_32(31), 22,
     816                                                kDisArmv8OpParmGpr, kDisArmv8OpParmGpr, kDisArmv8OpParmAddrInGpr);
     817
     818
     819/*
     820 * STP/LDP/STGP/LDPSW - post-indexed variant.
     821 *
     822 * Note: The opc,L bitfields are concatenated to form an index.
     823 */
     824DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(LdStRegPairPostIndex)
     825 DIS_ARMV8_OP_EX(0x28800000, "stp",             OP_ARMV8_A64_STP,       DISOPTYPE_HARMLESS, DISARMV8INSNCLASS_F_FORCED_32BIT),
     826 DIS_ARMV8_OP_EX(0x28c00000, "ldp",             OP_ARMV8_A64_LDP,       DISOPTYPE_HARMLESS, DISARMV8INSNCLASS_F_FORCED_32BIT),
     827    INVALID_OPCODE,
     828    INVALID_OPCODE,
     829 DIS_ARMV8_OP_EX(0xa8800000, "stp",             OP_ARMV8_A64_STP,       DISOPTYPE_HARMLESS, DISARMV8INSNCLASS_F_FORCED_64BIT),
     830 DIS_ARMV8_OP_EX(0xa8c00000, "ldp",             OP_ARMV8_A64_LDP,       DISOPTYPE_HARMLESS, DISARMV8INSNCLASS_F_FORCED_64BIT),
     831    INVALID_OPCODE,
     832    INVALID_OPCODE,
     833DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(LdStRegPairPostIndex)
     834    DIS_ARMV8_INSN_DECODE(kDisParmParseReg,             0,  5, 0 /*idxParam*/),
     835    DIS_ARMV8_INSN_DECODE(kDisParmParseReg,            10,  5, 1 /*idxParam*/),
     836    DIS_ARMV8_INSN_DECODE(kDisParmParseReg,             5,  5, 2 /*idxParam*/),
     837    DIS_ARMV8_INSN_DECODE(kDisParmParseSImmMemOff,     15,  7, 2 /*idxParam*/),
     838    DIS_ARMV8_INSN_DECODE(kDisParmParseSetPostIndexed,  0,  0, 2 /*idxParam*/),
     839DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END_PARAMS_3(LdStRegPairPostIndex, 0xffc00000 /*fFixedInsn*/, 0 /*fClass*/,
     840                                                kDisArmV8OpcDecodeCollate,
     841                                                RT_BIT_32(22) | RT_BIT_32(30) | RT_BIT_32(31), 22,
     842                                                kDisArmv8OpParmGpr, kDisArmv8OpParmGpr, kDisArmv8OpParmAddrInGpr);
     843
     844
     845/*
    794846 * C4.1.94 - Loads and Stores - Load/Store register pair variants
    795847 *
     
    805857DIS_ARMV8_DECODE_MAP_DEFINE_BEGIN(LdStRegPair)
    806858    DIS_ARMV8_DECODE_MAP_INVALID_ENTRY,             /** @todo */
    807     DIS_ARMV8_DECODE_MAP_INVALID_ENTRY,             /** @todo */
     859    DIS_ARMV8_DECODE_MAP_ENTRY(LdStRegPairPostIndex),
    808860    DIS_ARMV8_DECODE_MAP_ENTRY(LdStRegPairOff),
    809     DIS_ARMV8_DECODE_MAP_INVALID_ENTRY,             /** @todo */
     861    DIS_ARMV8_DECODE_MAP_ENTRY(LdStRegPairPreIndex),
    810862DIS_ARMV8_DECODE_MAP_DEFINE_END(LdStRegPair, RT_BIT_32(23) | RT_BIT_32(24), 23);
    811863
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