VirtualBox

Changeset 105900 in vbox for trunk/src/VBox/ValidationKit


Ignore:
Timestamp:
Aug 29, 2024 9:40:15 AM (5 months ago)
Author:
vboxsync
Message:

ValidationKit/bootsectors: bugref:10658 SIMD FP testcase: [v]hsubpd (W.I.P)

Location:
trunk/src/VBox/ValidationKit/bootsectors
Files:
2 edited

Legend:

Unmodified
Added
Removed

  • trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-4-template.mac

    r105744 r105900  
    329329
    330330;
     331;; [v]hsubpd
     332;
     333EMIT_INSTR_PLUS_ICEBP       hsubpd, XMM1, XMM2
     334EMIT_INSTR_PLUS_ICEBP       hsubpd, XMM1, FSxBX
     335EMIT_INSTR_PLUS_ICEBP_C64   hsubpd, XMM8, XMM9
     336EMIT_INSTR_PLUS_ICEBP_C64   hsubpd, XMM8, FSxBX
     337
     338EMIT_INSTR_PLUS_ICEBP       vhsubpd, XMM1, XMM2, XMM3
     339EMIT_INSTR_PLUS_ICEBP       vhsubpd, XMM1, XMM2, FSxBX
     340EMIT_INSTR_PLUS_ICEBP_C64   vhsubpd, XMM8, XMM9, XMM10
     341EMIT_INSTR_PLUS_ICEBP_C64   vhsubpd, XMM8, XMM9, FSxBX
     342
     343EMIT_INSTR_PLUS_ICEBP       vhsubpd, YMM1, YMM2, YMM3
     344EMIT_INSTR_PLUS_ICEBP       vhsubpd, YMM1, YMM2, FSxBX
     345EMIT_INSTR_PLUS_ICEBP_C64   vhsubpd, YMM8, YMM9, YMM10
     346EMIT_INSTR_PLUS_ICEBP_C64   vhsubpd, YMM8, YMM9, FSxBX
     347
     348;
    331349;; [v]mulps
    332350;

  • trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-4.c32

    r105899 r105900  
    60486048        { bs3CpuInstr4_vhsubps_YMM8_YMM9_YMM10_icebp_c64, 255, RM_REG, T_AVX_256, 8, 9, 10,  RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
    60496049        { bs3CpuInstr4_vhsubps_YMM8_YMM9_FSxBX_icebp_c64, 255, RM_MEM, T_AVX_256, 8, 9, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
     6050    };
     6051
     6052    static BS3CPUINSTR4_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR4_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64);
     6053    unsigned const                         iTest       = BS3CPUINSTR4_TEST_MODES_INDEX(bMode);
     6054    return bs3CpuInstr4_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests,
     6055                                        g_aXcptConfig2, RT_ELEMENTS(g_aXcptConfig2));
     6056}
     6057
     6058
     6059/*
     6060 * [V]HSUBPD.
     6061 */
     6062BS3_DECL_FAR(uint8_t) bs3CpuInstr4_v_hsubpd(uint8_t bMode)
     6063{
     6064    static BS3CPUINSTR4_TEST1_VALUES_PD_T const s_aValues[] =
     6065    {
     6066    /*
     6067     * Zero.
     6068     */
     6069    /* 0*/{ { /*src2     */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } },
     6070            { /*src1     */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } },
     6071            { /* =>      */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } },
     6072              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
     6073              /*128:out  */ X86_MXCSR_XCPT_MASK,
     6074              /*256:out  */ X86_MXCSR_XCPT_MASK,
     6075              /*xcpt?    */ false, false },
     6076          { { /*src2     */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } },
     6077            { /*src1     */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } },
     6078            { /* =>      */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } },
     6079              /*mxcsr:in */ 0,
     6080              /*128:out  */ 0,
     6081              /*256:out  */ 0,
     6082              /*xcpt?    */ false, false },
     6083          { { /*src2     */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } },
     6084            { /*src1     */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } },
     6085            { /* =>      */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } },
     6086              /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
     6087              /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
     6088              /*256:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
     6089              /*xcpt?    */ false, false },
     6090          { { /*src2     */ { FP64_0(1), FP64_0(0), FP64_0(0), FP64_0(0) } },
     6091            { /*src1     */ { FP64_0(1), FP64_0(0), FP64_0(0), FP64_0(0) } },
     6092            { /* =>      */ { FP64_0(1), FP64_0(1), FP64_0(0), FP64_0(0) } },
     6093              /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO,
     6094              /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO,
     6095              /*256:out  */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO,
     6096              /*xcpt?    */ false, false },
     6097          { { /*src2     */ { FP64_0(1), FP64_0(0), FP64_0(1), FP64_0(1) } },
     6098            { /*src1     */ { FP64_0(0), FP64_0(0), FP64_0(1), FP64_0(0) } },
     6099            { /* =>      */ { FP64_0(0), FP64_0(1), FP64_0(1), FP64_0(0) } },
     6100              /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
     6101              /*128:out  */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
     6102              /*256:out  */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
     6103              /*xcpt?    */ false, false },
     6104          { { /*src2     */ { FP64_0(0), FP64_0(1), FP64_0(0), FP64_0(1) } },
     6105            { /*src1     */ { FP64_0(0), FP64_0(1), FP64_0(0), FP64_0(1) } },
     6106            { /* =>      */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } },
     6107              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
     6108              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
     6109              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
     6110              /*xcpt?    */ false, false },
     6111    /** @todo Infinity; Overflow/Precision; Denormals; Normals; Invalids; Underflow,
     6112     *        Precision; Rounding, FZ etc. */
     6113    };
     6114
     6115    static BS3CPUINSTR4_TEST1_T const s_aTests16[] =
     6116    {
     6117        { bs3CpuInstr4_hsubpd_XMM1_XMM2_icebp_c16,  255, RM_REG, T_SSE, 1, 1, 2,   RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
     6118        { bs3CpuInstr4_hsubpd_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE, 1, 1, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
     6119
     6120        { bs3CpuInstr4_vhsubpd_XMM1_XMM2_XMM3_icebp_c16,  255, RM_REG, T_AVX_128, 1, 2, 3,   RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
     6121        { bs3CpuInstr4_vhsubpd_XMM1_XMM2_FSxBX_icebp_c16, 255, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
     6122
     6123        { bs3CpuInstr4_vhsubpd_YMM1_YMM2_YMM3_icebp_c16,  255, RM_REG, T_AVX_256, 1, 2, 3,   RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
     6124        { bs3CpuInstr4_vhsubpd_YMM1_YMM2_FSxBX_icebp_c16, 255, RM_MEM, T_AVX_256, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
     6125    };
     6126    static BS3CPUINSTR4_TEST1_T const s_aTests32[] =
     6127    {
     6128        { bs3CpuInstr4_hsubpd_XMM1_XMM2_icebp_c32,  255, RM_REG, T_SSE, 1, 1, 2,   RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
     6129        { bs3CpuInstr4_hsubpd_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE, 1, 1, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
     6130
     6131        { bs3CpuInstr4_vhsubpd_XMM1_XMM2_XMM3_icebp_c32,  255, RM_REG, T_AVX_128, 1, 2, 3,   RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
     6132        { bs3CpuInstr4_vhsubpd_XMM1_XMM2_FSxBX_icebp_c32, 255, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
     6133
     6134        { bs3CpuInstr4_vhsubpd_YMM1_YMM2_YMM3_icebp_c32,  255, RM_REG, T_AVX_256, 1, 2, 3,   RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
     6135        { bs3CpuInstr4_vhsubpd_YMM1_YMM2_FSxBX_icebp_c32, 255, RM_MEM, T_AVX_256, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
     6136    };
     6137    static BS3CPUINSTR4_TEST1_T const s_aTests64[] =
     6138    {
     6139        { bs3CpuInstr4_hsubpd_XMM1_XMM2_icebp_c64,  255, RM_REG, T_SSE, 1, 1, 2,   RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
     6140        { bs3CpuInstr4_hsubpd_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE, 1, 1, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
     6141
     6142        { bs3CpuInstr4_vhsubpd_XMM1_XMM2_XMM3_icebp_c64,  255, RM_REG, T_AVX_128, 1, 2, 3,   RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
     6143        { bs3CpuInstr4_vhsubpd_XMM1_XMM2_FSxBX_icebp_c64, 255, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
     6144
     6145        { bs3CpuInstr4_vhsubpd_YMM1_YMM2_YMM3_icebp_c64,  255, RM_REG, T_AVX_256, 1, 2, 3,   RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
     6146        { bs3CpuInstr4_vhsubpd_YMM1_YMM2_FSxBX_icebp_c64, 255, RM_MEM, T_AVX_256, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
     6147
     6148        { bs3CpuInstr4_hsubpd_XMM8_XMM9_icebp_c64,  255, RM_REG, T_SSE, 8, 8, 9,   RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
     6149        { bs3CpuInstr4_hsubpd_XMM8_FSxBX_icebp_c64, 255, RM_MEM, T_SSE, 8, 8, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
     6150
     6151        { bs3CpuInstr4_vhsubpd_XMM8_XMM9_XMM10_icebp_c64, 255, RM_REG, T_AVX_128, 8, 9, 10,  RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
     6152        { bs3CpuInstr4_vhsubpd_XMM8_XMM9_FSxBX_icebp_c64, 255, RM_MEM, T_AVX_128, 8, 9, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
     6153        { bs3CpuInstr4_vhsubpd_YMM8_YMM9_YMM10_icebp_c64, 255, RM_REG, T_AVX_256, 8, 9, 10,  RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
     6154        { bs3CpuInstr4_vhsubpd_YMM8_YMM9_FSxBX_icebp_c64, 255, RM_MEM, T_AVX_256, 8, 9, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
    60506155    };
    60516156
    … …  
    78978002        { "[v]subsd",       bs3CpuInstr4_v_subsd,  0 },
    78988003        { "[v]hsubps",      bs3CpuInstr4_v_hsubps, 0 },
     8004        { "[v]hsubpd",      bs3CpuInstr4_v_hsubpd, 0 },
    78998005        { "[v]mulps",       bs3CpuInstr4_v_mulps,  0 },
    79008006        { "[v]mulpd",       bs3CpuInstr4_v_mulpd,  0 },
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