Changeset 105908 in vbox for trunk/src/VBox

Timestamp:

Aug 30, 2024 9:27:06 AM (3 months ago)

Author:

vboxsync

Message:

ValidationKit/bootsectors: bugref:10658 SIMD FP testcase: [v]hsubpd (W.I.P)

File:

• trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-4.c32 (modified) (1 diff)

trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-4.c32

@@ -6109 +6109 @@
               /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
               /*xcpt?    */ false, false },
-    /** @todo Infinity; Overflow/Precision; Denormals; Normals; Invalids; Underflow,
+    /*
+     * Infinity.
+     */
+    /* 6*/{ { /*src2     */ { FP64_INF(0), FP64_INF(1), FP64_INF(0), FP64_INF(1) } },
+            { /*src1     */ { FP64_INF(1), FP64_INF(0), FP64_0(0),   FP64_0(0)   } },
+            { /* =>      */ { FP64_INF(1), FP64_INF(0), FP64_0(0),   FP64_INF(0) } },
+              /*mxcsr:in */ X86_MXCSR_IM,
+              /*128:out  */ X86_MXCSR_IM,
+              /*256:out  */ X86_MXCSR_IM,
+              /*xcpt?    */ false, false },
+          { { /*src2     */ { FP64_0(0), FP64_0(0), FP64_INF(1), FP64_INF(1)  } },
+            { /*src1     */ { FP64_0(0), FP64_0(0), FP64_INF(1), FP64_INF(0)  } },
+            { /* =>      */ { FP64_0(0), FP64_0(0), FP64_INF(1), FP64_QNAN(1) } },
+              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
+              /*128:out  */ X86_MXCSR_XCPT_MASK,
+              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,
+              /*xcpt?    */ false, false },
+          { { /*src2     */ { FP64_INF(0), FP64_INF(1), FP64_INF(0), FP64_INF(1) } },
+            { /*src1     */ { FP64_INF(1), FP64_INF(0), FP64_0(0),   FP64_0(0)   } },
+            { /* =>      */ { FP64_INF(1), FP64_INF(0), FP64_0(0),   FP64_INF(0) } },
+              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ,
+              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ,
+              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ,
+              /*xcpt?    */ false, false },
+          { { /*src2     */ { FP64_INF(1),  FP64_INF(1),  FP64_INF(0), FP64_0(0)   } },
+            { /*src1     */ { FP64_INF(0),  FP64_INF(0),  FP64_INF(1), FP64_0(0)   } },
+            { /* =>      */ { FP64_QNAN(1),  FP64_QNAN(1), FP64_INF(1), FP64_INF(0) } },
+              /*mxcsr:in */ X86_MXCSR_RC_ZERO,
+              /*128:out  */ X86_MXCSR_RC_ZERO | X86_MXCSR_IE,
+              /*256:out  */ X86_MXCSR_RC_ZERO | X86_MXCSR_IE,
+              /*xcpt?    */ true, true },
+          { { /*src2     */ { FP64_INF(0),  FP64_QNAN(1), FP64_INF(1),  FP64_QNAN(0) } },
+            { /*src1     */ { FP64_INF(0),  FP64_QNAN(0), FP64_INF(1),  FP64_QNAN(0) } },
+            { /* =>      */ { FP64_QNAN(0), FP64_QNAN(1), FP64_QNAN(0), FP64_QNAN(0) } },
+              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_UP,
+              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_UP,
+              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_UP,
+              /*xcpt?    */ false, false },
+    /** @todo Overflow/Precision; Denormals; Normals; Invalids; Underflow,
      *        Precision; Rounding, FZ etc. */
     };