Changeset 105912 in vbox
- Timestamp:
- Aug 30, 2024 4:24:00 PM (5 months ago)
- File:
-
- 1 edited
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trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-4.c32
r105908 r105912 1668 1668 /*256:out */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_RC_ZERO | X86_MXCSR_OE | X86_MXCSR_PE, 1669 1669 /*xcpt? */ false, false }, 1670 { { /*src2 */ { FP32_NORM_MAX(0), FP32_NORM_MIN(1), FP32_0(0), FP32_NORM_MAX(0), FP32_NORM_MAX(0), FP32_NORM_MIN(1),FP32_0(0), FP32_NORM_MAX(0) } },1671 { /*src1 */ { FP32_NORM_MAX(0), FP32_NORM_MIN(1), FP32_0(0), FP32_NORM_MAX(0), FP32_NORM_MAX(0), FP32_NORM_MIN(1),FP32_0(0), FP32_NORM_MAX(0) } },1672 { /* => */ { FP32_INF(0), FP32_V(1, 0, 2), FP32_0(0), FP32_INF(0), FP32_INF(0), FP32_V(1, 0, 2), FP32_0(0), FP32_INF(0)} },1670 { { /*src2 */ { FP32_NORM_MAX(0), FP32_NORM_MIN(1), FP32_0(0), FP32_NORM_MAX(0), FP32_NORM_MAX(0), FP32_NORM_MIN(1), FP32_0(0), FP32_NORM_MAX(0) } }, 1671 { /*src1 */ { FP32_NORM_MAX(0), FP32_NORM_MIN(1), FP32_0(0), FP32_NORM_MAX(0), FP32_NORM_MAX(0), FP32_NORM_MIN(1), FP32_0(0), FP32_NORM_MAX(0) } }, 1672 { /* => */ { FP32_INF(0), FP32_V(1, 0, FP32_EXP_NORM_MIN + 1), FP32_0(0), FP32_INF(0), FP32_INF(0), FP32_V(1, 0, FP32_EXP_NORM_MIN + 1), FP32_0(0), FP32_INF(0) } }, 1673 1673 /*mxcsr:in */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP, 1674 1674 /*128:out */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP | X86_MXCSR_OE | X86_MXCSR_PE, 1675 1675 /*256:out */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP | X86_MXCSR_OE | X86_MXCSR_PE, 1676 1676 /*xcpt? */ false, false }, 1677 { { /*src2 */ { FP32_NORM_MIN(1), FP32_NORM_MAX(0), FP32_NORM_MAX(0), FP32_0(0), FP32_0(1), FP32_NORM_MAX(0), FP32_NORM_MAX(0), FP32_NORM_MIN(1)} },1678 { /*src1 */ { FP32_NORM_MIN(1), FP32_NORM_MAX(0), FP32_NORM_MAX(1), FP32_0(0), FP32_0(1), FP32_NORM_MAX(1), FP32_NORM_MAX(0), FP32_NORM_MIN(1)} },1679 { /* => */ { FP32_V(1, 0, 2), FP32_NORM_MAX(0), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(1), FP32_NORM_MAX(0), FP32_V(1, 0, 2)} },1677 { { /*src2 */ { FP32_NORM_MIN(1), FP32_NORM_MAX(0), FP32_NORM_MAX(0), FP32_0(0), FP32_0(1), FP32_NORM_MAX(0), FP32_NORM_MAX(0), FP32_NORM_MIN(1) } }, 1678 { /*src1 */ { FP32_NORM_MIN(1), FP32_NORM_MAX(0), FP32_NORM_MAX(1), FP32_0(0), FP32_0(1), FP32_NORM_MAX(1), FP32_NORM_MAX(0), FP32_NORM_MIN(1) } }, 1679 { /* => */ { FP32_V(1, 0, FP32_EXP_NORM_MIN + 1), FP32_NORM_MAX(0), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(1), FP32_NORM_MAX(0), FP32_V(1, 0, FP32_EXP_NORM_MIN + 1) } }, 1680 1680 /*mxcsr:in */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 1681 1681 /*128:out */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN | X86_MXCSR_OE | X86_MXCSR_PE, … … 1748 1748 /*256:out */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, 1749 1749 /*xcpt? */ false, false }, 1750 { { /*src2 */ { FP32_NORM_SAFE_INT_MIN(0), FP32_0(0), FP32_NORM_SAFE_INT_MIN(0), FP32_NORM_SAFE_INT_MIN(0), FP32_NORM_SAFE_INT_MIN(0), FP32_0(0), FP32_NORM_SAFE_INT_MIN(0), FP32_NORM_SAFE_INT_MIN(0)} },1751 { /*src1 */ { FP32_NORM_SAFE_INT_MIN(1), FP32_NORM_SAFE_INT_MIN(1), FP32_0(0), FP32_NORM_SAFE_INT_MIN(0), FP32_NORM_SAFE_INT_MIN(1), FP32_NORM_SAFE_INT_MIN(1), FP32_0(0), FP32_NORM_SAFE_INT_MIN(0)} },1752 { /* => */ { FP32_0(1), FP32_NORM_SAFE_INT_MIN(1), FP32_NORM_SAFE_INT_MIN(0), FP32_V(0, 0, 2), FP32_0(1), FP32_NORM_SAFE_INT_MIN(1), FP32_NORM_SAFE_INT_MIN(0), FP32_V(0, 0, 2)} },1750 { { /*src2 */ { FP32_NORM_SAFE_INT_MIN(0), FP32_0(0), FP32_NORM_SAFE_INT_MIN(0), FP32_NORM_SAFE_INT_MIN(0), FP32_NORM_SAFE_INT_MIN(0), FP32_0(0), FP32_NORM_SAFE_INT_MIN(0), FP32_NORM_SAFE_INT_MIN(0) } }, 1751 { /*src1 */ { FP32_NORM_SAFE_INT_MIN(1), FP32_NORM_SAFE_INT_MIN(1), FP32_0(0), FP32_NORM_SAFE_INT_MIN(0), FP32_NORM_SAFE_INT_MIN(1), FP32_NORM_SAFE_INT_MIN(1), FP32_0(0), FP32_NORM_SAFE_INT_MIN(0) } }, 1752 { /* => */ { FP32_0(1), FP32_NORM_SAFE_INT_MIN(1), FP32_NORM_SAFE_INT_MIN(0), FP32_V(0, 0, FP32_EXP_SAFE_INT_MIN + 1), FP32_0(1), FP32_NORM_SAFE_INT_MIN(1), FP32_NORM_SAFE_INT_MIN(0), FP32_V(0, 0, FP32_EXP_SAFE_INT_MIN + 1) } }, 1753 1753 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 1754 1754 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 1755 1755 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 1756 1756 /*xcpt? */ false, false }, 1757 { { /*src2 */ { FP32_V(0, 0x600000, 0x7e)/* 0.875*/, FP32_V(0, 0x3ce348, 0x90)/*193421.125*/, FP32_V(0, 0x6423f2, 0x92)/*934463.125*/, FP32_NORM_SAFE_INT_MIN(1), FP32_NORM_SAFE_INT_MIN(0),FP32_V(0, 0x16b43a, 0x93)/*1234567.25*/, FP32_V(0, 0x792318, 0x91)/*510232.75*/, FP32_V(0, 0x600000, 0x7e)/* 0.875*/ } },1758 { /*src1 */ { FP32_V(0, 0x769b50, 0x92)/*1010101.000*/, FP32_V(0, 0x430ebc, 0x91)/*399477.875*/, FP32_V(1, 0x0a19f0, 0x8f)/*-70707.875*/, FP32_NORM_SAFE_INT_MIN(1), FP32_NORM_SAFE_INT_MIN(0),FP32_V(0, 0x00c6d3, 0x94)/*2109876.75*/, FP32_V(1, 0x316740, 0x8e)/*-45415.25*/, FP32_V(0, 0x769b50, 0x92)/*1010101.000*/ } },1759 { /* => */ { FP32_V(0, 0x769b5e, 0x92)/*1010101.875*/, FP32_V(0, 0x10c030, 0x92)/*592899.000*/, FP32_V(0, 0x52e0b4, 0x92)/*863755.250*/, FP32_V(1, 0, 2), FP32_V(0, 0, 2),FP32_V(0, 0x4c20f0, 0x94)/*3344444.00*/, FP32_V(0, 0x62f630, 0x91)/*464817.50*/, FP32_V(0, 0x769b5e, 0x92)/*1010101.875*/ } },1757 { { /*src2 */ { FP32_V(0, 0x600000, 0x7e)/* 0.875*/, FP32_V(0, 0x3ce348, 0x90)/*193421.125*/, FP32_V(0, 0x6423f2, 0x92)/*934463.125*/, FP32_NORM_SAFE_INT_MIN(1), FP32_NORM_SAFE_INT_MIN(0), FP32_V(0, 0x16b43a, 0x93)/*1234567.25*/, FP32_V(0, 0x792318, 0x91)/*510232.75*/, FP32_V(0, 0x600000, 0x7e)/* 0.875*/ } }, 1758 { /*src1 */ { FP32_V(0, 0x769b50, 0x92)/*1010101.000*/, FP32_V(0, 0x430ebc, 0x91)/*399477.875*/, FP32_V(1, 0x0a19f0, 0x8f)/*-70707.875*/, FP32_NORM_SAFE_INT_MIN(1), FP32_NORM_SAFE_INT_MIN(0), FP32_V(0, 0x00c6d3, 0x94)/*2109876.75*/, FP32_V(1, 0x316740, 0x8e)/*-45415.25*/, FP32_V(0, 0x769b50, 0x92)/*1010101.000*/ } }, 1759 { /* => */ { FP32_V(0, 0x769b5e, 0x92)/*1010101.875*/, FP32_V(0, 0x10c030, 0x92)/*592899.000*/, FP32_V(0, 0x52e0b4, 0x92)/*863755.250*/, FP32_V(1, 0, FP32_EXP_SAFE_INT_MIN + 1), FP32_V(0, 0, FP32_EXP_SAFE_INT_MIN + 1), FP32_V(0, 0x4c20f0, 0x94)/*3344444.00*/, FP32_V(0, 0x62f630, 0x91)/*464817.50*/, FP32_V(0, 0x769b5e, 0x92)/*1010101.875*/ } }, 1760 1760 /*mxcsr:in */ X86_MXCSR_RC_DOWN, 1761 1761 /*128:out */ X86_MXCSR_RC_DOWN, … … 2047 2047 /*256:out */ X86_MXCSR_OE, 2048 2048 /*xcpt? */ true, true }, 2049 { { /*src2 */ { FP64_NORM_MAX(0), FP64_NORM_MIN(1), FP64_0(0), FP64_NORM_MAX(0) } },2050 { /*src1 */ { FP64_NORM_MAX(0), FP64_NORM_MIN(1), FP64_0(0), FP64_NORM_MAX(0) } },2051 { /* => */ { FP64_INF(0), FP64_V(1, 0, 2), FP64_0(0), FP64_INF(0) } },2049 { { /*src2 */ { FP64_NORM_MAX(0), FP64_NORM_MIN(1), FP64_0(0), FP64_NORM_MAX(0) } }, 2050 { /*src1 */ { FP64_NORM_MAX(0), FP64_NORM_MIN(1), FP64_0(0), FP64_NORM_MAX(0) } }, 2051 { /* => */ { FP64_INF(0), FP64_V(1, 0, FP32_EXP_NORM_MIN + 1), FP64_0(0), FP64_INF(0) } }, 2052 2052 /*mxcsr:in */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_DAZ | X86_MXCSR_FZ, 2053 2053 /*128:out */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_OE | X86_MXCSR_PE, 2054 2054 /*256:out */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_OE | X86_MXCSR_PE, 2055 2055 /*xcpt? */ false, false }, 2056 { { /*src2 */ { FP64_NORM_MIN(1), FP64_NORM_MAX(0), FP64_NORM_MAX(0), FP64_0(0) } },2057 { /*src1 */ { FP64_NORM_MIN(1), FP64_NORM_MAX(0), FP64_NORM_MAX(1), FP64_0(0) } },2058 { /* => */ { FP64_V(1, 0, 2), FP64_INF(0), FP64_0(0), FP64_0(0) } },2056 { { /*src2 */ { FP64_NORM_MIN(1), FP64_NORM_MAX(0), FP64_NORM_MAX(0), FP64_0(0) } }, 2057 { /*src1 */ { FP64_NORM_MIN(1), FP64_NORM_MAX(0), FP64_NORM_MAX(1), FP64_0(0) } }, 2058 { /* => */ { FP64_V(1, 0, FP32_EXP_NORM_MIN + 1), FP64_INF(0), FP64_0(0), FP64_0(0) } }, 2059 2059 /*mxcsr:in */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_FZ, 2060 2060 /*128:out */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_FZ | X86_MXCSR_OE | X86_MXCSR_PE, … … 2121 2121 /*256:out */ X86_MXCSR_FZ, 2122 2122 /*xcpt? */ false, false }, 2123 { { /*src2 */ { FP64_NORM_SAFE_INT_MIN(0), FP64_0(0), FP64_NORM_SAFE_INT_MIN(0), FP64_NORM_SAFE_INT_MIN(0) } },2124 { /*src1 */ { FP64_NORM_SAFE_INT_MIN(1), FP64_NORM_SAFE_INT_MIN(1), FP64_0(0), FP64_NORM_SAFE_INT_MIN(0) } },2125 { /* => */ { FP64_0(1), FP64_NORM_SAFE_INT_MIN(1), FP64_NORM_SAFE_INT_MIN(0), FP64_V(0, 0, 2)} },2123 { { /*src2 */ { FP64_NORM_SAFE_INT_MIN(0), FP64_0(0), FP64_NORM_SAFE_INT_MIN(0), FP64_NORM_SAFE_INT_MIN(0) } }, 2124 { /*src1 */ { FP64_NORM_SAFE_INT_MIN(1), FP64_NORM_SAFE_INT_MIN(1), FP64_0(0), FP64_NORM_SAFE_INT_MIN(0) } }, 2125 { /* => */ { FP64_0(1), FP64_NORM_SAFE_INT_MIN(1), FP64_NORM_SAFE_INT_MIN(0), FP64_V(0, 0, FP32_EXP_SAFE_INT_MIN + 1) } }, 2126 2126 /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 2127 2127 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 2128 2128 /*256:out */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 2129 2129 /*xcpt? */ false, false }, 2130 { { /*src2 */ { FP64_V(0, 0xc122186c3cfd0, 0x42d)/*123456789876543.25*/, FP64_0(0), FP64_0(0), FP64_NORM_SAFE_INT_MIN(1) } },2131 { /*src1 */ { FP64_V(0, 0xb88e0395d49b0, 0x42d)/*121098765432102.75*/, FP64_0(0), FP64_0(0), FP64_NORM_SAFE_INT_MIN(1) } },2132 { /* => */ { FP64_V(0, 0xbcd80e0108cc0, 0x42e)/*244555555308646.00*/, FP64_0(0), FP64_0(0), FP64_V(1, 0, 2)} },2130 { { /*src2 */ { FP64_V(0, 0xc122186c3cfd0, 0x42d)/*123456789876543.25*/, FP64_0(0), FP64_0(0), FP64_NORM_SAFE_INT_MIN(1) } }, 2131 { /*src1 */ { FP64_V(0, 0xb88e0395d49b0, 0x42d)/*121098765432102.75*/, FP64_0(0), FP64_0(0), FP64_NORM_SAFE_INT_MIN(1) } }, 2132 { /* => */ { FP64_V(0, 0xbcd80e0108cc0, 0x42e)/*244555555308646.00*/, FP64_0(0), FP64_0(0), FP64_V(1, 0, FP32_EXP_SAFE_INT_MIN + 1) } }, 2133 2133 /*mxcsr:in */ X86_MXCSR_RC_UP, 2134 2134 /*128:out */ X86_MXCSR_RC_UP, … … 3399 3399 /*256:out */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_RC_ZERO | X86_MXCSR_OE | X86_MXCSR_PE, 3400 3400 /*xcpt? */ false, false }, 3401 { { /*src2 */ { FP32_NORM_MAX(0), FP32_NORM_MAX(1), FP32_0(0), FP32_NORM_MIN(1), FP32_NORM_MAX(0), FP32_NORM_MAX(0), FP32_0(0), FP32_NORM_MAX(0) } },3402 { /*src1 */ { FP32_NORM_MAX(0), FP32_NORM_MAX(0), FP32_NORM_MIN(1), FP32_NORM_MIN(1), FP32_NORM_MIN(1), FP32_NORM_MAX(0), FP32_NORM_MIN(0), FP32_NORM_MAX(1) } },3403 { /* => */ { FP32_INF(0), FP32_V(1, 0, 2), FP32_0(0), FP32_NORM_MIN(1), FP32_NORM_MAX(0), FP32_V(1, FP32_FRAC_NORM_MAX - 1, FP32_EXP_NORM_MAX), FP32_INF(0), FP32_NORM_MAX(0) } },3401 { { /*src2 */ { FP32_NORM_MAX(0), FP32_NORM_MAX(1), FP32_0(0), FP32_NORM_MIN(1), FP32_NORM_MAX(0), FP32_NORM_MAX(0), FP32_0(0), FP32_NORM_MAX(0) } }, 3402 { /*src1 */ { FP32_NORM_MAX(0), FP32_NORM_MAX(0), FP32_NORM_MIN(1), FP32_NORM_MIN(1), FP32_NORM_MIN(1), FP32_NORM_MAX(0), FP32_NORM_MIN(0), FP32_NORM_MAX(1) } }, 3403 { /* => */ { FP32_INF(0), FP32_V(1, 0, FP32_EXP_NORM_MIN + 1), FP32_0(0), FP32_NORM_MIN(1), FP32_NORM_MAX(0), FP32_V(1, FP32_FRAC_NORM_MAX - 1, FP32_EXP_NORM_MAX), FP32_INF(0), FP32_NORM_MAX(0) } }, 3404 3404 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_RC_UP, 3405 3405 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_RC_UP | X86_MXCSR_OE | X86_MXCSR_PE, 3406 3406 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_RC_UP | X86_MXCSR_OE | X86_MXCSR_PE, 3407 3407 /*xcpt? */ false, false }, 3408 { { /*src2 */ { FP32_NORM_MAX(0), FP32_NORM_MAX(0), FP32_NORM_MAX(0), FP32_0(0), FP32_0(0), FP32_NORM_MAX(0),FP32_NORM_MIN(1), FP32_NORM_MIN(0) } },3409 { /*src1 */ { FP32_NORM_MIN(1), FP32_NORM_MIN(1), FP32_NORM_MIN(0), FP32_NORM_MIN(0), FP32_0(0), FP32_NORM_MAX(1),FP32_NORM_MIN(1), FP32_NORM_MIN(1) } },3410 { /* => */ { FP32_V(1, 0, 2), FP32_V(0, 0, 2), FP32_NORM_MAX(0), FP32_NORM_MAX(0), FP32_NORM_MAX(1), FP32_V(1, 0, 2), FP32_NORM_MAX(0), FP32_0(0) } },3408 { { /*src2 */ { FP32_NORM_MAX(0), FP32_NORM_MAX(0), FP32_NORM_MAX(0), FP32_0(0), FP32_0(0), FP32_NORM_MAX(0), FP32_NORM_MIN(1), FP32_NORM_MIN(0) } }, 3409 { /*src1 */ { FP32_NORM_MIN(1), FP32_NORM_MIN(1), FP32_NORM_MIN(0), FP32_NORM_MIN(0), FP32_0(0), FP32_NORM_MAX(1), FP32_NORM_MIN(1), FP32_NORM_MIN(1) } }, 3410 { /* => */ { FP32_V(1, 0, FP32_EXP_NORM_MIN + 1), FP32_V(0, 0, FP32_EXP_NORM_MIN + 1), FP32_NORM_MAX(0), FP32_NORM_MAX(0), FP32_NORM_MAX(1), FP32_V(1, 0, FP32_EXP_NORM_MIN + 1), FP32_NORM_MAX(0), FP32_0(0) } }, 3411 3411 /*mxcsr:in */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_RC_ZERO, 3412 3412 /*128:out */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_RC_ZERO | X86_MXCSR_OE | X86_MXCSR_PE, … … 3481 3481 { { /*src2 */ { FP32_V(0, 0x6423f2, 0x92)/* 934463.125*/, FP32_V(1, 0x0a19f0, 0x8f)/*-70707.875*/, FP32_NORM_SAFE_INT_MIN(1), FP32_NORM_SAFE_INT_MIN(1), FP32_NORM_SAFE_INT_MIN(0), FP32_NORM_SAFE_INT_MIN(0), FP32_V(0, 0x600000, 0x7e)/* 0.875*/, FP32_V(0, 0x769b50, 0x92)/*1010101.000*/ } }, 3482 3482 { /*src1 */ { FP32_V(0, 0x769b50, 0x92)/*1010101.000*/, FP32_V(0, 0x600000, 0x7e)/* 0.875*/, FP32_V(0, 0x430ebc, 0x91)/*399477.875*/, FP32_V(0, 0x3ce348, 0x90)/*193421.125*/, FP32_V(0, 0x16b43a, 0x93)/*1234567.25*/, FP32_V(0, 0x00c6d3, 0x94)/*2109876.75*/, FP32_V(0, 0x792318, 0x91)/*510232.750*/, FP32_V(1, 0x316740, 0x8e)/* -45415.250*/ } }, 3483 { /* => */ { FP32_V(0, 0x769b5e, 0x92)/*1010101.875*/, FP32_V(0, 0x10c030, 0x92)/*592899.000*/, FP32_V(0, 0x52e0b4, 0x92)/*863755.250*/, FP32_V(1, 0, 2), FP32_V(0, 0x4c20f0, 0x94)/*3344444.00*/, FP32_V(0, 0x62f630, 0x91)/*464817.50*/, FP32_V(0, 0, 2),FP32_V(0, 0x769b5e, 0x92)/*1010101.875*/ } },3483 { /* => */ { FP32_V(0, 0x769b5e, 0x92)/*1010101.875*/, FP32_V(0, 0x10c030, 0x92)/*592899.000*/, FP32_V(0, 0x52e0b4, 0x92)/*863755.250*/, FP32_V(1, 0, FP32_EXP_SAFE_INT_MIN + 1), FP32_V(0, 0x4c20f0, 0x94)/*3344444.00*/, FP32_V(0, 0x62f630, 0x91)/*464817.50*/, FP32_V(0, 0, FP32_EXP_SAFE_INT_MIN + 1), FP32_V(0, 0x769b5e, 0x92)/*1010101.875*/ } }, 3484 3484 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 3485 3485 /*128:out */ X86_MXCSR_XCPT_MASK, … … 3785 3785 /*256:out */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_RC_ZERO | X86_MXCSR_OE | X86_MXCSR_PE, 3786 3786 /*xcpt? */ false, false }, 3787 { { /*src2 */ { FP64_NORM_MAX(0), FP64_NORM_MAX(1), FP64_0(0), FP64_NORM_MIN(1) } },3788 { /*src1 */ { FP64_NORM_MAX(0), FP64_NORM_MAX(0), FP64_NORM_MIN(1), FP64_NORM_MIN(1) } },3789 { /* => */ { FP64_INF(0), FP64_0(0), FP64_V(1, 0, 2), FP64_NORM_MIN(1) } },3787 { { /*src2 */ { FP64_NORM_MAX(0), FP64_NORM_MAX(1), FP64_0(0), FP64_NORM_MIN(1) } }, 3788 { /*src1 */ { FP64_NORM_MAX(0), FP64_NORM_MAX(0), FP64_NORM_MIN(1), FP64_NORM_MIN(1) } }, 3789 { /* => */ { FP64_INF(0), FP64_0(0), FP64_V(1, 0, FP32_EXP_NORM_MIN + 1), FP64_NORM_MIN(1) } }, 3790 3790 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_RC_UP, 3791 3791 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_RC_UP | X86_MXCSR_OE | X86_MXCSR_PE, … … 3799 3799 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_RC_UP | X86_MXCSR_OE | X86_MXCSR_PE, 3800 3800 /*xcpt? */ false, false }, 3801 { { /*src2 */ { FP64_NORM_MAX(0), FP64_NORM_MAX(0), FP64_NORM_MAX(0),FP64_0(0) } },3802 { /*src1 */ { FP64_NORM_MIN(1), FP64_NORM_MIN(1), FP64_NORM_MIN(0),FP64_NORM_MIN(0) } },3803 { /* => */ { FP64_V(1, 0, 2), FP64_NORM_MAX(0), FP64_V(0, 0, 2), FP64_NORM_MAX(0) } },3801 { { /*src2 */ { FP64_NORM_MAX(0), FP64_NORM_MAX(0), FP64_NORM_MAX(0), FP64_0(0) } }, 3802 { /*src1 */ { FP64_NORM_MIN(1), FP64_NORM_MIN(1), FP64_NORM_MIN(0), FP64_NORM_MIN(0) } }, 3803 { /* => */ { FP64_V(1, 0, FP32_EXP_NORM_MIN + 1), FP64_NORM_MAX(0), FP64_V(0, 0, FP32_EXP_NORM_MIN + 1), FP64_NORM_MAX(0) } }, 3804 3804 /*mxcsr:in */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_RC_ZERO, 3805 3805 /*128:out */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_RC_ZERO | X86_MXCSR_OE | X86_MXCSR_PE, 3806 3806 /*256:out */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_RC_ZERO | X86_MXCSR_OE | X86_MXCSR_PE, 3807 3807 /*xcpt? */ false, false }, 3808 { { /*src2 */ { FP64_0(0), FP64_NORM_MAX(0), FP64_NORM_MIN(1), FP64_NORM_MIN(0) } },3809 { /*src1 */ { FP64_NORM_MAX(1), FP64_NORM_MAX(1), FP64_NORM_MIN(1), FP64_NORM_MIN(1) } },3810 { /* => */ { FP64_V(1, FP64_FRAC_NORM_MAX, FP64_EXP_NORM_MAX), FP64_NORM_MAX(0), FP64_V(1, 0, 2), FP64_0(0) } },3808 { { /*src2 */ { FP64_0(0), FP64_NORM_MAX(0), FP64_NORM_MIN(1), FP64_NORM_MIN(0) } }, 3809 { /*src1 */ { FP64_NORM_MAX(1), FP64_NORM_MAX(1), FP64_NORM_MIN(1), FP64_NORM_MIN(1) } }, 3810 { /* => */ { FP64_V(1, FP64_FRAC_NORM_MAX, FP64_EXP_NORM_MAX), FP64_NORM_MAX(0), FP64_V(1, 0, FP32_EXP_NORM_MIN + 1), FP64_0(0) } }, 3811 3811 /*mxcsr:in */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_RC_ZERO, 3812 3812 /*128:out */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_RC_ZERO | X86_MXCSR_OE | X86_MXCSR_PE, … … 3858 3858 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, 3859 3859 /*xcpt? */ false, false }, 3860 { { /*src2 */ { FP64_NORM_SAFE_INT_MIN(0), FP64_0(0), FP64_NORM_SAFE_INT_MIN(1), FP64_NORM_SAFE_INT_MIN(1)} },3861 { /*src1 */ { FP64_NORM_SAFE_INT_MIN(1), FP64_NORM_SAFE_INT_MIN(0), FP64_NORM_SAFE_INT_MIN(0), FP64_NORM_SAFE_INT_MIN(0)} },3862 { /* => */ { FP64_0(1), FP64_NORM_SAFE_INT_MIN(0), FP64_V(0, 0, 2), FP64_V(1, 0, 2)} },3860 { { /*src2 */ { FP64_NORM_SAFE_INT_MIN(0), FP64_0(0), FP64_NORM_SAFE_INT_MIN(1), FP64_NORM_SAFE_INT_MIN(1) } }, 3861 { /*src1 */ { FP64_NORM_SAFE_INT_MIN(1), FP64_NORM_SAFE_INT_MIN(0), FP64_NORM_SAFE_INT_MIN(0), FP64_NORM_SAFE_INT_MIN(0) } }, 3862 { /* => */ { FP64_0(1), FP64_NORM_SAFE_INT_MIN(0), FP64_V(0, 0, FP32_EXP_SAFE_INT_MIN + 1), FP64_V(1, 0, FP32_EXP_SAFE_INT_MIN + 1) } }, 3863 3863 /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 3864 3864 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 3865 3865 /*256:out */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 3866 3866 /*xcpt? */ false, false }, 3867 { { /*src2 */ { FP64_V(0, 0xc122186c3cfd0, 0x42d)/*123456789876543.25*/, FP64_V(1, 0xc122186c3cfd0, 0x42d)/*-123456789876543.25*/, FP64_NORM_SAFE_INT_MIN(1), FP64_NORM_SAFE_INT_MIN(1) } },3868 { /*src1 */ { FP64_V(0, 0xc122186c3cfd0, 0x42d)/*123456789876543.25*/, FP64_V(0, 0xb88e0395d49b0, 0x42d)/* 121098765432102.75*/, FP64_NORM_V0(0), FP64_NORM_V0(1) } },3869 { /* => */ { FP64_V(0, 0xbcd80e0108cc0, 0x42e)/*244555555308646.00*/, FP64_0(0), FP64_0(0), FP64_V(1, 0, 2)} },3867 { { /*src2 */ { FP64_V(0, 0xc122186c3cfd0, 0x42d)/*123456789876543.25*/, FP64_V(1, 0xc122186c3cfd0, 0x42d)/*-123456789876543.25*/, FP64_NORM_SAFE_INT_MIN(1), FP64_NORM_SAFE_INT_MIN(1) } }, 3868 { /*src1 */ { FP64_V(0, 0xc122186c3cfd0, 0x42d)/*123456789876543.25*/, FP64_V(0, 0xb88e0395d49b0, 0x42d)/* 121098765432102.75*/, FP64_NORM_V0(0), FP64_NORM_V0(1) } }, 3869 { /* => */ { FP64_V(0, 0xbcd80e0108cc0, 0x42e)/*244555555308646.00*/, FP64_0(0), FP64_0(0), FP64_V(1, 0, FP32_EXP_SAFE_INT_MIN + 1) } }, 3870 3870 /*mxcsr:in */ X86_MXCSR_RC_UP, 3871 3871 /*128:out */ X86_MXCSR_RC_UP, … … 4170 4170 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_OE | X86_MXCSR_PE, 4171 4171 /*xcpt? */ false, false }, 4172 { { /*src2 */ { FP32_NORM_MAX(0), FP32_NORM_MIN(1), FP32_0(0), FP32_NORM_MAX(0), FP32_0(0), FP32_V(1, 0, 2), FP32_NORM_MIN(1), FP32_NORM_MAX(0) } },4173 { /*src1 */ { FP32_NORM_MAX(1), FP32_NORM_MAX(0), FP32_0(0), FP32_NORM_MAX(1), FP32_0(0), FP32_NORM_MIN(1), FP32_NORM_MIN(1), FP32_NORM_MAX(0) } },4174 { /* => */ { FP32_NORM_MAX(1), FP32_NORM_MAX(0), FP32_0(0), FP32_NORM_MAX(1), FP32_0(0), FP32_NORM_MIN(0), FP32_0(0), FP32_0(0) } },4172 { { /*src2 */ { FP32_NORM_MAX(0), FP32_NORM_MIN(1), FP32_0(0), FP32_NORM_MAX(0), FP32_0(0), FP32_V(1, 0, FP32_EXP_NORM_MIN + 1), FP32_NORM_MIN(1), FP32_NORM_MAX(0) } }, 4173 { /*src1 */ { FP32_NORM_MAX(1), FP32_NORM_MAX(0), FP32_0(0), FP32_NORM_MAX(1), FP32_0(0), FP32_NORM_MIN(1), FP32_NORM_MIN(1), FP32_NORM_MAX(0) } }, 4174 { /* => */ { FP32_NORM_MAX(1), FP32_NORM_MAX(0), FP32_0(0), FP32_NORM_MAX(1), FP32_0(0), FP32_NORM_MIN(0), FP32_0(0), FP32_0(0) } }, 4175 4175 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_OM | X86_MXCSR_PM, 4176 4176 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_OE | X86_MXCSR_PE, 4177 4177 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_OE | X86_MXCSR_PE, 4178 4178 /*xcpt? */ false, false }, 4179 { { /*src2 */ { FP32_V(1, 0, 2), FP32_NORM_MAX(0), FP32_NORM_MAX(0), FP32_0(0), FP32_0(1), FP32_NORM_MAX(0), FP32_NORM_MAX(0), FP32_V(1, 0, 2) } },4180 { /*src1 */ { FP32_NORM_MIN(1), FP32_NORM_MAX(0), FP32_NORM_MAX(1), FP32_0(0), FP32_0(1), FP32_NORM_MAX(1), FP32_NORM_MAX(1), FP32_NORM_MIN(1) } },4181 { /* => */ { FP32_NORM_MIN(0), FP32_0(0), FP32_NORM_MAX(1), FP32_0(0), FP32_0(0), FP32_NORM_MAX(1), FP32_NORM_MAX(1), FP32_NORM_MIN(0) } },4179 { { /*src2 */ { FP32_V(1, 0, FP32_EXP_NORM_MIN + 1), FP32_NORM_MAX(0), FP32_NORM_MAX(0), FP32_0(0), FP32_0(1), FP32_NORM_MAX(0), FP32_NORM_MAX(0), FP32_V(1, 0, 2) } }, 4180 { /*src1 */ { FP32_NORM_MIN(1), FP32_NORM_MAX(0), FP32_NORM_MAX(1), FP32_0(0), FP32_0(1), FP32_NORM_MAX(1), FP32_NORM_MAX(1), FP32_NORM_MIN(1) } }, 4181 { /* => */ { FP32_NORM_MIN(0), FP32_0(0), FP32_NORM_MAX(1), FP32_0(0), FP32_0(0), FP32_NORM_MAX(1), FP32_NORM_MAX(1), FP32_NORM_MIN(0) } }, 4182 4182 /*mxcsr:in */ X86_MXCSR_RC_ZERO | X86_MXCSR_OM | X86_MXCSR_PM, 4183 4183 /*128:out */ X86_MXCSR_RC_ZERO | X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_OE | X86_MXCSR_PE, … … 4250 4250 /*256:out */ X86_MXCSR_RC_UP, 4251 4251 /*xcpt? */ false, false }, 4252 { { /*src2 */ { FP32_NORM_SAFE_INT_MIN(0), FP32_0(0), FP32_NORM_SAFE_INT_MIN(0), FP32_NORM_SAFE_INT_MIN(0), FP32_NORM_SAFE_INT_MIN(0), FP32_0(1), FP32_NORM_SAFE_INT_MIN(1), FP32_NORM_SAFE_INT_MIN(1) } },4253 { /*src1 */ { FP32_NORM_SAFE_INT_MIN(0), FP32_NORM_SAFE_INT_MIN(1), FP32_0(0), FP32_V(0, 0, 2),FP32_NORM_SAFE_INT_MIN(0), FP32_NORM_SAFE_INT_MIN(1), FP32_0(0), FP32_NORM_SAFE_INT_MIN(1) } },4254 { /* => */ { FP32_0(0), FP32_NORM_SAFE_INT_MIN(1), FP32_NORM_SAFE_INT_MIN(1), FP32_NORM_SAFE_INT_MIN(0), FP32_0(0), FP32_NORM_SAFE_INT_MIN(1), FP32_NORM_SAFE_INT_MIN(0), FP32_0(0) } },4252 { { /*src2 */ { FP32_NORM_SAFE_INT_MIN(0), FP32_0(0), FP32_NORM_SAFE_INT_MIN(0), FP32_NORM_SAFE_INT_MIN(0), FP32_NORM_SAFE_INT_MIN(0), FP32_0(1), FP32_NORM_SAFE_INT_MIN(1), FP32_NORM_SAFE_INT_MIN(1) } }, 4253 { /*src1 */ { FP32_NORM_SAFE_INT_MIN(0), FP32_NORM_SAFE_INT_MIN(1), FP32_0(0), FP32_V(0, 0, FP32_EXP_SAFE_INT_MIN + 1), FP32_NORM_SAFE_INT_MIN(0), FP32_NORM_SAFE_INT_MIN(1), FP32_0(0), FP32_NORM_SAFE_INT_MIN(1) } }, 4254 { /* => */ { FP32_0(0), FP32_NORM_SAFE_INT_MIN(1), FP32_NORM_SAFE_INT_MIN(1), FP32_NORM_SAFE_INT_MIN(0), FP32_0(0), FP32_NORM_SAFE_INT_MIN(1), FP32_NORM_SAFE_INT_MIN(0), FP32_0(0) } }, 4255 4255 /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, 4256 4256 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, 4257 4257 /*256:out */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, 4258 4258 /*xcpt? */ false, false }, 4259 { { /*src2 */ { FP32_V(0, 0x600000, 0x7e)/* 0.875*/, FP32_V(0, 0x3ce348, 0x90)/*193421.125*/, FP32_V(1, 0x0a19f0, 0x8f)/*-70707.875*/, FP32_NORM_SAFE_INT_MIN(1), FP32_NORM_SAFE_INT_MIN(0),FP32_V(0, 0x00c6d3, 0x94)/*2109876.75*/, FP32_V(0, 0x316740, 0x8e)/* 45415.25*/, FP32_V(0, 0x600000, 0x7e)/* 0.875*/ } },4260 { /*src1 */ { FP32_V(0, 0x769b5e, 0x92)/*1010101.875*/, FP32_V(0, 0x10c030, 0x92)/*592899.000*/, FP32_V(0, 0x52e0b4, 0x92)/*863755.250*/, FP32_NORM_SAFE_INT_MIN(0), FP32_NORM_SAFE_INT_MIN(1),FP32_V(0, 0x4c20f0, 0x94)/*3344444.00*/, FP32_V(0, 0x792318, 0x91)/*510232.75*/, FP32_V(1, 0x769b50, 0x92)/*-1010101.000*/ } },4261 { /* => */ { FP32_V(0, 0x769b50, 0x92)/*1010101.000*/, FP32_V(0, 0x430ebc, 0x91)/*399477.875*/, FP32_V(0, 0x6423f2, 0x92)/*934463.125*/, FP32_V(0, 0, 2), FP32_V(1, 0, 2),FP32_V(0, 0x16b43a, 0x93)/*1234567.25*/, FP32_V(0, 0x62f630, 0x91)/*464817.50*/, FP32_V(1, 0x769b5e, 0x92)/*-1010101.875*/ } },4259 { { /*src2 */ { FP32_V(0, 0x600000, 0x7e)/* 0.875*/, FP32_V(0, 0x3ce348, 0x90)/*193421.125*/, FP32_V(1, 0x0a19f0, 0x8f)/*-70707.875*/, FP32_NORM_SAFE_INT_MIN(1), FP32_NORM_SAFE_INT_MIN(0), FP32_V(0, 0x00c6d3, 0x94)/*2109876.75*/, FP32_V(0, 0x316740, 0x8e)/* 45415.25*/, FP32_V(0, 0x600000, 0x7e)/* 0.875*/ } }, 4260 { /*src1 */ { FP32_V(0, 0x769b5e, 0x92)/*1010101.875*/, FP32_V(0, 0x10c030, 0x92)/*592899.000*/, FP32_V(0, 0x52e0b4, 0x92)/*863755.250*/, FP32_NORM_SAFE_INT_MIN(0), FP32_NORM_SAFE_INT_MIN(1), FP32_V(0, 0x4c20f0, 0x94)/*3344444.00*/, FP32_V(0, 0x792318, 0x91)/*510232.75*/, FP32_V(1, 0x769b50, 0x92)/*-1010101.000*/ } }, 4261 { /* => */ { FP32_V(0, 0x769b50, 0x92)/*1010101.000*/, FP32_V(0, 0x430ebc, 0x91)/*399477.875*/, FP32_V(0, 0x6423f2, 0x92)/*934463.125*/, FP32_V(0, 0, FP32_EXP_SAFE_INT_MIN + 1), FP32_V(1, 0, FP32_EXP_SAFE_INT_MIN + 1), FP32_V(0, 0x16b43a, 0x93)/*1234567.25*/, FP32_V(0, 0x62f630, 0x91)/*464817.50*/, FP32_V(1, 0x769b5e, 0x92)/*-1010101.875*/ } }, 4262 4262 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 4263 4263 /*128:out */ X86_MXCSR_XCPT_MASK, … … 4576 4576 /*256:out */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_FZ | X86_MXCSR_OE | X86_MXCSR_PE, 4577 4577 /*xcpt? */ false, false }, 4578 { { /*src2 */ { FP64_NORM_MAX(0), FP64_NORM_MIN(1), FP64_V(1, 0, 2), FP64_NORM_MIN(1) } },4579 { /*src1 */ { FP64_NORM_MAX(1), FP64_NORM_MAX(0), FP64_NORM_MIN(1), FP64_NORM_MIN(1) } },4580 { /* => */ { FP64_INF(1), FP64_NORM_MAX(0), FP64_NORM_MIN(0), FP64_0(0) } },4578 { { /*src2 */ { FP64_NORM_MAX(0), FP64_NORM_MIN(1), FP64_V(1, 0, FP32_EXP_NORM_MIN + 1), FP64_NORM_MIN(1) } }, 4579 { /*src1 */ { FP64_NORM_MAX(1), FP64_NORM_MAX(0), FP64_NORM_MIN(1), FP64_NORM_MIN(1) } }, 4580 { /* => */ { FP64_INF(1), FP64_NORM_MAX(0), FP64_NORM_MIN(0), FP64_0(0) } }, 4581 4581 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_OM | X86_MXCSR_PM, 4582 4582 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_OE | X86_MXCSR_PE, 4583 4583 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_OE | X86_MXCSR_PE, 4584 4584 /*xcpt? */ false, false }, 4585 { { /*src2 */ { FP64_V(1, 0, 2), FP64_NORM_MAX(0), FP64_NORM_MAX(0), FP64_V(1, 0, 2) } },4586 { /*src1 */ { FP64_NORM_MIN(1), FP64_NORM_MAX(1), FP64_NORM_MAX(1), FP64_NORM_MIN(1) } },4587 { /* => */ { FP64_NORM_MIN(0), FP64_NORM_MAX(1), FP64_NORM_MAX(1), FP64_NORM_MIN(0) } },4585 { { /*src2 */ { FP64_V(1, 0, FP32_EXP_NORM_MIN + 1), FP64_NORM_MAX(0), FP64_NORM_MAX(0), FP64_V(1, 0, 2) } }, 4586 { /*src1 */ { FP64_NORM_MIN(1), FP64_NORM_MAX(1), FP64_NORM_MAX(1), FP64_NORM_MIN(1) } }, 4587 { /* => */ { FP64_NORM_MIN(0), FP64_NORM_MAX(1), FP64_NORM_MAX(1), FP64_NORM_MIN(0) } }, 4588 4588 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_OM | X86_MXCSR_PM, 4589 4589 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_OE | X86_MXCSR_PE, … … 4649 4649 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_XCPT_MASK, 4650 4650 /*xcpt? */ false, false }, 4651 { { /*src2 */ { FP64_NORM_SAFE_INT_MAX(1), FP64_0(0), FP64_NORM_SAFE_INT_MIN(0), FP64_NORM_SAFE_INT_MIN(1) } },4652 { /*src1 */ { FP64_NORM_SAFE_INT_MAX(1), FP64_NORM_SAFE_INT_MIN(1), FP64_0(0), FP64_NORM_SAFE_INT_MIN(0) } },4653 { /* => */ { FP64_0(0), FP64_NORM_SAFE_INT_MIN(1), FP64_NORM_SAFE_INT_MIN(1), FP64_V(0, 0, 2)} },4651 { { /*src2 */ { FP64_NORM_SAFE_INT_MAX(1), FP64_0(0), FP64_NORM_SAFE_INT_MIN(0), FP64_NORM_SAFE_INT_MIN(1) } }, 4652 { /*src1 */ { FP64_NORM_SAFE_INT_MAX(1), FP64_NORM_SAFE_INT_MIN(1), FP64_0(0), FP64_NORM_SAFE_INT_MIN(0) } }, 4653 { /* => */ { FP64_0(0), FP64_NORM_SAFE_INT_MIN(1), FP64_NORM_SAFE_INT_MIN(1), FP64_V(0, 0, FP32_EXP_SAFE_INT_MIN + 1) } }, 4654 4654 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP | X86_MXCSR_XCPT_MASK, 4655 4655 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP | X86_MXCSR_XCPT_MASK, 4656 4656 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP | X86_MXCSR_XCPT_MASK, 4657 4657 /*xcpt? */ false, false }, 4658 { { /*src2 */ { FP64_V(0, 0xc122186c3cfd0, 0x42d)/*123456789876543.25*/, FP64_0(0), FP64_0(1), FP64_NORM_SAFE_INT_MIN(0) } },4659 { /*src1 */ { FP64_V(0, 0xbcd80e0108cc0, 0x42e)/*244555555308646.00*/, FP64_0(0), FP64_0(1), FP64_NORM_SAFE_INT_MIN(1) } },4660 { /* => */ { FP64_V(0, 0xb88e0395d49b0, 0x42d)/*121098765432102.75*/, FP64_0(1), FP64_0(1), FP64_V(1, 0, 2) } },4658 { { /*src2 */ { FP64_V(0, 0xc122186c3cfd0, 0x42d)/*123456789876543.25*/, FP64_0(0), FP64_0(1), FP64_NORM_SAFE_INT_MIN(0) } }, 4659 { /*src1 */ { FP64_V(0, 0xbcd80e0108cc0, 0x42e)/*244555555308646.00*/, FP64_0(0), FP64_0(1), FP64_NORM_SAFE_INT_MIN(1) } }, 4660 { /* => */ { FP64_V(0, 0xb88e0395d49b0, 0x42d)/*121098765432102.75*/, FP64_0(1), FP64_0(1), FP64_V(1, 0, FP32_EXP_SAFE_INT_MIN + 1) } }, 4661 4661 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN | X86_MXCSR_XCPT_MASK, 4662 4662 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN | X86_MXCSR_XCPT_MASK, … … 5263 5263 /*256:out */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_FZ | X86_MXCSR_OE | X86_MXCSR_PE, 5264 5264 /*xcpt? */ false, false }, 5265 { { /*src2 */ { FP64_NORM_MAX(0), FP64_NORM_MIN(1), FP64_V(1, 0, 2), FP64_NORM_MIN(1) } },5266 { /*src1 */ { FP64_NORM_MAX(1), FP64_NORM_MAX(0), FP64_NORM_MIN(1), FP64_NORM_MIN(1) } },5267 { /* => */ { FP64_INF(1), FP64_NORM_MAX(0), FP64_NORM_MIN(0), FP64_0(0) } },5265 { { /*src2 */ { FP64_NORM_MAX(0), FP64_NORM_MIN(1), FP64_V(1, 0, FP32_EXP_NORM_MIN + 1), FP64_NORM_MIN(1) } }, 5266 { /*src1 */ { FP64_NORM_MAX(1), FP64_NORM_MAX(0), FP64_NORM_MIN(1), FP64_NORM_MIN(1) } }, 5267 { /* => */ { FP64_INF(1), FP64_NORM_MAX(0), FP64_NORM_MIN(0), FP64_0(0) } }, 5268 5268 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_OM | X86_MXCSR_PM, 5269 5269 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_OE | X86_MXCSR_PE, … … 6135 6135 { { /*src2 */ { FP64_INF(1), FP64_INF(1), FP64_INF(0), FP64_0(0) } }, 6136 6136 { /*src1 */ { FP64_INF(0), FP64_INF(0), FP64_INF(1), FP64_0(0) } }, 6137 { /* => */ { FP64_QNAN(1), 6137 { /* => */ { FP64_QNAN(1), FP64_QNAN(1), FP64_INF(1), FP64_INF(0) } }, 6138 6138 /*mxcsr:in */ X86_MXCSR_RC_ZERO, 6139 6139 /*128:out */ X86_MXCSR_RC_ZERO | X86_MXCSR_IE, … … 6147 6147 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_UP, 6148 6148 /*xcpt? */ false, false }, 6149 /** @todo Overflow/Precision; Denormals; Normals; Invalids; Underflow, 6149 /* 6150 * Overflow, Precision. 6151 */ 6152 /*11*/{ { /*src2 */ { FP64_0(0), FP64_0(0), FP64_NORM_MIN(0), FP64_NORM_MAX(0) } }, 6153 { /*src1 */ { FP64_0(0), FP64_0(0), FP64_NORM_MIN(1), FP64_NORM_MAX(1) } }, 6154 { /* => */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } }, 6155 /*mxcsr:in */ 0, 6156 /*128:out */ 0, 6157 /*256:out */ X86_MXCSR_PE, 6158 /*xcpt? */ false, true }, 6159 { { /*src2 */ { FP64_NORM_MIN(1), FP64_NORM_MAX(1), FP64_NORM_MAX(1), FP64_NORM_MAX(1) } }, 6160 { /*src1 */ { FP64_NORM_MAX(0), FP64_NORM_MAX(1), FP64_NORM_MIN(0), FP64_NORM_MAX(0) } }, 6161 { /* => */ { FP64_INF(0), FP64_NORM_MAX(0), FP64_NORM_MAX(1), FP64_0(0) } }, 6162 /*mxcsr:in */ X86_MXCSR_OM | X86_MXCSR_PM, 6163 /*128:out */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_OE | X86_MXCSR_PE, 6164 /*256:out */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_OE | X86_MXCSR_PE, 6165 /*xcpt? */ false, false }, 6166 { { /*src2 */ { FP64_NORM_MAX(1), FP64_NORM_MAX(0), FP64_2(0), FP64_1(0) } }, 6167 { /*src1 */ { FP64_NORM_MAX(0), FP64_NORM_MAX(0), FP64_NORM_MAX(1), FP64_NORM_MAX(0) } }, 6168 { /* => */ { FP64_0(0), FP64_NORM_MAX(1), FP64_NORM_MAX(1), FP64_1(0) } }, 6169 /*mxcsr:in */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_RC_ZERO, 6170 /*128:out */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_RC_ZERO | X86_MXCSR_OE | X86_MXCSR_PE, 6171 /*256:out */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_RC_ZERO | X86_MXCSR_OE | X86_MXCSR_PE, 6172 /*xcpt? */ false, false }, 6173 { { /*src2 */ { FP64_NORM_MAX(0), FP64_NORM_MAX(1), FP64_0(0), FP64_NORM_MIN(1) } }, 6174 { /*src1 */ { FP64_0(0), FP64_NORM_MAX(0), FP64_NORM_MIN(1), FP64_NORM_MIN(0) } }, 6175 { /* => */ { FP64_NORM_MAX(1), FP64_INF(0), FP64_V(1, 0, FP64_EXP_NORM_MIN + 1), FP64_NORM_MIN(0) } }, 6176 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_RC_UP, 6177 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_RC_UP | X86_MXCSR_OE | X86_MXCSR_PE, 6178 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_RC_UP | X86_MXCSR_OE | X86_MXCSR_PE, 6179 /*xcpt? */ false, false }, 6180 #if 0 6181 { { /*src2 */ { FP64_NORM_MAX(0), FP64_NORM_MAX(0), FP64_0(0), FP64_NORM_MAX(0) } }, 6182 { /*src1 */ { FP64_NORM_MIN(1), FP64_NORM_MAX(0), FP64_NORM_MIN(0), FP64_NORM_MAX(1) } }, 6183 { /* => */ { FP64_NORM_MAX(0), FP64_INF(0), FP64_V(1, FP64_FRAC_NORM_MAX - 1, FP64_EXP_NORM_MAX), FP64_NORM_MAX(0) } }, 6184 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_RC_UP, 6185 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_RC_UP | X86_MXCSR_OE | X86_MXCSR_PE, 6186 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_RC_UP | X86_MXCSR_OE | X86_MXCSR_PE, 6187 /*xcpt? */ false, false }, 6188 { { /*src2 */ { FP64_NORM_MAX(0), FP64_NORM_MAX(0), FP64_NORM_MAX(0), FP64_0(0) } }, 6189 { /*src1 */ { FP64_NORM_MIN(1), FP64_NORM_MIN(1), FP64_NORM_MIN(0), FP64_NORM_MIN(0) } }, 6190 { /* => */ { FP64_V(1, 0, 2), FP64_NORM_MAX(0), FP64_V(0, 0, 2), FP64_NORM_MAX(0) } }, 6191 /*mxcsr:in */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_RC_ZERO, 6192 /*128:out */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_RC_ZERO | X86_MXCSR_OE | X86_MXCSR_PE, 6193 /*256:out */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_RC_ZERO | X86_MXCSR_OE | X86_MXCSR_PE, 6194 /*xcpt? */ false, false }, 6195 { { /*src2 */ { FP64_0(0), FP64_NORM_MAX(0), FP64_NORM_MIN(1), FP64_NORM_MIN(0) } }, 6196 { /*src1 */ { FP64_NORM_MAX(1), FP64_NORM_MAX(1), FP64_NORM_MIN(1), FP64_NORM_MIN(1) } }, 6197 { /* => */ { FP64_V(1, FP64_FRAC_NORM_MAX, FP64_EXP_NORM_MAX), FP64_NORM_MAX(0), FP64_V(1, 0, 2), FP64_0(0) } }, 6198 /*mxcsr:in */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_RC_ZERO, 6199 /*128:out */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_RC_ZERO | X86_MXCSR_OE | X86_MXCSR_PE, 6200 /*256:out */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_RC_ZERO | X86_MXCSR_OE | X86_MXCSR_PE, 6201 /*xcpt? */ false, false }, 6202 { { /*src2 */ { FP64_0(0), FP64_0(0), FP64_NORM_MAX(0), FP64_NORM_MAX(1) } }, 6203 { /*src1 */ { FP64_0(0), FP64_0(0), FP64_NORM_MAX(0), FP64_NORM_MAX(0) } }, 6204 { /* => */ { FP64_0(0), FP64_0(0), FP64_NORM_MAX(0), FP64_NORM_MAX(1) } }, 6205 /*mxcsr:in */ X86_MXCSR_RC_ZERO, 6206 /*128:out */ X86_MXCSR_RC_ZERO, 6207 /*256:out */ X86_MXCSR_RC_ZERO | X86_MXCSR_OE, 6208 /*xcpt? */ false, true }, 6209 { { /*src2 */ { FP64_NORM_SAFE_INT_MIN(0), FP64_NORM_SAFE_INT_MAX(0), FP64_NORM_SAFE_INT_MAX(0), FP64_NORM_SAFE_INT_MAX(1) } }, 6210 { /*src1 */ { FP64_NORM_SAFE_INT_MAX(0), FP64_NORM_SAFE_INT_MIN(0), FP64_NORM_SAFE_INT_MAX(0), FP64_NORM_SAFE_INT_MIN(0) } }, 6211 { /* => */ { FP64_NORM_SAFE_INT_MAX(0), FP64_NORM_SAFE_INT_MAX(0), FP64_NORM_SAFE_INT_MAX(0), FP64_0(0) } }, 6212 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO, 6213 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO | X86_MXCSR_PE, 6214 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO | X86_MXCSR_PE, 6215 /*xcpt? */ false, false }, 6216 #endif 6217 /** @todo Denormals; Normals; Invalids; Underflow, 6150 6218 * Precision; Rounding, FZ etc. */ 6151 6219 };
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