Index: trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-4.c32
===================================================================
--- trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-4.c32	(revision 105908)
+++ trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-4.c32	(revision 105912)
@@ -1668,14 +1668,14 @@
               /*256:out  */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_RC_ZERO | X86_MXCSR_OE | X86_MXCSR_PE,
               /*xcpt?    */ false, false },
-          { { /*src2     */ { FP32_NORM_MAX(0), FP32_NORM_MIN(1), FP32_0(0), FP32_NORM_MAX(0), FP32_NORM_MAX(0), FP32_NORM_MIN(1), FP32_0(0), FP32_NORM_MAX(0) } },
-            { /*src1     */ { FP32_NORM_MAX(0), FP32_NORM_MIN(1), FP32_0(0), FP32_NORM_MAX(0), FP32_NORM_MAX(0), FP32_NORM_MIN(1), FP32_0(0), FP32_NORM_MAX(0) } },
-            { /* =>      */ { FP32_INF(0),      FP32_V(1, 0, 2),  FP32_0(0), FP32_INF(0),      FP32_INF(0),      FP32_V(1, 0, 2),  FP32_0(0), FP32_INF(0)        } },
+          { { /*src2     */ { FP32_NORM_MAX(0), FP32_NORM_MIN(1),                     FP32_0(0), FP32_NORM_MAX(0), FP32_NORM_MAX(0), FP32_NORM_MIN(1),                    FP32_0(0), FP32_NORM_MAX(0) } },
+            { /*src1     */ { FP32_NORM_MAX(0), FP32_NORM_MIN(1),                     FP32_0(0), FP32_NORM_MAX(0), FP32_NORM_MAX(0), FP32_NORM_MIN(1),                    FP32_0(0), FP32_NORM_MAX(0) } },
+            { /* =>      */ { FP32_INF(0),      FP32_V(1, 0, FP32_EXP_NORM_MIN + 1),  FP32_0(0), FP32_INF(0),      FP32_INF(0),      FP32_V(1, 0, FP32_EXP_NORM_MIN + 1), FP32_0(0), FP32_INF(0)      } },
               /*mxcsr:in */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
               /*128:out  */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP | X86_MXCSR_OE | X86_MXCSR_PE,
               /*256:out  */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP | X86_MXCSR_OE | X86_MXCSR_PE,
               /*xcpt?    */ false, false },
-          { { /*src2     */ { FP32_NORM_MIN(1), FP32_NORM_MAX(0), FP32_NORM_MAX(0), FP32_0(0), FP32_0(1), FP32_NORM_MAX(0), FP32_NORM_MAX(0), FP32_NORM_MIN(1) } },
-            { /*src1     */ { FP32_NORM_MIN(1), FP32_NORM_MAX(0), FP32_NORM_MAX(1), FP32_0(0), FP32_0(1), FP32_NORM_MAX(1), FP32_NORM_MAX(0), FP32_NORM_MIN(1) } },
-            { /* =>      */ { FP32_V(1, 0, 2),  FP32_NORM_MAX(0), FP32_0(1),        FP32_0(0), FP32_0(1), FP32_0(1),        FP32_NORM_MAX(0), FP32_V(1, 0, 2)  } },
+          { { /*src2     */ { FP32_NORM_MIN(1),                     FP32_NORM_MAX(0), FP32_NORM_MAX(0), FP32_0(0), FP32_0(1), FP32_NORM_MAX(0), FP32_NORM_MAX(0), FP32_NORM_MIN(1)                    } },
+            { /*src1     */ { FP32_NORM_MIN(1),                     FP32_NORM_MAX(0), FP32_NORM_MAX(1), FP32_0(0), FP32_0(1), FP32_NORM_MAX(1), FP32_NORM_MAX(0), FP32_NORM_MIN(1)                    } },
+            { /* =>      */ { FP32_V(1, 0, FP32_EXP_NORM_MIN + 1),  FP32_NORM_MAX(0), FP32_0(1),        FP32_0(0), FP32_0(1), FP32_0(1),        FP32_NORM_MAX(0), FP32_V(1, 0, FP32_EXP_NORM_MIN + 1) } },
               /*mxcsr:in */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
               /*128:out  */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN | X86_MXCSR_OE | X86_MXCSR_PE,
@@ -1748,14 +1748,14 @@
               /*256:out  */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
               /*xcpt?    */ false, false },
-          { { /*src2     */ { FP32_NORM_SAFE_INT_MIN(0), FP32_0(0),                 FP32_NORM_SAFE_INT_MIN(0), FP32_NORM_SAFE_INT_MIN(0), FP32_NORM_SAFE_INT_MIN(0), FP32_0(0),                 FP32_NORM_SAFE_INT_MIN(0), FP32_NORM_SAFE_INT_MIN(0) } },
-            { /*src1     */ { FP32_NORM_SAFE_INT_MIN(1), FP32_NORM_SAFE_INT_MIN(1), FP32_0(0),                 FP32_NORM_SAFE_INT_MIN(0), FP32_NORM_SAFE_INT_MIN(1), FP32_NORM_SAFE_INT_MIN(1), FP32_0(0),                 FP32_NORM_SAFE_INT_MIN(0) } },
-            { /* =>      */ { FP32_0(1),                 FP32_NORM_SAFE_INT_MIN(1), FP32_NORM_SAFE_INT_MIN(0), FP32_V(0, 0, 2),           FP32_0(1),                 FP32_NORM_SAFE_INT_MIN(1), FP32_NORM_SAFE_INT_MIN(0), FP32_V(0, 0, 2)           } },
+          { { /*src2     */ { FP32_NORM_SAFE_INT_MIN(0), FP32_0(0),                 FP32_NORM_SAFE_INT_MIN(0), FP32_NORM_SAFE_INT_MIN(0),               FP32_NORM_SAFE_INT_MIN(0), FP32_0(0),                 FP32_NORM_SAFE_INT_MIN(0), FP32_NORM_SAFE_INT_MIN(0)               } },
+            { /*src1     */ { FP32_NORM_SAFE_INT_MIN(1), FP32_NORM_SAFE_INT_MIN(1), FP32_0(0),                 FP32_NORM_SAFE_INT_MIN(0),               FP32_NORM_SAFE_INT_MIN(1), FP32_NORM_SAFE_INT_MIN(1), FP32_0(0),                 FP32_NORM_SAFE_INT_MIN(0)               } },
+            { /* =>      */ { FP32_0(1),                 FP32_NORM_SAFE_INT_MIN(1), FP32_NORM_SAFE_INT_MIN(0), FP32_V(0, 0, FP32_EXP_SAFE_INT_MIN + 1), FP32_0(1),                 FP32_NORM_SAFE_INT_MIN(1), FP32_NORM_SAFE_INT_MIN(0), FP32_V(0, 0, FP32_EXP_SAFE_INT_MIN + 1) } },
               /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
               /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
               /*256:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
               /*xcpt?    */ false, false },
-          { { /*src2     */ { FP32_V(0, 0x600000, 0x7e)/*      0.875*/, FP32_V(0, 0x3ce348, 0x90)/*193421.125*/, FP32_V(0, 0x6423f2, 0x92)/*934463.125*/, FP32_NORM_SAFE_INT_MIN(1), FP32_NORM_SAFE_INT_MIN(0), FP32_V(0, 0x16b43a, 0x93)/*1234567.25*/, FP32_V(0, 0x792318, 0x91)/*510232.75*/, FP32_V(0, 0x600000, 0x7e)/*      0.875*/ } },
-            { /*src1     */ { FP32_V(0, 0x769b50, 0x92)/*1010101.000*/, FP32_V(0, 0x430ebc, 0x91)/*399477.875*/, FP32_V(1, 0x0a19f0, 0x8f)/*-70707.875*/, FP32_NORM_SAFE_INT_MIN(1), FP32_NORM_SAFE_INT_MIN(0), FP32_V(0, 0x00c6d3, 0x94)/*2109876.75*/, FP32_V(1, 0x316740, 0x8e)/*-45415.25*/, FP32_V(0, 0x769b50, 0x92)/*1010101.000*/ } },
-            { /* =>      */ { FP32_V(0, 0x769b5e, 0x92)/*1010101.875*/, FP32_V(0, 0x10c030, 0x92)/*592899.000*/, FP32_V(0, 0x52e0b4, 0x92)/*863755.250*/, FP32_V(1, 0, 2),           FP32_V(0, 0, 2),           FP32_V(0, 0x4c20f0, 0x94)/*3344444.00*/, FP32_V(0, 0x62f630, 0x91)/*464817.50*/, FP32_V(0, 0x769b5e, 0x92)/*1010101.875*/ } },
+          { { /*src2     */ { FP32_V(0, 0x600000, 0x7e)/*      0.875*/, FP32_V(0, 0x3ce348, 0x90)/*193421.125*/, FP32_V(0, 0x6423f2, 0x92)/*934463.125*/, FP32_NORM_SAFE_INT_MIN(1),               FP32_NORM_SAFE_INT_MIN(0),                FP32_V(0, 0x16b43a, 0x93)/*1234567.25*/, FP32_V(0, 0x792318, 0x91)/*510232.75*/, FP32_V(0, 0x600000, 0x7e)/*      0.875*/ } },
+            { /*src1     */ { FP32_V(0, 0x769b50, 0x92)/*1010101.000*/, FP32_V(0, 0x430ebc, 0x91)/*399477.875*/, FP32_V(1, 0x0a19f0, 0x8f)/*-70707.875*/, FP32_NORM_SAFE_INT_MIN(1),               FP32_NORM_SAFE_INT_MIN(0),                FP32_V(0, 0x00c6d3, 0x94)/*2109876.75*/, FP32_V(1, 0x316740, 0x8e)/*-45415.25*/, FP32_V(0, 0x769b50, 0x92)/*1010101.000*/ } },
+            { /* =>      */ { FP32_V(0, 0x769b5e, 0x92)/*1010101.875*/, FP32_V(0, 0x10c030, 0x92)/*592899.000*/, FP32_V(0, 0x52e0b4, 0x92)/*863755.250*/, FP32_V(1, 0, FP32_EXP_SAFE_INT_MIN + 1), FP32_V(0, 0, FP32_EXP_SAFE_INT_MIN + 1),  FP32_V(0, 0x4c20f0, 0x94)/*3344444.00*/, FP32_V(0, 0x62f630, 0x91)/*464817.50*/, FP32_V(0, 0x769b5e, 0x92)/*1010101.875*/ } },
               /*mxcsr:in */ X86_MXCSR_RC_DOWN,
               /*128:out  */ X86_MXCSR_RC_DOWN,
@@ -2047,14 +2047,14 @@
               /*256:out  */ X86_MXCSR_OE,
               /*xcpt?    */ true, true },
-          { { /*src2     */ { FP64_NORM_MAX(0), FP64_NORM_MIN(1), FP64_0(0), FP64_NORM_MAX(0) } },
-            { /*src1     */ { FP64_NORM_MAX(0), FP64_NORM_MIN(1), FP64_0(0), FP64_NORM_MAX(0) } },
-            { /* =>      */ { FP64_INF(0),      FP64_V(1, 0, 2),  FP64_0(0), FP64_INF(0)      } },
+          { { /*src2     */ { FP64_NORM_MAX(0), FP64_NORM_MIN(1),                     FP64_0(0), FP64_NORM_MAX(0) } },
+            { /*src1     */ { FP64_NORM_MAX(0), FP64_NORM_MIN(1),                     FP64_0(0), FP64_NORM_MAX(0) } },
+            { /* =>      */ { FP64_INF(0),      FP64_V(1, 0, FP32_EXP_NORM_MIN + 1),  FP64_0(0), FP64_INF(0)      } },
               /*mxcsr:in */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_DAZ | X86_MXCSR_FZ,
               /*128:out  */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_OE | X86_MXCSR_PE,
               /*256:out  */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_OE | X86_MXCSR_PE,
               /*xcpt?    */ false, false },
-          { { /*src2     */ { FP64_NORM_MIN(1), FP64_NORM_MAX(0), FP64_NORM_MAX(0), FP64_0(0) } },
-            { /*src1     */ { FP64_NORM_MIN(1), FP64_NORM_MAX(0), FP64_NORM_MAX(1), FP64_0(0) } },
-            { /* =>      */ { FP64_V(1, 0, 2),  FP64_INF(0),      FP64_0(0),        FP64_0(0) } },
+          { { /*src2     */ { FP64_NORM_MIN(1),                     FP64_NORM_MAX(0), FP64_NORM_MAX(0), FP64_0(0) } },
+            { /*src1     */ { FP64_NORM_MIN(1),                     FP64_NORM_MAX(0), FP64_NORM_MAX(1), FP64_0(0) } },
+            { /* =>      */ { FP64_V(1, 0, FP32_EXP_NORM_MIN + 1),  FP64_INF(0),      FP64_0(0),        FP64_0(0) } },
               /*mxcsr:in */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_FZ,
               /*128:out  */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_FZ | X86_MXCSR_OE | X86_MXCSR_PE,
@@ -2121,14 +2121,14 @@
               /*256:out  */ X86_MXCSR_FZ,
               /*xcpt?    */ false, false },
-          { { /*src2     */ { FP64_NORM_SAFE_INT_MIN(0), FP64_0(0),                 FP64_NORM_SAFE_INT_MIN(0), FP64_NORM_SAFE_INT_MIN(0) } },
-            { /*src1     */ { FP64_NORM_SAFE_INT_MIN(1), FP64_NORM_SAFE_INT_MIN(1), FP64_0(0),                 FP64_NORM_SAFE_INT_MIN(0) } },
-            { /* =>      */ { FP64_0(1),                 FP64_NORM_SAFE_INT_MIN(1), FP64_NORM_SAFE_INT_MIN(0), FP64_V(0, 0, 2)           } },
+          { { /*src2     */ { FP64_NORM_SAFE_INT_MIN(0), FP64_0(0),                 FP64_NORM_SAFE_INT_MIN(0), FP64_NORM_SAFE_INT_MIN(0)               } },
+            { /*src1     */ { FP64_NORM_SAFE_INT_MIN(1), FP64_NORM_SAFE_INT_MIN(1), FP64_0(0),                 FP64_NORM_SAFE_INT_MIN(0)               } },
+            { /* =>      */ { FP64_0(1),                 FP64_NORM_SAFE_INT_MIN(1), FP64_NORM_SAFE_INT_MIN(0), FP64_V(0, 0, FP32_EXP_SAFE_INT_MIN + 1) } },
               /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
               /*128:out  */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
               /*256:out  */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
               /*xcpt?    */ false, false },
-          { { /*src2     */ { FP64_V(0, 0xc122186c3cfd0, 0x42d)/*123456789876543.25*/, FP64_0(0), FP64_0(0), FP64_NORM_SAFE_INT_MIN(1) } },
-            { /*src1     */ { FP64_V(0, 0xb88e0395d49b0, 0x42d)/*121098765432102.75*/, FP64_0(0), FP64_0(0), FP64_NORM_SAFE_INT_MIN(1) } },
-            { /* =>      */ { FP64_V(0, 0xbcd80e0108cc0, 0x42e)/*244555555308646.00*/, FP64_0(0), FP64_0(0), FP64_V(1, 0, 2)           } },
+          { { /*src2     */ { FP64_V(0, 0xc122186c3cfd0, 0x42d)/*123456789876543.25*/, FP64_0(0), FP64_0(0), FP64_NORM_SAFE_INT_MIN(1)               } },
+            { /*src1     */ { FP64_V(0, 0xb88e0395d49b0, 0x42d)/*121098765432102.75*/, FP64_0(0), FP64_0(0), FP64_NORM_SAFE_INT_MIN(1)               } },
+            { /* =>      */ { FP64_V(0, 0xbcd80e0108cc0, 0x42e)/*244555555308646.00*/, FP64_0(0), FP64_0(0), FP64_V(1, 0, FP32_EXP_SAFE_INT_MIN + 1) } },
               /*mxcsr:in */ X86_MXCSR_RC_UP,
               /*128:out  */ X86_MXCSR_RC_UP,
@@ -3399,14 +3399,14 @@
               /*256:out  */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_RC_ZERO | X86_MXCSR_OE | X86_MXCSR_PE,
               /*xcpt?    */ false, false },
-          { { /*src2     */ { FP32_NORM_MAX(0), FP32_NORM_MAX(1), FP32_0(0),        FP32_NORM_MIN(1), FP32_NORM_MAX(0), FP32_NORM_MAX(0),                                     FP32_0(0),        FP32_NORM_MAX(0) } },
-            { /*src1     */ { FP32_NORM_MAX(0), FP32_NORM_MAX(0), FP32_NORM_MIN(1), FP32_NORM_MIN(1), FP32_NORM_MIN(1), FP32_NORM_MAX(0),                                     FP32_NORM_MIN(0), FP32_NORM_MAX(1) } },
-            { /* =>      */ { FP32_INF(0),      FP32_V(1, 0, 2),  FP32_0(0),        FP32_NORM_MIN(1), FP32_NORM_MAX(0), FP32_V(1, FP32_FRAC_NORM_MAX - 1, FP32_EXP_NORM_MAX), FP32_INF(0),      FP32_NORM_MAX(0) } },
+          { { /*src2     */ { FP32_NORM_MAX(0), FP32_NORM_MAX(1),                     FP32_0(0),        FP32_NORM_MIN(1), FP32_NORM_MAX(0), FP32_NORM_MAX(0),                                     FP32_0(0),        FP32_NORM_MAX(0) } },
+            { /*src1     */ { FP32_NORM_MAX(0), FP32_NORM_MAX(0),                     FP32_NORM_MIN(1), FP32_NORM_MIN(1), FP32_NORM_MIN(1), FP32_NORM_MAX(0),                                     FP32_NORM_MIN(0), FP32_NORM_MAX(1) } },
+            { /* =>      */ { FP32_INF(0),      FP32_V(1, 0, FP32_EXP_NORM_MIN + 1),  FP32_0(0),        FP32_NORM_MIN(1), FP32_NORM_MAX(0), FP32_V(1, FP32_FRAC_NORM_MAX - 1, FP32_EXP_NORM_MAX), FP32_INF(0),      FP32_NORM_MAX(0) } },
               /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_RC_UP,
               /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_RC_UP | X86_MXCSR_OE | X86_MXCSR_PE,
               /*256:out  */ X86_MXCSR_DAZ | X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_RC_UP | X86_MXCSR_OE | X86_MXCSR_PE,
               /*xcpt?    */ false, false },
-          { { /*src2     */ { FP32_NORM_MAX(0), FP32_NORM_MAX(0), FP32_NORM_MAX(0), FP32_0(0),        FP32_0(0),        FP32_NORM_MAX(0), FP32_NORM_MIN(1), FP32_NORM_MIN(0) } },
-            { /*src1     */ { FP32_NORM_MIN(1), FP32_NORM_MIN(1), FP32_NORM_MIN(0), FP32_NORM_MIN(0), FP32_0(0),        FP32_NORM_MAX(1), FP32_NORM_MIN(1), FP32_NORM_MIN(1) } },
-            { /* =>      */ { FP32_V(1, 0, 2),  FP32_V(0, 0, 2),  FP32_NORM_MAX(0), FP32_NORM_MAX(0), FP32_NORM_MAX(1), FP32_V(1, 0, 2),  FP32_NORM_MAX(0), FP32_0(0)        } },
+          { { /*src2     */ { FP32_NORM_MAX(0),                     FP32_NORM_MAX(0),                     FP32_NORM_MAX(0), FP32_0(0),        FP32_0(0),        FP32_NORM_MAX(0),                     FP32_NORM_MIN(1), FP32_NORM_MIN(0) } },
+            { /*src1     */ { FP32_NORM_MIN(1),                     FP32_NORM_MIN(1),                     FP32_NORM_MIN(0), FP32_NORM_MIN(0), FP32_0(0),        FP32_NORM_MAX(1),                     FP32_NORM_MIN(1), FP32_NORM_MIN(1) } },
+            { /* =>      */ { FP32_V(1, 0, FP32_EXP_NORM_MIN + 1),  FP32_V(0, 0, FP32_EXP_NORM_MIN + 1),  FP32_NORM_MAX(0), FP32_NORM_MAX(0), FP32_NORM_MAX(1), FP32_V(1, 0, FP32_EXP_NORM_MIN + 1),  FP32_NORM_MAX(0), FP32_0(0)        } },
               /*mxcsr:in */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_RC_ZERO,
               /*128:out  */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_RC_ZERO | X86_MXCSR_OE | X86_MXCSR_PE,
@@ -3481,5 +3481,5 @@
           { { /*src2     */ { FP32_V(0, 0x6423f2, 0x92)/* 934463.125*/, FP32_V(1, 0x0a19f0, 0x8f)/*-70707.875*/, FP32_NORM_SAFE_INT_MIN(1),               FP32_NORM_SAFE_INT_MIN(1),               FP32_NORM_SAFE_INT_MIN(0),               FP32_NORM_SAFE_INT_MIN(0),               FP32_V(0, 0x600000, 0x7e)/*     0.875*/, FP32_V(0, 0x769b50, 0x92)/*1010101.000*/ } },
             { /*src1     */ { FP32_V(0, 0x769b50, 0x92)/*1010101.000*/, FP32_V(0, 0x600000, 0x7e)/*     0.875*/, FP32_V(0, 0x430ebc, 0x91)/*399477.875*/, FP32_V(0, 0x3ce348, 0x90)/*193421.125*/, FP32_V(0, 0x16b43a, 0x93)/*1234567.25*/, FP32_V(0, 0x00c6d3, 0x94)/*2109876.75*/, FP32_V(0, 0x792318, 0x91)/*510232.750*/, FP32_V(1, 0x316740, 0x8e)/* -45415.250*/ } },
-            { /* =>      */ { FP32_V(0, 0x769b5e, 0x92)/*1010101.875*/, FP32_V(0, 0x10c030, 0x92)/*592899.000*/, FP32_V(0, 0x52e0b4, 0x92)/*863755.250*/, FP32_V(1, 0, 2),                         FP32_V(0, 0x4c20f0, 0x94)/*3344444.00*/, FP32_V(0, 0x62f630, 0x91)/*464817.50*/,  FP32_V(0, 0, 2),                         FP32_V(0, 0x769b5e, 0x92)/*1010101.875*/ } },
+            { /* =>      */ { FP32_V(0, 0x769b5e, 0x92)/*1010101.875*/, FP32_V(0, 0x10c030, 0x92)/*592899.000*/, FP32_V(0, 0x52e0b4, 0x92)/*863755.250*/, FP32_V(1, 0, FP32_EXP_SAFE_INT_MIN + 1), FP32_V(0, 0x4c20f0, 0x94)/*3344444.00*/, FP32_V(0, 0x62f630, 0x91)/*464817.50*/,  FP32_V(0, 0, FP32_EXP_SAFE_INT_MIN + 1), FP32_V(0, 0x769b5e, 0x92)/*1010101.875*/ } },
               /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
               /*128:out  */ X86_MXCSR_XCPT_MASK,
@@ -3785,7 +3785,7 @@
               /*256:out  */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_RC_ZERO | X86_MXCSR_OE | X86_MXCSR_PE,
               /*xcpt?    */ false, false },
-          { { /*src2     */ { FP64_NORM_MAX(0), FP64_NORM_MAX(1), FP64_0(0),        FP64_NORM_MIN(1) } },
-            { /*src1     */ { FP64_NORM_MAX(0), FP64_NORM_MAX(0), FP64_NORM_MIN(1), FP64_NORM_MIN(1) } },
-            { /* =>      */ { FP64_INF(0),      FP64_0(0),        FP64_V(1, 0, 2),  FP64_NORM_MIN(1) } },
+          { { /*src2     */ { FP64_NORM_MAX(0), FP64_NORM_MAX(1), FP64_0(0),                            FP64_NORM_MIN(1) } },
+            { /*src1     */ { FP64_NORM_MAX(0), FP64_NORM_MAX(0), FP64_NORM_MIN(1),                     FP64_NORM_MIN(1) } },
+            { /* =>      */ { FP64_INF(0),      FP64_0(0),        FP64_V(1, 0, FP32_EXP_NORM_MIN + 1),  FP64_NORM_MIN(1) } },
               /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_RC_UP,
               /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_RC_UP | X86_MXCSR_OE | X86_MXCSR_PE,
@@ -3799,14 +3799,14 @@
               /*256:out  */ X86_MXCSR_DAZ | X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_RC_UP | X86_MXCSR_OE | X86_MXCSR_PE,
               /*xcpt?    */ false, false },
-          { { /*src2     */ { FP64_NORM_MAX(0), FP64_NORM_MAX(0), FP64_NORM_MAX(0), FP64_0(0)        } },
-            { /*src1     */ { FP64_NORM_MIN(1), FP64_NORM_MIN(1), FP64_NORM_MIN(0), FP64_NORM_MIN(0) } },
-            { /* =>      */ { FP64_V(1, 0, 2),  FP64_NORM_MAX(0), FP64_V(0, 0, 2),  FP64_NORM_MAX(0) } },
+          { { /*src2     */ { FP64_NORM_MAX(0),                     FP64_NORM_MAX(0), FP64_NORM_MAX(0),                     FP64_0(0)        } },
+            { /*src1     */ { FP64_NORM_MIN(1),                     FP64_NORM_MIN(1), FP64_NORM_MIN(0),                     FP64_NORM_MIN(0) } },
+            { /* =>      */ { FP64_V(1, 0, FP32_EXP_NORM_MIN + 1),  FP64_NORM_MAX(0), FP64_V(0, 0, FP32_EXP_NORM_MIN + 1),  FP64_NORM_MAX(0) } },
               /*mxcsr:in */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_RC_ZERO,
               /*128:out  */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_RC_ZERO | X86_MXCSR_OE | X86_MXCSR_PE,
               /*256:out  */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_RC_ZERO | X86_MXCSR_OE | X86_MXCSR_PE,
               /*xcpt?    */ false, false },
-          { { /*src2     */ { FP64_0(0),                                        FP64_NORM_MAX(0), FP64_NORM_MIN(1), FP64_NORM_MIN(0) } },
-            { /*src1     */ { FP64_NORM_MAX(1),                                 FP64_NORM_MAX(1), FP64_NORM_MIN(1), FP64_NORM_MIN(1) } },
-            { /* =>      */ { FP64_V(1, FP64_FRAC_NORM_MAX, FP64_EXP_NORM_MAX), FP64_NORM_MAX(0), FP64_V(1, 0, 2),  FP64_0(0)        } },
+          { { /*src2     */ { FP64_0(0),                                        FP64_NORM_MAX(0), FP64_NORM_MIN(1),                     FP64_NORM_MIN(0) } },
+            { /*src1     */ { FP64_NORM_MAX(1),                                 FP64_NORM_MAX(1), FP64_NORM_MIN(1),                     FP64_NORM_MIN(1) } },
+            { /* =>      */ { FP64_V(1, FP64_FRAC_NORM_MAX, FP64_EXP_NORM_MAX), FP64_NORM_MAX(0), FP64_V(1, 0, FP32_EXP_NORM_MIN + 1),  FP64_0(0)        } },
               /*mxcsr:in */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_RC_ZERO,
               /*128:out  */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_RC_ZERO | X86_MXCSR_OE | X86_MXCSR_PE,
@@ -3858,14 +3858,14 @@
               /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
               /*xcpt?    */ false, false },
-          { { /*src2     */ { FP64_NORM_SAFE_INT_MIN(0), FP64_0(0),                 FP64_NORM_SAFE_INT_MIN(1), FP64_NORM_SAFE_INT_MIN(1) } },
-            { /*src1     */ { FP64_NORM_SAFE_INT_MIN(1), FP64_NORM_SAFE_INT_MIN(0), FP64_NORM_SAFE_INT_MIN(0), FP64_NORM_SAFE_INT_MIN(0) } },
-            { /* =>      */ { FP64_0(1),                 FP64_NORM_SAFE_INT_MIN(0), FP64_V(0, 0, 2),           FP64_V(1, 0, 2)           } },
+          { { /*src2     */ { FP64_NORM_SAFE_INT_MIN(0), FP64_0(0),                 FP64_NORM_SAFE_INT_MIN(1),               FP64_NORM_SAFE_INT_MIN(1)               } },
+            { /*src1     */ { FP64_NORM_SAFE_INT_MIN(1), FP64_NORM_SAFE_INT_MIN(0), FP64_NORM_SAFE_INT_MIN(0),               FP64_NORM_SAFE_INT_MIN(0)               } },
+            { /* =>      */ { FP64_0(1),                 FP64_NORM_SAFE_INT_MIN(0), FP64_V(0, 0, FP32_EXP_SAFE_INT_MIN + 1), FP64_V(1, 0, FP32_EXP_SAFE_INT_MIN + 1) } },
               /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
               /*128:out  */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
               /*256:out  */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
               /*xcpt?    */ false, false },
-          { { /*src2     */ { FP64_V(0, 0xc122186c3cfd0, 0x42d)/*123456789876543.25*/, FP64_V(1, 0xc122186c3cfd0, 0x42d)/*-123456789876543.25*/, FP64_NORM_SAFE_INT_MIN(1), FP64_NORM_SAFE_INT_MIN(1) } },
-            { /*src1     */ { FP64_V(0, 0xc122186c3cfd0, 0x42d)/*123456789876543.25*/, FP64_V(0, 0xb88e0395d49b0, 0x42d)/* 121098765432102.75*/, FP64_NORM_V0(0),           FP64_NORM_V0(1)           } },
-            { /* =>      */ { FP64_V(0, 0xbcd80e0108cc0, 0x42e)/*244555555308646.00*/, FP64_0(0),                                                FP64_0(0),                 FP64_V(1, 0, 2)           } },
+          { { /*src2     */ { FP64_V(0, 0xc122186c3cfd0, 0x42d)/*123456789876543.25*/, FP64_V(1, 0xc122186c3cfd0, 0x42d)/*-123456789876543.25*/, FP64_NORM_SAFE_INT_MIN(1), FP64_NORM_SAFE_INT_MIN(1)               } },
+            { /*src1     */ { FP64_V(0, 0xc122186c3cfd0, 0x42d)/*123456789876543.25*/, FP64_V(0, 0xb88e0395d49b0, 0x42d)/* 121098765432102.75*/, FP64_NORM_V0(0),           FP64_NORM_V0(1)                         } },
+            { /* =>      */ { FP64_V(0, 0xbcd80e0108cc0, 0x42e)/*244555555308646.00*/, FP64_0(0),                                                FP64_0(0),                 FP64_V(1, 0, FP32_EXP_SAFE_INT_MIN + 1) } },
               /*mxcsr:in */ X86_MXCSR_RC_UP,
               /*128:out  */ X86_MXCSR_RC_UP,
@@ -4170,14 +4170,14 @@
               /*256:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_OE | X86_MXCSR_PE,
               /*xcpt?    */ false, false },
-          { { /*src2     */ { FP32_NORM_MAX(0), FP32_NORM_MIN(1), FP32_0(0), FP32_NORM_MAX(0), FP32_0(0), FP32_V(1, 0, 2),  FP32_NORM_MIN(1), FP32_NORM_MAX(0) } },
-            { /*src1     */ { FP32_NORM_MAX(1), FP32_NORM_MAX(0), FP32_0(0), FP32_NORM_MAX(1), FP32_0(0), FP32_NORM_MIN(1), FP32_NORM_MIN(1), FP32_NORM_MAX(0) } },
-            { /* =>      */ { FP32_NORM_MAX(1), FP32_NORM_MAX(0), FP32_0(0), FP32_NORM_MAX(1), FP32_0(0), FP32_NORM_MIN(0), FP32_0(0),        FP32_0(0)        } },
+          { { /*src2     */ { FP32_NORM_MAX(0), FP32_NORM_MIN(1), FP32_0(0), FP32_NORM_MAX(0), FP32_0(0), FP32_V(1, 0, FP32_EXP_NORM_MIN + 1),  FP32_NORM_MIN(1), FP32_NORM_MAX(0) } },
+            { /*src1     */ { FP32_NORM_MAX(1), FP32_NORM_MAX(0), FP32_0(0), FP32_NORM_MAX(1), FP32_0(0), FP32_NORM_MIN(1),                     FP32_NORM_MIN(1), FP32_NORM_MAX(0) } },
+            { /* =>      */ { FP32_NORM_MAX(1), FP32_NORM_MAX(0), FP32_0(0), FP32_NORM_MAX(1), FP32_0(0), FP32_NORM_MIN(0),                     FP32_0(0),        FP32_0(0)        } },
               /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_OM | X86_MXCSR_PM,
               /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_OE | X86_MXCSR_PE,
               /*256:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_OE | X86_MXCSR_PE,
               /*xcpt?    */ false, false },
-          { { /*src2     */ { FP32_V(1, 0, 2),  FP32_NORM_MAX(0), FP32_NORM_MAX(0), FP32_0(0), FP32_0(1), FP32_NORM_MAX(0), FP32_NORM_MAX(0), FP32_V(1, 0, 2)  } },
-            { /*src1     */ { FP32_NORM_MIN(1), FP32_NORM_MAX(0), FP32_NORM_MAX(1), FP32_0(0), FP32_0(1), FP32_NORM_MAX(1), FP32_NORM_MAX(1), FP32_NORM_MIN(1) } },
-            { /* =>      */ { FP32_NORM_MIN(0), FP32_0(0),        FP32_NORM_MAX(1), FP32_0(0), FP32_0(0), FP32_NORM_MAX(1), FP32_NORM_MAX(1), FP32_NORM_MIN(0) } },
+          { { /*src2     */ { FP32_V(1, 0, FP32_EXP_NORM_MIN + 1),  FP32_NORM_MAX(0), FP32_NORM_MAX(0), FP32_0(0), FP32_0(1), FP32_NORM_MAX(0), FP32_NORM_MAX(0), FP32_V(1, 0, 2)  } },
+            { /*src1     */ { FP32_NORM_MIN(1),                     FP32_NORM_MAX(0), FP32_NORM_MAX(1), FP32_0(0), FP32_0(1), FP32_NORM_MAX(1), FP32_NORM_MAX(1), FP32_NORM_MIN(1) } },
+            { /* =>      */ { FP32_NORM_MIN(0),                     FP32_0(0),        FP32_NORM_MAX(1), FP32_0(0), FP32_0(0), FP32_NORM_MAX(1), FP32_NORM_MAX(1), FP32_NORM_MIN(0) } },
               /*mxcsr:in */ X86_MXCSR_RC_ZERO | X86_MXCSR_OM | X86_MXCSR_PM,
               /*128:out  */ X86_MXCSR_RC_ZERO | X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_OE | X86_MXCSR_PE,
@@ -4250,14 +4250,14 @@
               /*256:out  */ X86_MXCSR_RC_UP,
               /*xcpt?    */ false, false },
-          { { /*src2     */ { FP32_NORM_SAFE_INT_MIN(0), FP32_0(0),                 FP32_NORM_SAFE_INT_MIN(0), FP32_NORM_SAFE_INT_MIN(0), FP32_NORM_SAFE_INT_MIN(0), FP32_0(1),                 FP32_NORM_SAFE_INT_MIN(1), FP32_NORM_SAFE_INT_MIN(1) } },
-            { /*src1     */ { FP32_NORM_SAFE_INT_MIN(0), FP32_NORM_SAFE_INT_MIN(1), FP32_0(0),                 FP32_V(0, 0, 2),           FP32_NORM_SAFE_INT_MIN(0), FP32_NORM_SAFE_INT_MIN(1), FP32_0(0),                 FP32_NORM_SAFE_INT_MIN(1) } },
-            { /* =>      */ { FP32_0(0),                 FP32_NORM_SAFE_INT_MIN(1), FP32_NORM_SAFE_INT_MIN(1), FP32_NORM_SAFE_INT_MIN(0), FP32_0(0),                 FP32_NORM_SAFE_INT_MIN(1), FP32_NORM_SAFE_INT_MIN(0), FP32_0(0)                 } },
+          { { /*src2     */ { FP32_NORM_SAFE_INT_MIN(0), FP32_0(0),                 FP32_NORM_SAFE_INT_MIN(0), FP32_NORM_SAFE_INT_MIN(0),               FP32_NORM_SAFE_INT_MIN(0), FP32_0(1),                 FP32_NORM_SAFE_INT_MIN(1), FP32_NORM_SAFE_INT_MIN(1) } },
+            { /*src1     */ { FP32_NORM_SAFE_INT_MIN(0), FP32_NORM_SAFE_INT_MIN(1), FP32_0(0),                 FP32_V(0, 0, FP32_EXP_SAFE_INT_MIN + 1), FP32_NORM_SAFE_INT_MIN(0), FP32_NORM_SAFE_INT_MIN(1), FP32_0(0),                 FP32_NORM_SAFE_INT_MIN(1) } },
+            { /* =>      */ { FP32_0(0),                 FP32_NORM_SAFE_INT_MIN(1), FP32_NORM_SAFE_INT_MIN(1), FP32_NORM_SAFE_INT_MIN(0),               FP32_0(0),                 FP32_NORM_SAFE_INT_MIN(1), FP32_NORM_SAFE_INT_MIN(0), FP32_0(0)                 } },
               /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
               /*128:out  */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
               /*256:out  */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
               /*xcpt?    */ false, false },
-          { { /*src2     */ { FP32_V(0, 0x600000, 0x7e)/*      0.875*/, FP32_V(0, 0x3ce348, 0x90)/*193421.125*/, FP32_V(1, 0x0a19f0, 0x8f)/*-70707.875*/, FP32_NORM_SAFE_INT_MIN(1), FP32_NORM_SAFE_INT_MIN(0), FP32_V(0, 0x00c6d3, 0x94)/*2109876.75*/, FP32_V(0, 0x316740, 0x8e)/* 45415.25*/, FP32_V(0, 0x600000, 0x7e)/*       0.875*/ } },
-            { /*src1     */ { FP32_V(0, 0x769b5e, 0x92)/*1010101.875*/, FP32_V(0, 0x10c030, 0x92)/*592899.000*/, FP32_V(0, 0x52e0b4, 0x92)/*863755.250*/, FP32_NORM_SAFE_INT_MIN(0), FP32_NORM_SAFE_INT_MIN(1), FP32_V(0, 0x4c20f0, 0x94)/*3344444.00*/, FP32_V(0, 0x792318, 0x91)/*510232.75*/, FP32_V(1, 0x769b50, 0x92)/*-1010101.000*/ } },
-            { /* =>      */ { FP32_V(0, 0x769b50, 0x92)/*1010101.000*/, FP32_V(0, 0x430ebc, 0x91)/*399477.875*/, FP32_V(0, 0x6423f2, 0x92)/*934463.125*/, FP32_V(0, 0, 2),           FP32_V(1, 0, 2),           FP32_V(0, 0x16b43a, 0x93)/*1234567.25*/, FP32_V(0, 0x62f630, 0x91)/*464817.50*/, FP32_V(1, 0x769b5e, 0x92)/*-1010101.875*/ } },
+          { { /*src2     */ { FP32_V(0, 0x600000, 0x7e)/*      0.875*/, FP32_V(0, 0x3ce348, 0x90)/*193421.125*/, FP32_V(1, 0x0a19f0, 0x8f)/*-70707.875*/, FP32_NORM_SAFE_INT_MIN(1),               FP32_NORM_SAFE_INT_MIN(0),               FP32_V(0, 0x00c6d3, 0x94)/*2109876.75*/, FP32_V(0, 0x316740, 0x8e)/* 45415.25*/, FP32_V(0, 0x600000, 0x7e)/*       0.875*/ } },
+            { /*src1     */ { FP32_V(0, 0x769b5e, 0x92)/*1010101.875*/, FP32_V(0, 0x10c030, 0x92)/*592899.000*/, FP32_V(0, 0x52e0b4, 0x92)/*863755.250*/, FP32_NORM_SAFE_INT_MIN(0),               FP32_NORM_SAFE_INT_MIN(1),               FP32_V(0, 0x4c20f0, 0x94)/*3344444.00*/, FP32_V(0, 0x792318, 0x91)/*510232.75*/, FP32_V(1, 0x769b50, 0x92)/*-1010101.000*/ } },
+            { /* =>      */ { FP32_V(0, 0x769b50, 0x92)/*1010101.000*/, FP32_V(0, 0x430ebc, 0x91)/*399477.875*/, FP32_V(0, 0x6423f2, 0x92)/*934463.125*/, FP32_V(0, 0, FP32_EXP_SAFE_INT_MIN + 1), FP32_V(1, 0, FP32_EXP_SAFE_INT_MIN + 1), FP32_V(0, 0x16b43a, 0x93)/*1234567.25*/, FP32_V(0, 0x62f630, 0x91)/*464817.50*/, FP32_V(1, 0x769b5e, 0x92)/*-1010101.875*/ } },
               /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
               /*128:out  */ X86_MXCSR_XCPT_MASK,
@@ -4576,14 +4576,14 @@
               /*256:out  */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_FZ | X86_MXCSR_OE | X86_MXCSR_PE,
               /*xcpt?    */ false, false },
-          { { /*src2     */ { FP64_NORM_MAX(0), FP64_NORM_MIN(1), FP64_V(1, 0, 2),  FP64_NORM_MIN(1) } },
-            { /*src1     */ { FP64_NORM_MAX(1), FP64_NORM_MAX(0), FP64_NORM_MIN(1), FP64_NORM_MIN(1) } },
-            { /* =>      */ { FP64_INF(1),      FP64_NORM_MAX(0), FP64_NORM_MIN(0), FP64_0(0)        } },
+          { { /*src2     */ { FP64_NORM_MAX(0), FP64_NORM_MIN(1), FP64_V(1, 0, FP32_EXP_NORM_MIN + 1),  FP64_NORM_MIN(1) } },
+            { /*src1     */ { FP64_NORM_MAX(1), FP64_NORM_MAX(0), FP64_NORM_MIN(1),                     FP64_NORM_MIN(1) } },
+            { /* =>      */ { FP64_INF(1),      FP64_NORM_MAX(0), FP64_NORM_MIN(0),                     FP64_0(0)        } },
               /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_OM | X86_MXCSR_PM,
               /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_OE | X86_MXCSR_PE,
               /*256:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_OE | X86_MXCSR_PE,
               /*xcpt?    */ false, false },
-          { { /*src2     */ { FP64_V(1, 0, 2),  FP64_NORM_MAX(0), FP64_NORM_MAX(0), FP64_V(1, 0, 2)  } },
-            { /*src1     */ { FP64_NORM_MIN(1), FP64_NORM_MAX(1), FP64_NORM_MAX(1), FP64_NORM_MIN(1) } },
-            { /* =>      */ { FP64_NORM_MIN(0), FP64_NORM_MAX(1), FP64_NORM_MAX(1), FP64_NORM_MIN(0) } },
+          { { /*src2     */ { FP64_V(1, 0, FP32_EXP_NORM_MIN + 1),  FP64_NORM_MAX(0), FP64_NORM_MAX(0), FP64_V(1, 0, 2)  } },
+            { /*src1     */ { FP64_NORM_MIN(1),                     FP64_NORM_MAX(1), FP64_NORM_MAX(1), FP64_NORM_MIN(1) } },
+            { /* =>      */ { FP64_NORM_MIN(0),                     FP64_NORM_MAX(1), FP64_NORM_MAX(1), FP64_NORM_MIN(0) } },
               /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_OM | X86_MXCSR_PM,
               /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_OE | X86_MXCSR_PE,
@@ -4649,14 +4649,14 @@
               /*256:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_XCPT_MASK,
               /*xcpt?    */ false, false },
-          { { /*src2     */ { FP64_NORM_SAFE_INT_MAX(1), FP64_0(0),                 FP64_NORM_SAFE_INT_MIN(0), FP64_NORM_SAFE_INT_MIN(1) } },
-            { /*src1     */ { FP64_NORM_SAFE_INT_MAX(1), FP64_NORM_SAFE_INT_MIN(1), FP64_0(0),                 FP64_NORM_SAFE_INT_MIN(0) } },
-            { /* =>      */ { FP64_0(0),                 FP64_NORM_SAFE_INT_MIN(1), FP64_NORM_SAFE_INT_MIN(1), FP64_V(0, 0, 2)           } },
+          { { /*src2     */ { FP64_NORM_SAFE_INT_MAX(1), FP64_0(0),                 FP64_NORM_SAFE_INT_MIN(0), FP64_NORM_SAFE_INT_MIN(1)               } },
+            { /*src1     */ { FP64_NORM_SAFE_INT_MAX(1), FP64_NORM_SAFE_INT_MIN(1), FP64_0(0),                 FP64_NORM_SAFE_INT_MIN(0)               } },
+            { /* =>      */ { FP64_0(0),                 FP64_NORM_SAFE_INT_MIN(1), FP64_NORM_SAFE_INT_MIN(1), FP64_V(0, 0, FP32_EXP_SAFE_INT_MIN + 1) } },
               /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP | X86_MXCSR_XCPT_MASK,
               /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP | X86_MXCSR_XCPT_MASK,
               /*256:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP | X86_MXCSR_XCPT_MASK,
               /*xcpt?    */ false, false },
-          { { /*src2     */ { FP64_V(0, 0xc122186c3cfd0, 0x42d)/*123456789876543.25*/, FP64_0(0), FP64_0(1), FP64_NORM_SAFE_INT_MIN(0) } },
-            { /*src1     */ { FP64_V(0, 0xbcd80e0108cc0, 0x42e)/*244555555308646.00*/, FP64_0(0), FP64_0(1), FP64_NORM_SAFE_INT_MIN(1) } },
-            { /* =>      */ { FP64_V(0, 0xb88e0395d49b0, 0x42d)/*121098765432102.75*/, FP64_0(1), FP64_0(1), FP64_V(1, 0, 2) } },
+          { { /*src2     */ { FP64_V(0, 0xc122186c3cfd0, 0x42d)/*123456789876543.25*/, FP64_0(0), FP64_0(1), FP64_NORM_SAFE_INT_MIN(0)               } },
+            { /*src1     */ { FP64_V(0, 0xbcd80e0108cc0, 0x42e)/*244555555308646.00*/, FP64_0(0), FP64_0(1), FP64_NORM_SAFE_INT_MIN(1)               } },
+            { /* =>      */ { FP64_V(0, 0xb88e0395d49b0, 0x42d)/*121098765432102.75*/, FP64_0(1), FP64_0(1), FP64_V(1, 0, FP32_EXP_SAFE_INT_MIN + 1) } },
               /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN | X86_MXCSR_XCPT_MASK,
               /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN | X86_MXCSR_XCPT_MASK,
@@ -5263,7 +5263,7 @@
               /*256:out  */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_FZ | X86_MXCSR_OE | X86_MXCSR_PE,
               /*xcpt?    */ false, false },
-          { { /*src2     */ { FP64_NORM_MAX(0), FP64_NORM_MIN(1), FP64_V(1, 0, 2),  FP64_NORM_MIN(1) } },
-            { /*src1     */ { FP64_NORM_MAX(1), FP64_NORM_MAX(0), FP64_NORM_MIN(1), FP64_NORM_MIN(1) } },
-            { /* =>      */ { FP64_INF(1),      FP64_NORM_MAX(0), FP64_NORM_MIN(0), FP64_0(0)        } },
+          { { /*src2     */ { FP64_NORM_MAX(0), FP64_NORM_MIN(1), FP64_V(1, 0, FP32_EXP_NORM_MIN + 1),  FP64_NORM_MIN(1) } },
+            { /*src1     */ { FP64_NORM_MAX(1), FP64_NORM_MAX(0), FP64_NORM_MIN(1),                     FP64_NORM_MIN(1) } },
+            { /* =>      */ { FP64_INF(1),      FP64_NORM_MAX(0), FP64_NORM_MIN(0),                     FP64_0(0)        } },
               /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_OM | X86_MXCSR_PM,
               /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_OE | X86_MXCSR_PE,
@@ -6135,5 +6135,5 @@
           { { /*src2     */ { FP64_INF(1),  FP64_INF(1),  FP64_INF(0), FP64_0(0)   } },
             { /*src1     */ { FP64_INF(0),  FP64_INF(0),  FP64_INF(1), FP64_0(0)   } },
-            { /* =>      */ { FP64_QNAN(1),  FP64_QNAN(1), FP64_INF(1), FP64_INF(0) } },
+            { /* =>      */ { FP64_QNAN(1), FP64_QNAN(1), FP64_INF(1), FP64_INF(0) } },
               /*mxcsr:in */ X86_MXCSR_RC_ZERO,
               /*128:out  */ X86_MXCSR_RC_ZERO | X86_MXCSR_IE,
@@ -6147,5 +6147,73 @@
               /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_UP,
               /*xcpt?    */ false, false },
-    /** @todo Overflow/Precision; Denormals; Normals; Invalids; Underflow,
+    /*
+     * Overflow, Precision.
+     */
+    /*11*/{ { /*src2     */ { FP64_0(0), FP64_0(0), FP64_NORM_MIN(0), FP64_NORM_MAX(0) } },
+            { /*src1     */ { FP64_0(0), FP64_0(0), FP64_NORM_MIN(1), FP64_NORM_MAX(1) } },
+            { /* =>      */ { FP64_0(0), FP64_0(0), FP64_0(0),        FP64_0(0)        } },
+              /*mxcsr:in */ 0,
+              /*128:out  */ 0,
+              /*256:out  */ X86_MXCSR_PE,
+              /*xcpt?    */ false, true },
+          { { /*src2     */ { FP64_NORM_MIN(1), FP64_NORM_MAX(1), FP64_NORM_MAX(1), FP64_NORM_MAX(1) } },
+            { /*src1     */ { FP64_NORM_MAX(0), FP64_NORM_MAX(1), FP64_NORM_MIN(0), FP64_NORM_MAX(0) } },
+            { /* =>      */ { FP64_INF(0),      FP64_NORM_MAX(0), FP64_NORM_MAX(1), FP64_0(0)       } },
+              /*mxcsr:in */ X86_MXCSR_OM | X86_MXCSR_PM,
+              /*128:out  */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_OE | X86_MXCSR_PE,
+              /*256:out  */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_OE | X86_MXCSR_PE,
+              /*xcpt?    */ false, false },
+          { { /*src2     */ { FP64_NORM_MAX(1), FP64_NORM_MAX(0), FP64_2(0),        FP64_1(0)        } },
+            { /*src1     */ { FP64_NORM_MAX(0), FP64_NORM_MAX(0), FP64_NORM_MAX(1), FP64_NORM_MAX(0) } },
+            { /* =>      */ { FP64_0(0),        FP64_NORM_MAX(1), FP64_NORM_MAX(1), FP64_1(0)        } },
+              /*mxcsr:in */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_RC_ZERO,
+              /*128:out  */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_RC_ZERO | X86_MXCSR_OE | X86_MXCSR_PE,
+              /*256:out  */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_RC_ZERO | X86_MXCSR_OE | X86_MXCSR_PE,
+              /*xcpt?    */ false, false },
+          { { /*src2     */ { FP64_NORM_MAX(0), FP64_NORM_MAX(1), FP64_0(0),        FP64_NORM_MIN(1) } },
+            { /*src1     */ { FP64_0(0),        FP64_NORM_MAX(0), FP64_NORM_MIN(1), FP64_NORM_MIN(0) } },
+            { /* =>      */ { FP64_NORM_MAX(1), FP64_INF(0),      FP64_V(1, 0, FP64_EXP_NORM_MIN + 1),  FP64_NORM_MIN(0) } },
+              /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_RC_UP,
+              /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_RC_UP | X86_MXCSR_OE | X86_MXCSR_PE,
+              /*256:out  */ X86_MXCSR_DAZ | X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_RC_UP | X86_MXCSR_OE | X86_MXCSR_PE,
+              /*xcpt?    */ false, false },
+#if 0
+          { { /*src2     */ { FP64_NORM_MAX(0), FP64_NORM_MAX(0), FP64_0(0),                                            FP64_NORM_MAX(0) } },
+            { /*src1     */ { FP64_NORM_MIN(1), FP64_NORM_MAX(0), FP64_NORM_MIN(0),                                     FP64_NORM_MAX(1) } },
+            { /* =>      */ { FP64_NORM_MAX(0), FP64_INF(0),      FP64_V(1, FP64_FRAC_NORM_MAX - 1, FP64_EXP_NORM_MAX), FP64_NORM_MAX(0) } },
+              /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_RC_UP,
+              /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_RC_UP | X86_MXCSR_OE | X86_MXCSR_PE,
+              /*256:out  */ X86_MXCSR_DAZ | X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_RC_UP | X86_MXCSR_OE | X86_MXCSR_PE,
+              /*xcpt?    */ false, false },
+          { { /*src2     */ { FP64_NORM_MAX(0), FP64_NORM_MAX(0), FP64_NORM_MAX(0), FP64_0(0)        } },
+            { /*src1     */ { FP64_NORM_MIN(1), FP64_NORM_MIN(1), FP64_NORM_MIN(0), FP64_NORM_MIN(0) } },
+            { /* =>      */ { FP64_V(1, 0, 2),  FP64_NORM_MAX(0), FP64_V(0, 0, 2),  FP64_NORM_MAX(0) } },
+              /*mxcsr:in */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_RC_ZERO,
+              /*128:out  */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_RC_ZERO | X86_MXCSR_OE | X86_MXCSR_PE,
+              /*256:out  */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_RC_ZERO | X86_MXCSR_OE | X86_MXCSR_PE,
+              /*xcpt?    */ false, false },
+          { { /*src2     */ { FP64_0(0),                                        FP64_NORM_MAX(0), FP64_NORM_MIN(1), FP64_NORM_MIN(0) } },
+            { /*src1     */ { FP64_NORM_MAX(1),                                 FP64_NORM_MAX(1), FP64_NORM_MIN(1), FP64_NORM_MIN(1) } },
+            { /* =>      */ { FP64_V(1, FP64_FRAC_NORM_MAX, FP64_EXP_NORM_MAX), FP64_NORM_MAX(0), FP64_V(1, 0, 2),  FP64_0(0)        } },
+              /*mxcsr:in */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_RC_ZERO,
+              /*128:out  */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_RC_ZERO | X86_MXCSR_OE | X86_MXCSR_PE,
+              /*256:out  */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_RC_ZERO | X86_MXCSR_OE | X86_MXCSR_PE,
+              /*xcpt?    */ false, false },
+          { { /*src2     */ { FP64_0(0), FP64_0(0), FP64_NORM_MAX(0), FP64_NORM_MAX(1) } },
+            { /*src1     */ { FP64_0(0), FP64_0(0), FP64_NORM_MAX(0), FP64_NORM_MAX(0) } },
+            { /* =>      */ { FP64_0(0), FP64_0(0), FP64_NORM_MAX(0), FP64_NORM_MAX(1) } },
+              /*mxcsr:in */ X86_MXCSR_RC_ZERO,
+              /*128:out  */ X86_MXCSR_RC_ZERO,
+              /*256:out  */ X86_MXCSR_RC_ZERO | X86_MXCSR_OE,
+              /*xcpt?    */ false, true },
+          { { /*src2     */ { FP64_NORM_SAFE_INT_MIN(0), FP64_NORM_SAFE_INT_MAX(0), FP64_NORM_SAFE_INT_MAX(0), FP64_NORM_SAFE_INT_MAX(1) } },
+            { /*src1     */ { FP64_NORM_SAFE_INT_MAX(0), FP64_NORM_SAFE_INT_MIN(0), FP64_NORM_SAFE_INT_MAX(0), FP64_NORM_SAFE_INT_MIN(0) } },
+            { /* =>      */ { FP64_NORM_SAFE_INT_MAX(0), FP64_NORM_SAFE_INT_MAX(0), FP64_NORM_SAFE_INT_MAX(0), FP64_0(0)                 } },
+              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
+              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO | X86_MXCSR_PE,
+              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO | X86_MXCSR_PE,
+              /*xcpt?    */ false, false },
+#endif
+    /** @todo Denormals; Normals; Invalids; Underflow,
      *        Precision; Rounding, FZ etc. */
     };
