Changeset 105923 in vbox for trunk/src/VBox/ValidationKit

Timestamp:

Sep 3, 2024 7:52:02 AM (5 months ago)

Author:

vboxsync

Message:

ValidationKit/bootsectors: bugref:10658 SIMD FP testcase: [v]hsubpd (W.I.P)

File:

• trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-4.c32 (modified) (3 diffs)

trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-4.c32

@@ -6109 +6109 @@
               /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
               /*xcpt?    */ false, false },
+          { { /*src2     */ { FP64_0(0), FP64_0(1), FP64_0(1), FP64_0(1) } },
+            { /*src1     */ { FP64_0(0), FP64_0(0), FP64_0(1), FP64_0(0) } },
+            { /* =>      */ { FP64_0(1), FP64_0(0), FP64_0(1), FP64_0(1) } },
+              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN,
+              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN,
+              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN,
+              /*xcpt?    */ false, false },
     /*
      * Infinity.
      */
-    /* 6*/{ { /*src2     */ { FP64_INF(0), FP64_INF(1), FP64_INF(0), FP64_INF(1) } },
+    /* 7*/{ { /*src2     */ { FP64_INF(0), FP64_INF(1), FP64_INF(0), FP64_INF(1) } },
             { /*src1     */ { FP64_INF(1), FP64_INF(0), FP64_0(0),   FP64_0(0)   } },
             { /* =>      */ { FP64_INF(1), FP64_INF(0), FP64_0(0),   FP64_INF(0) } },
@@ -6150 +6157 @@
      * Overflow, Precision.
      */
-    /*11*/{ { /*src2     */ { FP64_0(0), FP64_0(0), FP64_NORM_MIN(0), FP64_NORM_MAX(0) } },
+    /*12*/{ { /*src2     */ { FP64_0(0), FP64_0(0), FP64_NORM_MIN(0), FP64_NORM_MAX(0) } },
             { /*src1     */ { FP64_0(0), FP64_0(0), FP64_NORM_MIN(1), FP64_NORM_MAX(1) } },
             { /* =>      */ { FP64_0(0), FP64_0(0), FP64_0(0),        FP64_0(0)        } },
@@ -6213 +6220 @@
               /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_DAZ | X86_MXCSR_RC_UP | X86_MXCSR_PE,
               /*xcpt?    */ false, false },
-    /** @todo Denormals; Normals; Invalids; Underflow,
+    /*
+     * Denormals.
+     */
+    /*21*/{ { /*src2     */ { FP64_DENORM_MAX(0), FP64_0(0),          FP64_DENORM_MAX(0), FP64_0(0)          } },
+            { /*src1     */ { FP64_0(0),          FP64_DENORM_MAX(1), FP64_0(0),          FP64_DENORM_MAX(1) } },
+            { /* =>      */ { FP64_0(0),          FP64_0(0),          FP64_0(0),          FP64_0(0)          } },
+              /*mxcsr:in */ 0,
+              /*128:out  */ X86_MXCSR_DE,
+              /*256:out  */ X86_MXCSR_DE,
+              /*xcpt?    */ true, true },
+          { { /*src2     */ { FP64_DENORM_MAX(0), FP64_DENORM_MAX(0), FP64_DENORM_MIN(1), FP64_DENORM_MIN(1) } },
+            { /*src1     */ { FP64_DENORM_MIN(0), FP64_DENORM_MAX(0), FP64_DENORM_MAX(1), FP64_DENORM_MAX(1) } },
+            { /* =>      */ { FP64_0(0),          FP64_0(0),          FP64_0(0),          FP64_0(0)          } },
+              /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_XCPT_MASK,
+              /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_XCPT_MASK,
+              /*256:out  */ X86_MXCSR_DAZ | X86_MXCSR_XCPT_MASK,
+              /*xcpt?    */ false, false },
+          { { /*src2     */ { FP64_DENORM_MAX(0), FP64_0(0), FP64_0(0),          FP64_0(0) } },
+            { /*src1     */ { FP64_0(0),          FP64_0(0), FP64_DENORM_MIN(0), FP64_0(0) } },
+            { /* =>      */ { FP64_0(0),          FP64_0(0), FP64_0(0),          FP64_0(0) } },
+              /*mxcsr:in */ 0,
+              /*128:out  */ X86_MXCSR_DE,
+              /*256:out  */ X86_MXCSR_DE,
+              /*xcpt?    */ true, true },
+          { { /*src2     */ { FP64_0(0), FP64_0(0),          FP64_DENORM_MIN(1), FP64_DENORM_MAX(1) } },
+            { /*src1     */ { FP64_0(1), FP64_DENORM_MAX(0), FP64_DENORM_MAX(1), FP64_0(0)          } },
+            { /* =>      */ { FP64_0(1), FP64_0(0),          FP64_0(1),          FP64_0(0)          } },
+              /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_XCPT_MASK,
+              /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_XCPT_MASK,
+              /*256:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_XCPT_MASK,
+              /*xcpt?    */ false, false },
+          { { /*src2     */ { FP64_0(0), FP64_0(0), FP64_DENORM_MAX(0), FP64_DENORM_MAX(0) } },
+            { /*src1     */ { FP64_0(0), FP64_0(0), FP64_DENORM_MIN(1), FP64_DENORM_MIN(1) } },
+            { /* =>      */ { FP64_0(0), FP64_0(0), FP64_0(0),          FP64_0(0)          } },
+              /*mxcsr:in */ 0,
+              /*128:out  */ 0,
+              /*256:out  */ X86_MXCSR_DE,
+              /*xcpt?    */ false, true },
+          { { /*src2     */ { FP64_0(0), FP64_0(0), FP64_DENORM_MAX(1), FP64_DENORM_MAX(1) } },
+            { /*src1     */ { FP64_0(0), FP64_0(0), FP64_DENORM_MIN(1), FP64_DENORM_MIN(1) } },
+            { /* =>      */ { FP64_0(1), FP64_0(1), FP64_0(1),          FP64_0(1)          } },
+              /*mxcsr:in */ X86_MXCSR_XCPT_FLAGS | X86_MXCSR_RC_DOWN,
+              /*128:out  */ X86_MXCSR_XCPT_FLAGS | X86_MXCSR_RC_DOWN,
+              /*256:out  */ X86_MXCSR_XCPT_FLAGS | X86_MXCSR_RC_DOWN | X86_MXCSR_DE,
+              /*xcpt?    */ false, true },
+    /** @todo Normals; Invalids; Underflow,
      *        Precision; Rounding, FZ etc. */
     };