Changeset 105942 in vbox for trunk/src/VBox/ValidationKit/bootsectors

Timestamp:

Sep 4, 2024 10:21:55 AM (5 months ago)

Author:

vboxsync

Message:

ValidationKit/bootsectors: bugref:10658 SIMD FP testcase: [v]addsubps (W.I.P)

File:

• trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-4.c32 (modified) (1 diff)

trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-4.c32

@@ -8398 +8398 @@
               /*256:out  */ X86_MXCSR_PE,
               /*xcpt?    */ true, true },
-    /** @todo Normals; Denormals; Invalids; Rounding; FZ etc. */
+    /*
+     * Normals.
+     */
+    /*24*/{ { /*src2     */ { FP32_V(0, 0,        0x7d)/*0.25*/, FP32_V(0, 0x600000, 0x7f)/* 1.75*/, FP32_V(0, 0,        0x7d)/*0.25*/, FP32_V(1, 0,        0x7e)/*-0.50*/, FP32_V(0, 0x400000, 0x7e)/* 0.75*/, FP32_V(0, 0x600000, 0x7f)/* 1.75*/, FP32_V(0, 0,        0x7e)/*0.50*/, FP32_V(0, 0x534000, 0x86)/*211.25*/} },
+            { /*src1     */ { FP32_V(0, 0x600000, 0x7f)/*1.75*/, FP32_V(1, 0,        0x7d)/*-0.25*/, FP32_V(0, 0x400000, 0x7e)/*0.75*/, FP32_V(1, 0,        0x7d)/*-0.25*/, FP32_V(0, 0,        0x7e)/* 0.50*/, FP32_V(1, 0,        0x7d)/*-0.25*/, FP32_V(0, 0x400000, 0x7e)/*0.75*/, FP32_1(1)                /*- 1.00*/} },
+            { /* =>      */ { FP32_V(0, 0x400000, 0x7f)/*1.50*/, FP32_V(0, 0x400000, 0x7f)/* 1.50*/, FP32_V(0, 0,        0x7e)/*0.50*/, FP32_V(1, 0x400000, 0x7e)/*-0.75*/, FP32_V(1, 0,        0x7d)/*-0.25*/, FP32_V(0, 0x400000, 0x7f)/* 1.50*/, FP32_V(0, 0,        0x7d)/*0.25*/, FP32_V(0, 0x524000, 0x86)/*210.25*/} },
+              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
+              /*128:out  */ X86_MXCSR_XCPT_MASK,
+              /*256:out  */ X86_MXCSR_XCPT_MASK,
+              /*xcpt?    */ false, false },
+          { { /*src2     */ { FP32_V(0, 0x5ca5b8, 0x93)/*1807543*/, FP32_V(0, 0x5ca5b8, 0x93)/*1807543*/, FP32_V(0, 0x600000, 0x81)/* 7*/, FP32_V(0, 0x5c0000, 0x84)/*55*/, FP32_V(0, 0x534000, 0x86)/*211.25*/, FP32_V(0, 0x2514d6, 0x93)/*1352346.75*/, FP32_V(0, 0x7c9000, 0x88)/*   1010.25*/, FP32_V(0, 0x534000, 0x86)/*211.25*/ } },
+            { /*src1     */ { FP32_V(0, 0x669050, 0x93)/*1888778*/, FP32_V(0, 0x1ea980, 0x8f)/*  81235*/, FP32_V(0, 0x780000, 0x84)/*62*/, FP32_V(0, 0x600000, 0x81)/* 7*/, FP32_1(0)                /*  1.00*/, FP32_V(0, 0x7c9000, 0x88)/*   1010.25*/, FP32_V(0, 0x253468, 0x93)/*1353357.00*/, FP32_1(1)                /*- 1.00*/ } },
+            { /* =>      */ { FP32_V(0, 0x1ea980, 0x8f)/*  81235*/, FP32_V(0, 0x669050, 0x93)/*1888778*/, FP32_V(0, 0x5c0000, 0x84)/*55*/, FP32_V(0, 0x780000, 0x84)/*62*/, FP32_V(1, 0x524000, 0x86)/*210.25*/, FP32_V(0, 0x253468, 0x93)/*1353357.00*/, FP32_V(0, 0x2514d6, 0x93)/*1352346.75*/, FP32_V(0, 0x524000, 0x86)/*210.25*/ } },
+              /*mxcsr:in */ 0,
+              /*128:out  */ 0,
+              /*256:out  */ 0,
+              /*xcpt?    */ false, false },
+          { { /*src2     */ { FP32_V(0, 0x6cb99c, 0x97)/*31028024*/, FP32_V(0, 0x74429f, 0x97)/*32015678*/, FP32_V(1, 0x3c614e, 0x96)/*-12345678*/, FP32_V(0, 0x3c614e, 0x96)/*12345678*/, FP32_V(0, 0x712060, 0x92)/*  987654*/, FP32_V(0, 0x74429f, 0x97)/*32015678*/, FP32_V(0, 0x2514d6, 0x93)/* 1352346.75*/, FP32_V(0, 0x3c614e, 0x96)/*12345678*/ } },
+            { /*src1     */ { FP32_V(0, 0x74429f, 0x97)/*32015678*/, FP32_V(1, 0x712060, 0x92)/*- 987654*/, FP32_V(0, 0x3c614e, 0x96)/* 12345678*/, FP32_V(0, 0x3c614e, 0x96)/*12345678*/, FP32_V(0, 0x74429f, 0x97)/*32015678*/, FP32_V(1, 0x712060, 0x92)/*- 987654*/, FP32_V(1, 0x7c9000, 0x88)/*   -1010.25*/, FP32_V(0, 0x3c614e, 0x96)/*12345678*/ } },
+            { /* =>      */ { FP32_V(0, 0x712060, 0x92)/*  987654*/, FP32_V(0, 0x6cb99c, 0x97)/*31028024*/, FP32_V(0, 0x3c614e, 0x97)/* 24691356*/, FP32_V(0, 0x3c614e, 0x97)/*24691356*/, FP32_V(0, 0x6cb99c, 0x97)/*31028024*/, FP32_V(0, 0x6cb99c, 0x97)/*31028024*/, FP32_V(1, 0x253468, 0x93)/*-1353357.00*/, FP32_V(0, 0x3c614e, 0x97)/*24691356*/ } },
+              /*mxcsr:in */ X86_MXCSR_FZ,
+              /*128:out  */ X86_MXCSR_FZ,
+              /*256:out  */ X86_MXCSR_FZ,
+              /*xcpt?    */ false, false },
+          { { /*src2     */ { FP32_1(0),                                                FP32_V(0, FP32_FRAC_NORM_MAX - 1, FP32_EXP_SAFE_INT_MAX), FP32_1(1),                                                FP32_NORM_SAFE_INT_MAX(0),                                FP32_1(1),                                                FP32_V(0, FP32_FRAC_NORM_MAX - 1, FP32_EXP_SAFE_INT_MAX), FP32_NORM_SAFE_INT_MAX(0),               FP32_NORM_SAFE_INT_MAX(0)                                } },
+            { /*src1     */ { FP32_NORM_SAFE_INT_MAX(0),                                FP32_1(0),                                                FP32_V(0, FP32_FRAC_NORM_MAX - 1, FP32_EXP_SAFE_INT_MAX), FP32_1(1),                                                FP32_V(0, FP32_FRAC_NORM_MAX - 1, FP32_EXP_SAFE_INT_MAX), FP32_1(0),                                                FP32_V(0, 0, FP32_EXP_SAFE_INT_MAX + 1), FP32_1(1)                                                } },
+            { /* =>      */ { FP32_V(0, FP32_FRAC_NORM_MAX - 1, FP32_EXP_SAFE_INT_MAX), FP32_NORM_SAFE_INT_MAX(0),                                FP32_NORM_SAFE_INT_MAX(0),                                FP32_V(0, FP32_FRAC_NORM_MAX - 1, FP32_EXP_SAFE_INT_MAX), FP32_NORM_SAFE_INT_MAX(0),                                FP32_NORM_SAFE_INT_MAX(0),                                FP32_1(0),                               FP32_V(0, FP32_FRAC_NORM_MAX - 1, FP32_EXP_SAFE_INT_MAX) } },
+              /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_RC_UP,
+              /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_RC_UP,
+              /*256:out  */ X86_MXCSR_DAZ | X86_MXCSR_RC_UP,
+              /*xcpt?    */ false, false },
+          { { /*src2     */ { FP32_NORM_SAFE_INT_MIN(0), FP32_NORM_SAFE_INT_MIN(0), FP32_NORM_SAFE_INT_MIN(0),               FP32_0(0),                 FP32_0(0),                 FP32_NORM_SAFE_INT_MIN(0), FP32_1(0),                               FP32_NORM_SAFE_INT_MIN(0)               } },
+            { /*src1     */ { FP32_NORM_SAFE_INT_MIN(0), FP32_NORM_SAFE_INT_MIN(1), FP32_V(0, 0, FP32_EXP_SAFE_INT_MIN + 1), FP32_NORM_SAFE_INT_MIN(1), FP32_NORM_SAFE_INT_MIN(1), FP32_0(0),                 FP32_NORM_SAFE_INT_MAX(1),               FP32_NORM_SAFE_INT_MIN(0)               } },
+            { /* =>      */ { FP32_0(1),                 FP32_0(1),                 FP32_NORM_SAFE_INT_MIN(0),               FP32_NORM_SAFE_INT_MIN(1), FP32_NORM_SAFE_INT_MIN(1), FP32_NORM_SAFE_INT_MIN(0), FP32_V(1, 0, FP32_EXP_SAFE_INT_MAX + 1), FP32_V(0, 0, FP32_EXP_SAFE_INT_MIN + 1) } },
+              /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
+              /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
+              /*256:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
+              /*xcpt?    */ false, false },
+          { { /*src2     */ { FP32_V(0, 0x3ce348, 0x90)/*193421.125*/, FP32_V(0, 0x600000, 0x7e)/*      0.875*/, FP32_V(1, 0x0a19f0, 0x8f)/*-70707.875*/, FP32_V(0, 0x3ce348, 0x90)/*193421.125*/, FP32_V(0, 0x00c6d3, 0x94)/*2109876.75*/, FP32_V(0, 0x6423f2, 0x92)/*934463.125*/, FP32_V(0, 0x316740, 0x8e)/* 45415.25*/, FP32_V(0, 0x16b43a, 0x93)/*1234567.25*/ } },
+            { /*src1     */ { FP32_V(0, 0x10c030, 0x92)/*592899.000*/, FP32_V(0, 0x769b50, 0x92)/*1010101.000*/, FP32_V(0, 0x52e0b4, 0x92)/*863755.250*/, FP32_V(0, 0x430ebc, 0x91)/*399477.875*/, FP32_V(0, 0x4c20f0, 0x94)/*3344444.00*/, FP32_V(1, 0x0a19f0, 0x8f)/*-70707.875*/, FP32_V(0, 0x792318, 0x91)/*510232.75*/, FP32_V(0, 0x00c6d3, 0x94)/*2109876.75*/ } },
+            { /* =>      */ { FP32_V(0, 0x430ebc, 0x91)/*399477.875*/, FP32_V(0, 0x769b5e, 0x92)/*1010101.875*/, FP32_V(0, 0x6423f2, 0x92)/*934463.125*/, FP32_V(0, 0x10c030, 0x92)/*592899.000*/, FP32_V(0, 0x16b43a, 0x93)/*1234567.25*/, FP32_V(0, 0x52e0b4, 0x92)/*863755.250*/, FP32_V(0, 0x62f630, 0x91)/*464817.50*/, FP32_V(0, 0x4c20f0, 0x94)/*3344444.00*/ } },
+              /*mxcsr:in */ X86_MXCSR_RC_DOWN,
+              /*128:out  */ X86_MXCSR_RC_DOWN,
+              /*256:out  */ X86_MXCSR_RC_DOWN,
+              /*xcpt?    */ false, false },
+    /** @todo Denormals; Invalids; Rounding; FZ etc. */
     };