Changeset 105995 in vbox for trunk/src/VBox/ValidationKit/bootsectors

Timestamp:

Sep 10, 2024 7:13:27 AM (3 months ago)

Author:

vboxsync

Message:

ValidationKit/bootsectors: bugref:10658 SIMD FP testcase: [v]addsubpd (W.I.P)

File:

• trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-4.c32 (modified) (1 diff)

trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-4.c32

@@ -8834 +8834 @@
               /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO,
               /*xcpt?    */ false, false },
-         /** @todo Overflow/Precision; Normals; Denormals; Invalids; Rounding; FZ
-          *        etc. */
+    /*
+     * Overflow, Precision.
+     */
+    /*24*/{ { /*src2     */ { FP64_0(0), FP64_0(0), FP64_NORM_MAX(1), FP64_NORM_MAX(0) } },
+            { /*src1     */ { FP64_0(0), FP64_0(0), FP64_NORM_MAX(1), FP64_NORM_MAX(0) } },
+            { /* =>      */ { FP64_0(0), FP64_0(0), FP64_0(0),        FP64_INF(0)      } },
+              /*mxcsr:in */ 0,
+              /*128:out  */ 0,
+              /*256:out  */ X86_MXCSR_OE,
+              /*xcpt?    */ false, true },
+          { { /*src2     */ { FP64_NORM_MIN(0),                                     FP64_NORM_MAX(0), FP64_1(0), FP64_NORM_MAX(1) } },
+            { /*src1     */ { FP64_NORM_MAX(0),                                     FP64_NORM_MAX(0), FP64_2(0), FP64_NORM_MAX(1) } },
+            { /* =>      */ { FP64_V(0, FP64_FRAC_NORM_MAX - 1, FP64_EXP_NORM_MAX), FP64_NORM_MAX(0), FP64_1(0), FP64_NORM_MAX(1) } },
+              /*mxcsr:in */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_RC_ZERO,
+              /*128:out  */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_RC_ZERO | X86_MXCSR_OE | X86_MXCSR_PE,
+              /*256:out  */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_RC_ZERO | X86_MXCSR_OE | X86_MXCSR_PE,
+              /*xcpt?    */ false, false },
+          { { /*src2     */ { FP64_NORM_MAX(0), FP64_1(0), FP64_0(0),       FP64_NORM_MAX(0) } },
+            { /*src1     */ { FP64_NORM_MAX(1), FP64_1(0), FP64_NORM_V3(1), FP64_NORM_MAX(0) } },
+            { /* =>      */ { FP64_NORM_MAX(1), FP64_2(0), FP64_NORM_V3(1), FP64_NORM_MAX(0) } },
+              /*mxcsr:in */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_RC_ZERO,
+              /*128:out  */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_RC_ZERO | X86_MXCSR_OE | X86_MXCSR_PE,
+              /*256:out  */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_RC_ZERO | X86_MXCSR_OE | X86_MXCSR_PE,
+              /*xcpt?    */ false, false },
+          { { /*src2     */ { FP64_NORM_MAX(0), FP64_NORM_MIN(1),                     FP64_NORM_V3(0), FP64_NORM_MAX(0),  } },
+            { /*src1     */ { FP64_NORM_MAX(0), FP64_NORM_MIN(1),                     FP64_NORM_V3(0), FP64_NORM_MAX(0),  } },
+            { /* =>      */ { FP64_0(0),        FP64_V(1, 0, FP64_EXP_NORM_MIN + 1),  FP64_0(0),       FP64_INF(0),       } },
+              /*mxcsr:in */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
+              /*128:out  */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
+              /*256:out  */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP | X86_MXCSR_OE | X86_MXCSR_PE,
+              /*xcpt?    */ false, false },
+          { { /*src2     */ { FP64_NORM_MAX(0),                                     FP64_NORM_MIN(1),                    FP64_0(0), FP64_NORM_MAX(0) } },
+            { /*src1     */ { FP64_NORM_MIN(0),                                     FP64_NORM_MIN(1),                    FP64_0(0), FP64_NORM_MAX(0) } },
+            { /* =>      */ { FP64_V(1, FP64_FRAC_NORM_MAX - 1, FP64_EXP_NORM_MAX), FP64_V(1, 0, FP64_EXP_NORM_MIN + 1), FP64_0(0), FP64_INF(0)      } },
+              /*mxcsr:in */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
+              /*128:out  */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP | X86_MXCSR_PE,
+              /*256:out  */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP | X86_MXCSR_OE | X86_MXCSR_PE,
+              /*xcpt?    */ false, false },
+          { { /*src2     */ { FP64_NORM_MIN(1), FP64_NORM_MAX(0), FP64_NORM_MAX(0), FP64_NORM_V2(1) } },
+            { /*src1     */ { FP64_NORM_MIN(1), FP64_NORM_MAX(0), FP64_NORM_MAX(1), FP64_0(0)       } },
+            { /* =>      */ { FP64_0(1),        FP64_NORM_MAX(0), FP64_INF(1),      FP64_NORM_V2(1) } },
+              /*mxcsr:in */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
+              /*128:out  */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN | X86_MXCSR_OE | X86_MXCSR_PE,
+              /*256:out  */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN | X86_MXCSR_OE | X86_MXCSR_PE,
+              /*xcpt?    */ false, false },
+          { { /*src2     */ { FP64_NORM_MAX(0), FP64_NORM_MAX(1), FP64_NORM_MAX(1), FP64_NORM_MAX(0) } },
+            { /*src1     */ { FP64_NORM_MAX(0), FP64_NORM_MAX(1), FP64_NORM_MAX(1), FP64_NORM_MAX(0) } },
+            { /* =>      */ { FP64_NORM_MAX(0), FP64_NORM_MAX(1), FP64_NORM_MAX(1), FP64_NORM_MAX(0) } },
+              /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ,
+              /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_OE,
+              /*256:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_OE,
+              /*xcpt?    */ true, true },
+          { { /*src2     */ { FP64_NORM_MAX(0), FP64_NORM_MAX(1), FP64_NORM_MAX(1), FP64_NORM_MAX(0) } },
+            { /*src1     */ { FP64_NORM_MAX(0), FP64_NORM_MAX(1), FP64_NORM_MAX(1), FP64_NORM_MAX(0) } },
+            { /* =>      */ { FP64_0(0),        FP64_NORM_MAX(1), FP64_0(0),        FP64_NORM_MAX(0) } },
+              /*mxcsr:in */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_RC_ZERO,
+              /*128:out  */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_RC_ZERO | X86_MXCSR_OE | X86_MXCSR_PE,
+              /*256:out  */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_RC_ZERO | X86_MXCSR_OE | X86_MXCSR_PE,
+              /*xcpt?    */ false, false },
+          { { /*src2     */ { FP64_NORM_MAX(0), FP64_NORM_MAX(1), FP64_NORM_MAX(1), FP64_NORM_MAX(0) } },
+            { /*src1     */ { FP64_NORM_MAX(0), FP64_NORM_MAX(1), FP64_NORM_MAX(1), FP64_NORM_MAX(0) } },
+            { /* =>      */ { FP64_0(0),        FP64_NORM_MAX(1), FP64_0(0),        FP64_INF(0)      } },
+              /*mxcsr:in */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_RC_UP,
+              /*128:out  */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_RC_UP | X86_MXCSR_OE | X86_MXCSR_PE,
+              /*256:out  */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_RC_UP | X86_MXCSR_OE | X86_MXCSR_PE,
+              /*xcpt?    */ false, false },
+          { { /*src2     */ { FP64_NORM_SAFE_INT_MIN(0),                            FP64_NORM_MAX(0), FP64_0(0), FP64_NORM_SAFE_INT_MAX(1)                            } },
+            { /*src1     */ { FP64_NORM_SAFE_INT_MAX(0),                            FP64_NORM_MAX(1), FP64_0(0), FP64_NORM_SAFE_INT_MAX(1)                            } },
+            { /* =>      */ { FP64_V(0, FP64_FRAC_NORM_MAX, FP64_EXP_SAFE_INT_MAX), FP64_NORM_MAX(1), FP64_0(0), FP64_V(1, FP64_FRAC_NORM_MAX, FP64_EXP_SAFE_INT_MAX) } },
+              /*mxcsr:in */ 0,
+              /*128:out  */ X86_MXCSR_PE,
+              /*256:out  */ X86_MXCSR_PE,
+              /*xcpt?    */ true, true },
+          { { /*src2     */ { FP64_NORM_SAFE_INT_MIN(0),                            FP64_NORM_MAX(0), FP64_0(0), FP64_NORM_SAFE_INT_MAX(1)                                } },
+            { /*src1     */ { FP64_NORM_SAFE_INT_MAX(0),                            FP64_NORM_MAX(1), FP64_0(0), FP64_NORM_SAFE_INT_MAX(1)                                } },
+            { /* =>      */ { FP64_V(0, FP64_FRAC_NORM_MAX, FP64_EXP_SAFE_INT_MAX), FP64_0(0),        FP64_0(0), FP64_V(1, FP64_FRAC_NORM_MAX, FP64_EXP_SAFE_INT_MAX + 1) } },
+              /*mxcsr:in */ 0,
+              /*128:out  */ X86_MXCSR_PE,
+              /*256:out  */ X86_MXCSR_PE,
+              /*xcpt?    */ true, true },
+    /** @todo Normals; Denormals; Invalids; Rounding; FZ etc. */
     };