VirtualBox

Changeset 106004 in vbox for trunk/include


Ignore:
Timestamp:
Sep 10, 2024 11:51:08 AM (8 months ago)
Author:
vboxsync
svn:sync-xref-src-repo-rev:
164750
Message:

Disassembler/ArmV8: Updates and start on floating point and SIMD instructions, bugref:10394

Location:
trunk/include/VBox
Files:
2 edited

Legend:

Unmodified
Added
Removed

  • trunk/include/VBox/dis-armv8.h

    r105850 r106004  
    44
    55/*
    6  * Copyright (C) 2023 Oracle and/or its affiliates.
     6 * Copyright (C) 2023-2024 Oracle and/or its affiliates.
    77 *
    88 * This file is part of VirtualBox base platform packages, as
    … …  
    4949/** @addtogroup grp_dis   VBox Disassembler
    5050 * @{ */
     51
     52typedef enum DISOPPARAMARMV8REGTYPE
     53{
     54    kDisOpParamArmV8RegType_Gpr_32Bit = 0,
     55    kDisOpParamArmV8RegType_Gpr_64Bit,
     56    kDisOpParamArmV8RegType_FpReg_Single,
     57    kDisOpParamArmV8RegType_FpReg_Double,
     58    kDisOpParamArmV8RegType_FpReg_Half,
     59    kDisOpParamArmV8RegType_Simd_Scalar_64Bit,
     60    kDisOpParamArmV8RegType_Simd_Scalar_128Bit,
     61    kDisOpParamArmV8RegType_Simd_Vector
     62} DISOPPARAMARMV8REGTYPE;
     63
    5164/**
    52  * GPR definition
     65 * Register definition
    5366 */
    5467typedef struct
    5568{
    56     /** Flag whether this is a 32-bit or 64-bit register. */
    57                      bool    f32Bit : 1;
    58     /** The register index. */
    59     RT_GCC_EXTENSION uint8_t idGpr  : 7;
     69    /** The register type (DISOPPARAMARMV8REGTYPE). */
     70    uint8_t  enmRegType;
     71    /** The register ID. */
     72    uint8_t  idReg;
    6073} DISOPPARAMARMV8REG;
    61 AssertCompileSize(DISOPPARAMARMV8REG, sizeof(uint8_t));
     74AssertCompileSize(DISOPPARAMARMV8REG, sizeof(uint16_t));
    6275/** Pointer to a disassembler GPR. */
    6376typedef DISOPPARAMARMV8REG *PDISOPPARAMARMV8REG;
    … …  
    7588    /** Any extension applied (DISARMV8OPPARMEXTEND). */
    7689    uint8_t                         enmExtend;
    77     /** The register operand. */
     90    /** The operand. */
    7891    union
    7992    {
    8093        /** General register index (DISGREG_XXX), applicable if DISUSE_REG_GEN32
    8194         * or DISUSE_REG_GEN64 is set in fUse. */
    82         DISOPPARAMARMV8REG          Gpr;
     95        DISOPPARAMARMV8REG          Reg;
    8396        /** IPRT System register encoding. */
    8497        uint16_t                    idSysReg;
    85         /**
    86          *  Conditional parameter (not a register I know but this saves us struct size and
    87          *  and these never occur at the same time, might get renamed if everything is done).
    88          *
    89          *  DISARMV8INSTRCOND
    90          */
     98        /** Conditional parameter - DISARMV8INSTRCOND */
    9199        uint8_t                     enmCond;
    92     } Reg;
     100        /** PState field (for MSR) - DISARMV8INSTRPSTATE. */
     101        uint8_t                     enmPState;
     102    } Op;
    93103    /** Register holding the offset. Applicable if DISUSE_INDEX is set in fUse. */
    94104    DISOPPARAMARMV8REG              GprIndex;
    … …  
    117127    /** Condition flag for the instruction - kArmv8InstrCond_Al if not conditional instruction. */
    118128    DISARMV8INSTRCOND   enmCond;
     129    /** Floating point type for floating point instructions. */
     130    DISARMV8INSTRFPTYPE enmFpType;
    119131    /** Operand size (for loads/stores primarily). */
    120132    uint8_t             cbOperand;

  • trunk/include/VBox/disopcode-armv8.h

    r105849 r106004  
    163163    OP_ARMV8_A64_ESB,
    164164    OP_ARMV8_A64_EXTR,
     165    OP_ARMV8_A64_FABS,
     166    OP_ARMV8_A64_FADD,
     167    OP_ARMV8_A64_FCCMP,
     168    OP_ARMV8_A64_FCCMPE,
     169    OP_ARMV8_A64_FCMP,
     170    OP_ARMV8_A64_FCMPE,
     171    OP_ARMV8_A64_FCSEL,
     172    OP_ARMV8_A64_FCVT,
     173    OP_ARMV8_A64_FCVTZS,
     174    OP_ARMV8_A64_FCVTZU,
     175    OP_ARMV8_A64_FDIV,
     176    OP_ARMV8_A64_FMADD,
     177    OP_ARMV8_A64_FMAX,
     178    OP_ARMV8_A64_FMAXNM,
     179    OP_ARMV8_A64_FMIN,
     180    OP_ARMV8_A64_FMINNM,
     181    OP_ARMV8_A64_FMOV,
     182    OP_ARMV8_A64_FMSUB,
     183    OP_ARMV8_A64_FMUL,
     184    OP_ARMV8_A64_FNEG,
     185    OP_ARMV8_A64_FNMADD,
     186    OP_ARMV8_A64_FNMSUB,
     187    OP_ARMV8_A64_FNMUL,
     188    OP_ARMV8_A64_FRINT32X,
     189    OP_ARMV8_A64_FRINT32Z,
     190    OP_ARMV8_A64_FRINT64X,
     191    OP_ARMV8_A64_FRINT64Z,
     192    OP_ARMV8_A64_FRINTA,
     193    OP_ARMV8_A64_FRINTI,
     194    OP_ARMV8_A64_FRINTM,
     195    OP_ARMV8_A64_FRINTN,
     196    OP_ARMV8_A64_FRINTP,
     197    OP_ARMV8_A64_FRINTX,
     198    OP_ARMV8_A64_FRINTZ,
     199    OP_ARMV8_A64_FSQRT,
     200    OP_ARMV8_A64_FSUB,
    165201    OP_ARMV8_A64_GMI,
    166202    OP_ARMV8_A64_HINT,
    … …  
    371407    OP_ARMV8_A64_SBFM,
    372408    OP_ARMV8_A64_SBFX,
     409    OP_ARMV8_A64_SCVTF,
    373410    OP_ARMV8_A64_SDIV,
    374411    OP_ARMV8_A64_SETF8,
    … …  
    400437    OP_ARMV8_A64_SEV,
    401438    OP_ARMV8_A64_SEVL,
     439    OP_ARMV8_A64_SHL,
    402440    OP_ARMV8_A64_SMADDL,
    403441    OP_ARMV8_A64_SMC,
    … …  
    408446    OP_ARMV8_A64_SMULH,
    409447    OP_ARMV8_A64_SMULL,
     448    OP_ARMV8_A64_SQRSHRN,
     449    OP_ARMV8_A64_SQSHL,
     450    OP_ARMV8_A64_SQSHRN,
     451    OP_ARMV8_A64_SRSHR,
     452    OP_ARMV8_A64_SRSRA,
    410453    OP_ARMV8_A64_SSBB,
     454    OP_ARMV8_A64_SSHR,
     455    OP_ARMV8_A64_SSRA,
    411456    OP_ARMV8_A64_ST2G,
    412457    OP_ARMV8_A64_ST64B,
    … …  
    498543    OP_ARMV8_A64_UBFM,
    499544    OP_ARMV8_A64_UBFX,
     545    OP_ARMV8_A64_UCVTF,
    500546    OP_ARMV8_A64_UDF,
    501547    OP_ARMV8_A64_UDIV,
    … …  
    553599
    554600
     601/** Armv8 PState fields.    */
     602typedef enum DISARMV8INSTRPSTATE
     603{
     604    kDisArmv8InstrPState_SPSel = 0,
     605    kDisArmv8InstrPState_DAIFSet,
     606    kDisArmv8InstrPState_DAIFClr,
     607    kDisArmv8InstrPState_UAO,
     608    kDisArmv8InstrPState_PAN,
     609    kDisArmv8InstrPState_ALLINT,
     610    kDisArmv8InstrPState_PM,
     611    kDisArmv8InstrPState_SSBS,
     612    kDisArmv8InstrPState_DIT,
     613    kDisArmv8InstrPState_SVCRSM,
     614    kDisArmv8InstrPState_SVCRZA,
     615    kDisArmv8InstrPState_SVCRSMZA,
     616    kDisArmv8InstrPState_TCO
     617} DISARMV8INSTRPSTATE;
     618
     619
     620/**
     621 * Floating point types.
     622 */
     623typedef enum DISARMV8INSTRFPTYPE
     624{
     625    kDisArmv8InstrFpType_Invalid = 0,
     626    kDisArmv8InstrFpType_Single,
     627    kDisArmv8InstrFpType_Double,
     628    kDisArmv8InstrFpType_Half
     629} DISARMV8INSTRFPTYPE;
     630
     631
    555632/** @defgroup grp_dis_opparam_armv8 Opcode parameters (DISOPCODE::fParam1,
    556633 *            DISOPCODE::fParam2, DISOPCODE::fParam3)
    … …  
    566643    /** Parameter is not used. */
    567644    kDisArmv8OpParmNone = 0,
    568     /** Imediate value. */
     645    /** Immediate value. */
    569646    kDisArmv8OpParmImm,
    570647    /** Relative address immediate. */
    571648    kDisArmv8OpParmImmRel,
    572     /** General purpose register. */
    573     kDisArmv8OpParmGpr,
     649    /** Register. */
     650    kDisArmv8OpParmReg,
    574651    /** System register. */
    575652    kDisArmv8OpParmSysReg,
    … …  
    577654    kDisArmv8OpParmAddrInGpr,
    578655    /** Conditional as parameter (CCMN/CCMP). */
    579     kDisArmv8OpParmCond
     656    kDisArmv8OpParmCond,
     657    /** PSTATE field (specific to MSR). */
     658    kDisArmv8OpParmPState
    580659} DISARMV8OPPARM;
    581660
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