Changeset 106014 in vbox for trunk/src/VBox/ValidationKit/bootsectors
- Timestamp:
- Sep 11, 2024 7:40:14 PM (5 months ago)
- File:
-
- 1 edited
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trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-4.c32
r106013 r106014 494 494 }; 495 495 496 /** Packed single-precision invalid values. */ 497 #define BS3CPUINSTR4_PS_INVALIDS \ 498 /*0 */{ { /*src2 */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V0), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V5) } }, \ 499 { /*src1 */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4) } }, \ 500 { /* => */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4) } }, \ 501 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, \ 502 /*128:out */ X86_MXCSR_XCPT_MASK, \ 503 /*256:out */ X86_MXCSR_XCPT_MASK, \ 504 /*xcpt? */ false, false }, \ 505 { { /*src2 */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V0), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V5) } }, \ 506 { /*src1 */ { FP32_SNAN(0), FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V4) } }, \ 507 { /* => */ { FP32_QNAN_V(0, 1), FP32_QNAN_V(0, 1), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4) } }, \ 508 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, \ 509 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, \ 510 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, \ 511 /*xcpt? */ false, false }, \ 512 { { /*src2 */ { FP32_SNAN(0), FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V6) } }, \ 513 { /*src1 */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1) } }, \ 514 { /* => */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1) } }, \ 515 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ, \ 516 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_IE, \ 517 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_IE, \ 518 /*xcpt? */ false, false }, \ 519 { { /*src2 */ { FP32_SNAN(0), FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V7), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V1) } }, \ 520 { /*src1 */ { FP32_SNAN(0), FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2) } }, \ 521 { /* => */ { FP32_QNAN_V(0, 1), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2) } }, \ 522 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, \ 523 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, \ 524 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, \ 525 /*xcpt? */ false, false }, \ 526 { { /*src2 */ { FP32_QNAN(0), FP32_QNAN_V(1, FP32_FRAC_NORM_MAX), FP32_NORM_V0(1), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_NORM_V3(0), FP32_QNAN_V(1, FP32_FRAC_V3), FP32_NORM_V5(0), FP32_QNAN_V(1, FP32_FRAC_V5) } }, \ 527 { /*src1 */ { FP32_1(0), FP32_1(1), FP32_QNAN_V(1, FP32_FRAC_V0), FP32_NORM_V2(1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_NORM_V4(0), FP32_QNAN_V(1, FP32_FRAC_V4), FP32_NORM_V6(1) } }, \ 528 { /* => */ { FP32_QNAN(0), FP32_QNAN_V(1, FP32_FRAC_NORM_MAX), FP32_QNAN_V(1, FP32_FRAC_V0), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(1, FP32_FRAC_V3), FP32_QNAN_V(1, FP32_FRAC_V4), FP32_QNAN_V(1, FP32_FRAC_V5) } }, \ 529 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_XCPT_FLAGS, \ 530 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_XCPT_FLAGS, \ 531 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_XCPT_FLAGS, \ 532 /*xcpt? */ false, false }, \ 533 { { /*src2 */ { FP32_SNAN(1), FP32_SNAN_V(1, FP32_FRAC_NORM_MAX), FP32_NORM_V0(1), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_NORM_V3(0), FP32_SNAN_V(1, FP32_FRAC_V3), FP32_NORM_V5(0), FP32_SNAN_V(1, FP32_FRAC_V5) } }, \ 534 { /*src1 */ { FP32_1(0), FP32_1(0), FP32_SNAN_V(1, FP32_FRAC_V0), FP32_NORM_V2(1), FP32_SNAN_V(1, FP32_FRAC_V2), FP32_NORM_V4(0), FP32_SNAN_V(1, FP32_FRAC_V4), FP32_NORM_V6(1) } }, \ 535 { /* => */ { FP32_QNAN_V(1, 1), FP32_QNAN_V(1, FP32_FRAC_NORM_MAX), FP32_QNAN_V(1, FP32_FRAC_V0), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(1, FP32_FRAC_V2), FP32_QNAN_V(1, FP32_FRAC_V3), FP32_QNAN_V(1, FP32_FRAC_V4), FP32_QNAN_V(1, FP32_FRAC_V5) } }, \ 536 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, \ 537 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, \ 538 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, \ 539 /*xcpt? */ false, false }, \ 540 { { /*src2 */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V0), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V5) } }, \ 541 { /*src1 */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4) } }, \ 542 { /* => */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4) } }, \ 543 /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, \ 544 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, \ 545 /*256:out */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, \ 546 /*xcpt? */ false, false }, \ 547 { { /*src2 */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V0), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V5) } }, \ 548 { /*src1 */ { FP32_SNAN(0), FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V4) } }, \ 549 { /* => */ { FP32_QNAN_V(0, 1), FP32_QNAN_V(0, 1), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4) } }, \ 550 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, \ 551 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE, \ 552 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE, \ 553 /*xcpt? */ true, true }, \ 554 { { /*src2 */ { FP32_SNAN(0), FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V6) } }, \ 555 { /*src1 */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1) } }, \ 556 { /* => */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1) } }, \ 557 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP, \ 558 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP | X86_MXCSR_IE, \ 559 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP | X86_MXCSR_IE, \ 560 /*xcpt? */ true, true }, \ 561 { { /*src2 */ { FP32_SNAN(0), FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V7), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V1) } }, \ 562 { /*src1 */ { FP32_SNAN(0), FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2) } }, \ 563 { /* => */ { FP32_QNAN_V(0, 1), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2) } }, \ 564 /*mxcsr:in */ X86_MXCSR_RC_UP, \ 565 /*128:out */ X86_MXCSR_RC_UP | X86_MXCSR_IE, \ 566 /*256:out */ X86_MXCSR_RC_UP | X86_MXCSR_IE, \ 567 /*xcpt? */ true, true }, \ 568 { { /*src2 */ { FP32_QNAN(0), FP32_QNAN_V(1, FP32_FRAC_NORM_MAX), FP32_NORM_V0(1), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_NORM_V3(0), FP32_QNAN_V(1, FP32_FRAC_V3), FP32_NORM_V5(0), FP32_QNAN_V(1, FP32_FRAC_V5) } }, \ 569 { /*src1 */ { FP32_1(0), FP32_1(1), FP32_QNAN_V(1, FP32_FRAC_V0), FP32_NORM_V2(1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_NORM_V4(0), FP32_QNAN_V(1, FP32_FRAC_V4), FP32_NORM_V6(1) } }, \ 570 { /* => */ { FP32_QNAN(0), FP32_QNAN_V(1, FP32_FRAC_NORM_MAX), FP32_QNAN_V(1, FP32_FRAC_V0), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(1, FP32_FRAC_V3), FP32_QNAN_V(1, FP32_FRAC_V4), FP32_QNAN_V(1, FP32_FRAC_V5) } }, \ 571 /*mxcsr:in */ 0, \ 572 /*128:out */ 0, \ 573 /*256:out */ 0, \ 574 /*xcpt? */ false, false }, \ 575 /*11*/{ { /*src2 */ { FP32_SNAN(1), FP32_SNAN_V(1, FP32_FRAC_NORM_MAX), FP32_NORM_V0(1), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_NORM_V3(0), FP32_SNAN_V(1, FP32_FRAC_V3), FP32_NORM_V5(0), FP32_SNAN_V(1, FP32_FRAC_V5) } }, \ 576 { /*src1 */ { FP32_1(0), FP32_1(0), FP32_SNAN_V(1, FP32_FRAC_V0), FP32_NORM_V2(1), FP32_SNAN_V(1, FP32_FRAC_V2), FP32_NORM_V4(0), FP32_SNAN_V(1, FP32_FRAC_V4), FP32_NORM_V6(1) } }, \ 577 { /* => */ { FP32_QNAN_V(1, 1), FP32_QNAN_V(1, FP32_FRAC_NORM_MAX), FP32_QNAN_V(1, FP32_FRAC_V0), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(1, FP32_FRAC_V2), FP32_QNAN_V(1, FP32_FRAC_V3), FP32_QNAN_V(1, FP32_FRAC_V4), FP32_QNAN_V(1, FP32_FRAC_V5) } }, \ 578 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO, \ 579 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE, \ 580 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE, \ 581 /*xcpt? */ true, true }, \ 582 583 /** Packed double-precision floating-point invalid values. */ 584 #define BS3CPUINSTR4_PD_INVALIDS \ 585 /*0 */{ { /*src2 */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V0), FP64_QNAN_V(0, FP64_FRAC_V1) } }, \ 586 { /*src1 */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V2) } }, \ 587 { /* => */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V2) } }, \ 588 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, \ 589 /*128:out */ X86_MXCSR_XCPT_MASK, \ 590 /*256:out */ X86_MXCSR_XCPT_MASK, \ 591 /*xcpt? */ false, false }, \ 592 { { /*src2 */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V0), FP64_QNAN_V(0, FP64_FRAC_V2) } }, \ 593 { /*src1 */ { FP64_SNAN(0), FP64_SNAN_V(0, FP64_FRAC_NORM_MIN), FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_SNAN_V(0, FP64_FRAC_V1) } }, \ 594 { /* => */ { FP64_QNAN_V(0, 1), FP64_QNAN_V(0, 1), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V1) } }, \ 595 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, \ 596 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, \ 597 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, \ 598 /*xcpt? */ false, false }, \ 599 { { /*src2 */ { FP64_SNAN(0), FP64_SNAN_V(0, FP64_FRAC_NORM_MIN), FP64_SNAN_V(0, FP64_FRAC_V0), FP64_SNAN_V(0, FP64_FRAC_V1) } }, \ 600 { /*src1 */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V2), FP64_QNAN_V(0, FP64_FRAC_V3) } }, \ 601 { /* => */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V2), FP64_QNAN_V(0, FP64_FRAC_V3) } }, \ 602 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, \ 603 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, \ 604 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, \ 605 /*xcpt? */ false, false }, \ 606 { { /*src2 */ { FP64_SNAN(0), FP64_SNAN_V(0, FP64_FRAC_NORM_MIN), FP64_SNAN_V(0, FP64_FRAC_V1), FP64_SNAN_V(0, FP64_FRAC_V2) } }, \ 607 { /*src1 */ { FP64_SNAN(0), FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_SNAN_V(0, FP64_FRAC_V3), FP64_SNAN_V(0, FP64_FRAC_V0) } }, \ 608 { /* => */ { FP64_QNAN_V(0, 1), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V3), FP64_QNAN_V(0, FP64_FRAC_V0) } }, \ 609 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, \ 610 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, \ 611 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, \ 612 /*xcpt? */ false, false }, \ 613 { { /*src2 */ { FP64_QNAN(0), FP64_QNAN_V(1, FP64_FRAC_NORM_MAX), FP64_NORM_V0(1), FP64_QNAN_V(0, FP64_FRAC_V1) } }, \ 614 { /*src1 */ { FP64_1(0), FP64_1(1), FP64_QNAN_V(1, FP64_FRAC_V0), FP64_NORM_V2(1) } }, \ 615 { /* => */ { FP64_QNAN(0), FP64_QNAN_V(1, FP64_FRAC_NORM_MAX), FP64_QNAN_V(1, FP64_FRAC_V0), FP64_QNAN_V(0, FP64_FRAC_V1) } }, \ 616 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, \ 617 /*128:out */ X86_MXCSR_XCPT_MASK, \ 618 /*256:out */ X86_MXCSR_XCPT_MASK, \ 619 /*xcpt? */ false, false }, \ 620 { { /*src2 */ { FP64_SNAN(1), FP64_SNAN_V(1, FP64_FRAC_NORM_MAX), FP64_NORM_V0(1), FP64_SNAN_V(0, FP64_FRAC_V1) } }, \ 621 { /*src1 */ { FP64_1(0), FP64_1(0), FP64_SNAN_V(1, FP64_FRAC_V0), FP64_NORM_V2(1) } }, \ 622 { /* => */ { FP64_QNAN_V(1, 1), FP64_QNAN_V(1, FP64_FRAC_NORM_MAX), FP64_QNAN_V(1, FP64_FRAC_V0), FP64_QNAN_V(0, FP64_FRAC_V1) } }, \ 623 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, \ 624 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, \ 625 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, \ 626 /*xcpt? */ false, false }, \ 627 { { /*src2 */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V0), FP64_QNAN_V(0, FP64_FRAC_V2) } }, \ 628 { /*src1 */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V3) } }, \ 629 { /* => */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V3) } }, \ 630 /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, \ 631 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, \ 632 /*256:out */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, \ 633 /*xcpt? */ false, false }, \ 634 { { /*src2 */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V0), FP64_QNAN_V(0, FP32_FRAC_V1) } }, \ 635 { /*src1 */ { FP64_SNAN(0), FP64_SNAN_V(0, FP64_FRAC_NORM_MIN), FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_SNAN_V(0, FP32_FRAC_V2) } }, \ 636 { /* => */ { FP64_QNAN_V(0, 1), FP64_QNAN_V(0, 1), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP32_FRAC_V2) } }, \ 637 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, \ 638 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE, \ 639 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE, \ 640 /*xcpt? */ true, true }, \ 641 { { /*src2 */ { FP64_SNAN(0), FP64_SNAN_V(0, FP64_FRAC_NORM_MIN), FP64_SNAN_V(0, FP64_FRAC_V1), FP64_SNAN_V(0, FP64_FRAC_V1) } }, \ 642 { /*src1 */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V3), FP64_QNAN_V(0, FP64_FRAC_V2) } }, \ 643 { /* => */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V3), FP64_QNAN_V(0, FP64_FRAC_V2) } }, \ 644 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, \ 645 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE, \ 646 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE, \ 647 /*xcpt? */ true, true }, \ 648 { { /*src2 */ { FP64_SNAN(0), FP64_SNAN_V(0, FP64_FRAC_NORM_MIN), FP64_SNAN_V(0, FP64_FRAC_V1), FP64_SNAN_V(0, FP64_FRAC_V2) } }, \ 649 { /*src1 */ { FP64_SNAN(0), FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_SNAN_V(0, FP64_FRAC_V0), FP64_SNAN_V(0, FP64_FRAC_V3) } }, \ 650 { /* => */ { FP64_QNAN_V(0, 1), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V0), FP64_QNAN_V(0, FP64_FRAC_V3) } }, \ 651 /*mxcsr:in */ X86_MXCSR_RC_UP, \ 652 /*128:out */ X86_MXCSR_RC_UP | X86_MXCSR_IE, \ 653 /*256:out */ X86_MXCSR_RC_UP | X86_MXCSR_IE, \ 654 /*xcpt? */ true, true }, \ 655 { { /*src2 */ { FP64_QNAN(0), FP64_QNAN_V(1, FP64_FRAC_NORM_MAX), FP64_NORM_V0(1), FP64_QNAN_V(0, FP64_FRAC_V1) } }, \ 656 { /*src1 */ { FP64_1(0), FP64_1(1), FP64_QNAN_V(1, FP64_FRAC_V3), FP64_NORM_V2(1) } }, \ 657 { /* => */ { FP64_QNAN(0), FP64_QNAN_V(1, FP64_FRAC_NORM_MAX), FP64_QNAN_V(1, FP64_FRAC_V3), FP64_QNAN_V(0, FP64_FRAC_V1) } }, \ 658 /*mxcsr:in */ X86_MXCSR_RC_DOWN, \ 659 /*128:out */ X86_MXCSR_RC_DOWN, \ 660 /*256:out */ X86_MXCSR_RC_DOWN, \ 661 /*xcpt? */ false, false }, \ 662 /*11*/{ { /*src2 */ { FP64_SNAN(1), FP64_SNAN_V(1, FP64_FRAC_NORM_MAX), FP64_NORM_V0(1), FP64_SNAN_V(0, FP64_FRAC_V2) } }, \ 663 { /*src1 */ { FP64_1(0), FP64_1(0), FP64_SNAN_V(1, FP64_FRAC_V3), FP64_NORM_V2(1) } }, \ 664 { /* => */ { FP64_QNAN_V(1, 1), FP64_QNAN_V(1, FP64_FRAC_NORM_MAX), FP64_QNAN_V(1, FP64_FRAC_V3), FP64_QNAN_V(0, FP64_FRAC_V2) } }, \ 665 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO, \ 666 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE, \ 667 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE, \ 668 /*xcpt? */ true, true }, \ 669 670 /** Scalar single-precision floating-point invalid values. */ 671 #define BS3CPUINSTR4_SS_INVALIDS \ 672 /* QNan, QNan (Masked). */ \ 673 /*0 */{ { /*src2 */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V0), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V5) } }, \ 674 { /*src1 */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4) } }, \ 675 { /* => */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4) } }, \ 676 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, \ 677 /*128:out */ X86_MXCSR_XCPT_MASK, \ 678 /*256:out */ X86_MXCSR_XCPT_MASK, \ 679 /*xcpt? */ false, false }, \ 680 { { /*src2 */ { FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4) } }, \ 681 { /*src1 */ { FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V1) } }, \ 682 { /* => */ { FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V1) } }, \ 683 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, \ 684 /*128:out */ X86_MXCSR_XCPT_MASK, \ 685 /*256:out */ X86_MXCSR_XCPT_MASK, \ 686 /*xcpt? */ false, false }, \ 687 { { /*src2 */ { FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4) } }, \ 688 { /*src1 */ { FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V1) } }, \ 689 { /* => */ { FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V1) } }, \ 690 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, \ 691 /*128:out */ X86_MXCSR_XCPT_MASK, \ 692 /*256:out */ X86_MXCSR_XCPT_MASK, \ 693 /*xcpt? */ false, false }, \ 694 /* QNan, SNan (Masked). */ \ 695 { { /*src2 */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4) } }, \ 696 { /*src1 */ { FP32_SNAN(0), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V1) } }, \ 697 { /* => */ { FP32_QNAN_V(0, 1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V1) } }, \ 698 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, \ 699 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, \ 700 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, \ 701 /*xcpt? */ false, false }, \ 702 { { /*src2 */ { FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V0), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V5) } }, \ 703 { /*src1 */ { FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V4) } }, \ 704 { /* => */ { FP32_QNAN_V(0, 1), FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V4) } }, \ 705 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, \ 706 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, \ 707 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, \ 708 /*xcpt? */ false, false }, \ 709 { { /*src2 */ { FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V0), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V5) } }, \ 710 { /*src1 */ { FP32_SNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4) } }, \ 711 { /* => */ { FP32_SNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4) } }, \ 712 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, \ 713 /*128:out */ X86_MXCSR_XCPT_MASK, \ 714 /*256:out */ X86_MXCSR_XCPT_MASK, \ 715 /*xcpt? */ false, false }, \ 716 /* SNan, QNan (Masked). */ \ 717 { { /*src2 */ { FP32_SNAN(0), FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V6) } }, \ 718 { /*src1 */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1) } }, \ 719 { /* => */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1) } }, \ 720 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, \ 721 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, \ 722 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, \ 723 /*xcpt? */ false, false }, \ 724 { { /*src2 */ { FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V6) } }, \ 725 { /*src1 */ { FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1) } }, \ 726 { /* => */ { FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1) } }, \ 727 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, \ 728 /*128:out */ X86_MXCSR_XCPT_MASK, \ 729 /*256:out */ X86_MXCSR_XCPT_MASK, \ 730 /*xcpt? */ false, false }, \ 731 { { /*src2 */ { FP32_SNAN_V(0, FP32_FRAC_V0), FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V6) } }, \ 732 { /*src1 */ { FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1) } }, \ 733 { /* => */ { FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1) } }, \ 734 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, \ 735 /*128:out */ X86_MXCSR_XCPT_MASK, \ 736 /*256:out */ X86_MXCSR_XCPT_MASK, \ 737 /*xcpt? */ false, false }, \ 738 /* SNan, SNan (Masked). */ \ 739 { { /*src2 */ { FP32_SNAN(0), FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V7), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V1) } }, \ 740 { /*src1 */ { FP32_SNAN(0), FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2) } }, \ 741 { /* => */ { FP32_QNAN_V(0, 1), FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2) } }, \ 742 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, \ 743 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, \ 744 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, \ 745 /*xcpt? */ false, false }, \ 746 { { /*src2 */ { FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V7), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V1) } }, \ 747 { /*src1 */ { FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V0), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2) } }, \ 748 { /* => */ { FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V0), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2) } }, \ 749 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, \ 750 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, \ 751 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, \ 752 /*xcpt? */ false, false }, \ 753 { { /*src2 */ { FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V7), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V1) } }, \ 754 { /*src1 */ { FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V0) } }, \ 755 { /* => */ { FP32_QNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V0) } }, \ 756 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, \ 757 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, \ 758 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, \ 759 /*xcpt? */ false, false }, \ 760 /* QNan, Norm FP (Masked). */ \ 761 { { /*src2 */ { FP32_QNAN(0), FP32_QNAN_V(1, FP32_FRAC_NORM_MAX), FP32_NORM_V0(1), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_NORM_V3(0), FP32_QNAN_V(1, FP32_FRAC_V3), FP32_NORM_V5(0), FP32_QNAN_V(1, FP32_FRAC_V5) } }, \ 762 { /*src1 */ { FP32_1(0), FP32_1(1), FP32_QNAN_V(1, FP32_FRAC_V0), FP32_NORM_V2(1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_NORM_V4(0), FP32_QNAN_V(1, FP32_FRAC_V4), FP32_NORM_V6(1) } }, \ 763 { /* => */ { FP32_QNAN(0), FP32_1(1), FP32_QNAN_V(1, FP32_FRAC_V0), FP32_NORM_V2(1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_NORM_V4(0), FP32_QNAN_V(1, FP32_FRAC_V4), FP32_NORM_V6(1) } }, \ 764 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, \ 765 /*128:out */ X86_MXCSR_XCPT_MASK, \ 766 /*256:out */ X86_MXCSR_XCPT_MASK, \ 767 /*xcpt? */ false, false }, \ 768 /* SNan, Norm FP (Masked). */ \ 769 { { /*src2 */ { FP32_SNAN(1), FP32_SNAN_V(1, FP32_FRAC_NORM_MAX), FP32_NORM_V0(1), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_NORM_V3(0), FP32_SNAN_V(1, FP32_FRAC_V3), FP32_NORM_V5(0), FP32_SNAN_V(1, FP32_FRAC_V5) } }, \ 770 { /*src1 */ { FP32_1(0), FP32_1(0), FP32_SNAN_V(1, FP32_FRAC_V0), FP32_NORM_V2(1), FP32_SNAN_V(1, FP32_FRAC_V2), FP32_NORM_V4(0), FP32_SNAN_V(1, FP32_FRAC_V4), FP32_NORM_V6(1) } }, \ 771 { /* => */ { FP32_QNAN_V(1, 1), FP32_1(0), FP32_SNAN_V(1, FP32_FRAC_V0), FP32_NORM_V2(1), FP32_SNAN_V(1, FP32_FRAC_V2), FP32_NORM_V4(0), FP32_SNAN_V(1, FP32_FRAC_V4), FP32_NORM_V6(1) } }, \ 772 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, \ 773 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, \ 774 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, \ 775 /*xcpt? */ false, false }, \ 776 /* QNan, QNan (Unmasked). */ \ 777 /*14*/{ { /*src2 */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V0), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V5) } }, \ 778 { /*src1 */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4) } }, \ 779 { /* => */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4) } }, \ 780 /*mxcsr:in */ 0, \ 781 /*128:out */ 0, \ 782 /*256:out */ 0, \ 783 /*xcpt? */ false, false }, \ 784 { { /*src2 */ { FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4) } }, \ 785 { /*src1 */ { FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V1) } }, \ 786 { /* => */ { FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V1) } }, \ 787 /*mxcsr:in */ 0, \ 788 /*128:out */ 0, \ 789 /*256:out */ 0, \ 790 /*xcpt? */ false, false }, \ 791 { { /*src2 */ { FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4) } }, \ 792 { /*src1 */ { FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V1) } }, \ 793 { /* => */ { FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V1) } }, \ 794 /*mxcsr:in */ 0, \ 795 /*128:out */ 0, \ 796 /*256:out */ 0, \ 797 /*xcpt? */ false, false }, \ 798 \ 799 /* QNan, SNan (Unmasked). */ \ 800 { { /*src2 */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4) } }, \ 801 { /*src1 */ { FP32_SNAN(0), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V1) } }, \ 802 { /* => */ { FP32_QNAN_V(0, 1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V1) } }, \ 803 /*mxcsr:in */ 0, \ 804 /*128:out */ X86_MXCSR_IE, \ 805 /*256:out */ X86_MXCSR_IE, \ 806 /*xcpt? */ true, true }, \ 807 { { /*src2 */ { FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V0), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V5) } }, \ 808 { /*src1 */ { FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V4) } }, \ 809 { /* => */ { FP32_QNAN_V(0, 1), FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V4) } }, \ 810 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, \ 811 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN | X86_MXCSR_IE, \ 812 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN | X86_MXCSR_IE, \ 813 /*xcpt? */ true, true }, \ 814 { { /*src2 */ { FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V0), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V5) } }, \ 815 { /*src1 */ { FP32_SNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4) } }, \ 816 { /* => */ { FP32_SNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4) } }, \ 817 /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, \ 818 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, \ 819 /*256:out */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, \ 820 /*xcpt? */ false, false }, \ 821 /* SNan, QNan (Unmasked). */ \ 822 { { /*src2 */ { FP32_SNAN(0), FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V6) } }, \ 823 { /*src1 */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1) } }, \ 824 { /* => */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1) } }, \ 825 /*mxcsr:in */ X86_MXCSR_DAZ, \ 826 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_IE, \ 827 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_IE, \ 828 /*xcpt? */ true, true }, \ 829 { { /*src2 */ { FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V6) } }, \ 830 { /*src1 */ { FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1) } }, \ 831 { /* => */ { FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1) } }, \ 832 /*mxcsr:in */ X86_MXCSR_RC_UP, \ 833 /*128:out */ X86_MXCSR_RC_UP, \ 834 /*256:out */ X86_MXCSR_RC_UP, \ 835 /*xcpt? */ false, false }, \ 836 { { /*src2 */ { FP32_SNAN_V(0, FP32_FRAC_V0), FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V6) } }, \ 837 { /*src1 */ { FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1) } }, \ 838 { /* => */ { FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1) } }, \ 839 /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, \ 840 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, \ 841 /*256:out */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, \ 842 /*xcpt? */ false, false }, \ 843 /* SNan, SNan (Unmasked). */ \ 844 /*24*/{ { /*src2 */ { FP32_SNAN(0), FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V7), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V1) } }, \ 845 { /*src1 */ { FP32_SNAN(0), FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2) } }, \ 846 { /* => */ { FP32_QNAN_V(0, 1), FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2) } }, \ 847 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ, \ 848 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_IE, \ 849 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_IE, \ 850 /*xcpt? */ true, true }, \ 851 { { /*src2 */ { FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V7), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V1) } }, \ 852 { /*src1 */ { FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V0), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2) } }, \ 853 { /* => */ { FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V0), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2) } }, \ 854 /*mxcsr:in */ X86_MXCSR_RC_ZERO, \ 855 /*128:out */ X86_MXCSR_RC_ZERO | X86_MXCSR_IE, \ 856 /*256:out */ X86_MXCSR_RC_ZERO | X86_MXCSR_IE, \ 857 /*xcpt? */ true, true }, \ 858 { { /*src2 */ { FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V7), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V1) } }, \ 859 { /*src1 */ { FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V0) } }, \ 860 { /* => */ { FP32_QNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V0) } }, \ 861 /*mxcsr:in */ 0, \ 862 /*128:out */ X86_MXCSR_IE, \ 863 /*256:out */ X86_MXCSR_IE, \ 864 /*xcpt? */ true, true }, \ 865 /* QNan, Norm FP (Unmasked). */ \ 866 { { /*src2 */ { FP32_QNAN(0), FP32_QNAN_V(1, FP32_FRAC_NORM_MAX), FP32_NORM_V0(1), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_NORM_V3(0), FP32_QNAN_V(1, FP32_FRAC_V3), FP32_NORM_V5(0), FP32_QNAN_V(1, FP32_FRAC_V5) } }, \ 867 { /*src1 */ { FP32_1(0), FP32_1(1), FP32_QNAN_V(1, FP32_FRAC_V0), FP32_NORM_V2(1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_NORM_V4(0), FP32_QNAN_V(1, FP32_FRAC_V4), FP32_NORM_V6(1) } }, \ 868 { /* => */ { FP32_QNAN(0), FP32_1(1), FP32_QNAN_V(1, FP32_FRAC_V0), FP32_NORM_V2(1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_NORM_V4(0), FP32_QNAN_V(1, FP32_FRAC_V4), FP32_NORM_V6(1) } }, \ 869 /*mxcsr:in */ X86_MXCSR_FZ, \ 870 /*128:out */ X86_MXCSR_FZ, \ 871 /*256:out */ X86_MXCSR_FZ, \ 872 /*xcpt? */ false, false }, \ 873 /* SNan, Norm FP (Unmasked). */ \ 874 /*28*/{ { /*src2 */ { FP32_SNAN(1), FP32_SNAN_V(1, FP32_FRAC_NORM_MAX), FP32_NORM_V0(1), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_NORM_V3(0), FP32_SNAN_V(1, FP32_FRAC_V3), FP32_NORM_V5(0), FP32_SNAN_V(1, FP32_FRAC_V5) } }, \ 875 { /*src1 */ { FP32_1(0), FP32_1(0), FP32_SNAN_V(1, FP32_FRAC_V0), FP32_NORM_V2(1), FP32_SNAN_V(1, FP32_FRAC_V2), FP32_NORM_V4(0), FP32_SNAN_V(1, FP32_FRAC_V4), FP32_NORM_V6(1) } }, \ 876 { /* => */ { FP32_QNAN_V(1, 1), FP32_1(0), FP32_SNAN_V(1, FP32_FRAC_V0), FP32_NORM_V2(1), FP32_SNAN_V(1, FP32_FRAC_V2), FP32_NORM_V4(0), FP32_SNAN_V(1, FP32_FRAC_V4), FP32_NORM_V6(1) } }, \ 877 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, \ 878 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE, \ 879 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE, \ 880 /*xcpt? */ true, true }, \ 881 882 /** Scalar double-precision floating-point invalid values. */ 883 #define BS3CPUINSTR4_SD_INVALIDS \ 884 /* QNan, QNan (Masked). */ \ 885 /*0 */{ { /*src2 */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V0), FP64_QNAN_V(0, FP64_FRAC_V1) } }, \ 886 { /*src1 */ { FP64_QNAN(0), FP64_QNAN_V(1, FP64_FRAC_NORM_MIN), FP64_QNAN_V(1, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V2) } }, \ 887 { /* => */ { FP64_QNAN(0), FP64_QNAN_V(1, FP64_FRAC_NORM_MIN), FP64_QNAN_V(1, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V2) } }, \ 888 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, \ 889 /*128:out */ X86_MXCSR_XCPT_MASK, \ 890 /*256:out */ X86_MXCSR_XCPT_MASK, \ 891 /*xcpt? */ false, false }, \ 892 { { /*src2 */ { FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(1, FP64_FRAC_V1), FP64_QNAN_V(0, FP64_FRAC_V2), FP64_INF(0) } }, \ 893 { /*src1 */ { FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(1, FP64_FRAC_V2), FP64_QNAN_V(1, FP64_FRAC_V3), FP64_SNAN(1) } }, \ 894 { /* => */ { FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(1, FP64_FRAC_V2), FP64_QNAN_V(1, FP64_FRAC_V3), FP64_SNAN(1) } }, \ 895 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, \ 896 /*128:out */ X86_MXCSR_XCPT_MASK, \ 897 /*256:out */ X86_MXCSR_XCPT_MASK, \ 898 /*xcpt? */ false, false }, \ 899 { { /*src2 */ { FP64_QNAN_V(0, FP64_FRAC_V1), FP64_QNAN_V(0, FP64_FRAC_V1), FP64_QNAN_V(0, FP64_FRAC_V2), FP64_INF(1) } }, \ 900 { /*src1 */ { FP64_QNAN_V(0, FP64_FRAC_V0), FP64_QNAN_V(0, FP64_FRAC_V2), FP64_QNAN_V(1, FP64_FRAC_V3), FP64_QNAN(0) } }, \ 901 { /* => */ { FP64_QNAN_V(0, FP64_FRAC_V0), FP64_QNAN_V(0, FP64_FRAC_V2), FP64_QNAN_V(1, FP64_FRAC_V3), FP64_QNAN(0) } }, \ 902 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, \ 903 /*128:out */ X86_MXCSR_XCPT_MASK, \ 904 /*256:out */ X86_MXCSR_XCPT_MASK, \ 905 /*xcpt? */ false, false }, \ 906 /* QNan, SNan (Masked). */ \ 907 { { /*src2 */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_V1), FP64_QNAN_V(0, FP64_FRAC_V2), FP64_QNAN_V(0, FP64_FRAC_V3) } }, \ 908 { /*src1 */ { FP64_SNAN(0), FP64_SNAN_V(1, FP64_FRAC_V2), FP64_SNAN_V(0, FP64_FRAC_V1), FP64_SNAN_V(1, FP64_FRAC_V2) } }, \ 909 { /* => */ { FP64_QNAN_V(0, 1), FP64_QNAN_V(1, FP64_FRAC_V2), FP64_SNAN_V(0, FP64_FRAC_V1), FP64_SNAN_V(1, FP64_FRAC_V2) } }, \ 910 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, \ 911 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, \ 912 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, \ 913 /*xcpt? */ false, false }, \ 914 { { /*src2 */ { FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V0), FP64_QNAN_V(0, FP64_FRAC_V1) } }, \ 915 { /*src1 */ { FP64_SNAN_V(0, FP64_FRAC_NORM_MIN), FP64_SNAN_V(1, FP64_FRAC_NORM_MIN), FP64_SNAN_V(1, FP64_FRAC_NORM_MAX), FP64_SNAN_V(0, FP64_FRAC_V2) } }, \ 916 { /* => */ { FP64_QNAN_V(0, 1), FP64_SNAN_V(1, FP64_FRAC_NORM_MIN), FP64_SNAN_V(1, FP64_FRAC_NORM_MAX), FP64_SNAN_V(0, FP64_FRAC_V2) } }, \ 917 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, \ 918 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, \ 919 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, \ 920 /*xcpt? */ false, false }, \ 921 { { /*src2 */ { FP64_QNAN_V(0, FP64_FRAC_V1), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V0), FP64_INF(0) } }, \ 922 { /*src1 */ { FP64_SNAN_V(0, FP64_FRAC_V2), FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(1, FP64_FRAC_NORM_MAX), FP64_QNAN(1) } }, \ 923 { /* => */ { FP64_SNAN_V(0, FP64_FRAC_V2), FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(1, FP64_FRAC_NORM_MAX), FP64_QNAN(1) } }, \ 924 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, \ 925 /*128:out */ X86_MXCSR_XCPT_MASK, \ 926 /*256:out */ X86_MXCSR_XCPT_MASK, \ 927 /*xcpt? */ false, false }, \ 928 /* SNan, QNan (Masked). */ \ 929 { { /*src2 */ { FP64_SNAN(0), FP64_SNAN_V(0, FP64_FRAC_NORM_MIN), FP64_SNAN_V(0, FP64_FRAC_V1), FP64_SNAN_V(1, FP64_FRAC_V1) } }, \ 930 { /*src1 */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(1, FP64_FRAC_V3), FP64_QNAN_V(1, FP64_FRAC_V2) } }, \ 931 { /* => */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(1, FP64_FRAC_V3), FP64_QNAN_V(1, FP64_FRAC_V2) } }, \ 932 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, \ 933 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, \ 934 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, \ 935 /*xcpt? */ false, false }, \ 936 { { /*src2 */ { FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_SNAN_V(1, FP64_FRAC_NORM_MAX), FP64_SNAN_V(0, FP64_FRAC_V1), FP64_SNAN_V(0, FP64_FRAC_V1) } }, \ 937 { /*src1 */ { FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(1, FP64_FRAC_NORM_MIN), FP64_QNAN_V(1, FP64_FRAC_V3), FP64_QNAN_V(0, FP64_FRAC_V2) } }, \ 938 { /* => */ { FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(1, FP64_FRAC_NORM_MIN), FP64_QNAN_V(1, FP64_FRAC_V3), FP64_QNAN_V(0, FP64_FRAC_V2) } }, \ 939 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, \ 940 /*128:out */ X86_MXCSR_XCPT_MASK, \ 941 /*256:out */ X86_MXCSR_XCPT_MASK, \ 942 /*xcpt? */ false, false }, \ 943 { { /*src2 */ { FP64_SNAN_V(0, FP64_FRAC_V0), FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_SNAN_V(0, FP64_FRAC_V1), FP64_SNAN_V(0, FP64_FRAC_V1) } }, \ 944 { /*src1 */ { FP64_QNAN_V(0, FP64_FRAC_V1), FP64_QNAN_V(1, FP64_FRAC_NORM_MIN), FP64_QNAN_V(1, FP64_FRAC_V2), FP64_QNAN_V(1, FP64_FRAC_V3) } }, \ 945 { /* => */ { FP64_QNAN_V(0, FP64_FRAC_V1), FP64_QNAN_V(1, FP64_FRAC_NORM_MIN), FP64_QNAN_V(1, FP64_FRAC_V2), FP64_QNAN_V(1, FP64_FRAC_V3) } }, \ 946 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, \ 947 /*128:out */ X86_MXCSR_XCPT_MASK, \ 948 /*256:out */ X86_MXCSR_XCPT_MASK, \ 949 /*xcpt? */ false, false }, \ 950 /* SNan, SNan (Masked). */ \ 951 { { /*src2 */ { FP64_SNAN(0), FP64_SNAN_V(0, FP64_FRAC_NORM_MIN), FP64_SNAN_V(0, FP64_FRAC_V1), FP64_SNAN_V(0, FP64_FRAC_V2) } }, \ 952 { /*src1 */ { FP64_SNAN(0), FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_SNAN_V(0, FP64_FRAC_V0), FP64_SNAN_V(0, FP64_FRAC_V3) } }, \ 953 { /* => */ { FP64_QNAN_V(0, 1), FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_SNAN_V(0, FP64_FRAC_V0), FP64_SNAN_V(0, FP64_FRAC_V3) } }, \ 954 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, \ 955 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, \ 956 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, \ 957 /*xcpt? */ false, false }, \ 958 { { /*src2 */ { FP64_SNAN_V(0, FP64_FRAC_NORM_MIN), FP64_SNAN_V(0, FP64_FRAC_V2), FP64_SNAN_V(0, FP64_FRAC_V1), FP64_SNAN_V(0, FP64_FRAC_V2) } }, \ 959 { /*src1 */ { FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_SNAN_V(0, FP64_FRAC_V0), FP64_SNAN_V(0, FP64_FRAC_V2), FP64_SNAN_V(1, FP64_FRAC_V3) } }, \ 960 { /* => */ { FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_SNAN_V(0, FP64_FRAC_V0), FP64_SNAN_V(0, FP64_FRAC_V2), FP64_SNAN_V(1, FP64_FRAC_V3) } }, \ 961 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, \ 962 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, \ 963 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, \ 964 /*xcpt? */ false, false }, \ 965 { { /*src2 */ { FP64_SNAN_V(0, FP64_FRAC_V1), FP64_SNAN_V(0, FP64_FRAC_V2), FP64_SNAN_V(0, FP64_FRAC_V1), FP64_SNAN_V(0, FP64_FRAC_V2) } }, \ 966 { /*src1 */ { FP64_SNAN_V(0, FP64_FRAC_V0), FP64_SNAN_V(0, FP64_FRAC_V3), FP64_SNAN_V(0, FP64_FRAC_V0), FP64_SNAN_V(0, FP64_FRAC_V3) } }, \ 967 { /* => */ { FP64_QNAN_V(0, FP64_FRAC_V0), FP64_SNAN_V(0, FP64_FRAC_V3), FP64_SNAN_V(0, FP64_FRAC_V0), FP64_SNAN_V(0, FP64_FRAC_V3) } }, \ 968 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, \ 969 /*128:out */ X86_MXCSR_XCPT_MASK, \ 970 /*256:out */ X86_MXCSR_XCPT_MASK, \ 971 /*xcpt? */ false, false }, \ 972 /* QNan, Norm FP (Masked). */ \ 973 { { /*src2 */ { FP64_QNAN(0), FP64_QNAN_V(1, FP64_FRAC_NORM_MAX), FP64_NORM_V0(1), FP64_QNAN_V(0, FP64_FRAC_V1) } }, \ 974 { /*src1 */ { FP64_1(0), FP64_1(1), FP64_QNAN_V(1, FP64_FRAC_V0), FP64_NORM_V2(1) } }, \ 975 { /* => */ { FP64_QNAN(0), FP64_1(1), FP64_QNAN_V(1, FP64_FRAC_V0), FP64_NORM_V2(1) } }, \ 976 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, \ 977 /*128:out */ X86_MXCSR_XCPT_MASK, \ 978 /*256:out */ X86_MXCSR_XCPT_MASK, \ 979 /*xcpt? */ false, false }, \ 980 /* SNan, Norm FP (Masked). */ \ 981 { { /*src2 */ { FP64_SNAN(1), FP64_SNAN_V(1, FP64_FRAC_NORM_MAX), FP64_NORM_V0(1), FP64_SNAN_V(0, FP64_FRAC_V1) } }, \ 982 { /*src1 */ { FP64_1(0), FP64_1(0), FP64_SNAN_V(1, FP64_FRAC_V0), FP64_NORM_V2(1) } }, \ 983 { /* => */ { FP64_QNAN_V(1, 1), FP64_1(0), FP64_SNAN_V(1, FP64_FRAC_V0), FP64_NORM_V2(1) } }, \ 984 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, \ 985 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, \ 986 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, \ 987 /*xcpt? */ false, false }, \ 988 /* QNan, QNan (Unmasked). */ \ 989 /*14*/{ { /*src2 */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V0), FP64_QNAN_V(0, FP64_FRAC_V1) } }, \ 990 { /*src1 */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V2) } }, \ 991 { /* => */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V2) } }, \ 992 /*mxcsr:in */ 0, \ 993 /*128:out */ 0, \ 994 /*256:out */ 0, \ 995 /*xcpt? */ false, false }, \ 996 { { /*src2 */ { FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V1), FP64_QNAN_V(0, FP64_FRAC_V2), FP64_QNAN_V(0, FP64_FRAC_V3) } }, \ 997 { /*src1 */ { FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(0, FP64_FRAC_V2), FP64_QNAN_V(0, FP64_FRAC_V0), FP64_QNAN_V(0, FP64_FRAC_V2) } }, \ 998 { /* => */ { FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(0, FP64_FRAC_V2), FP64_QNAN_V(0, FP64_FRAC_V0), FP64_QNAN_V(0, FP64_FRAC_V2) } }, \ 999 /*mxcsr:in */ 0, \ 1000 /*128:out */ 0, \ 1001 /*256:out */ 0, \ 1002 /*xcpt? */ false, false }, \ 1003 { { /*src2 */ { FP64_QNAN_V(0, FP64_FRAC_V1), FP64_QNAN_V(0, FP64_FRAC_V1), FP64_QNAN_V(0, FP64_FRAC_V2), FP64_QNAN_V(0, FP64_FRAC_V3) } }, \ 1004 { /*src1 */ { FP64_QNAN_V(0, FP64_FRAC_V2), FP64_QNAN_V(1, FP64_FRAC_V2), FP64_QNAN_V(0, FP64_FRAC_V0), FP64_QNAN_V(1, FP64_FRAC_V0) } }, \ 1005 { /* => */ { FP64_QNAN_V(0, FP64_FRAC_V2), FP64_QNAN_V(1, FP64_FRAC_V2), FP64_QNAN_V(0, FP64_FRAC_V0), FP64_QNAN_V(1, FP64_FRAC_V0) } }, \ 1006 /*mxcsr:in */ 0, \ 1007 /*128:out */ 0, \ 1008 /*256:out */ 0, \ 1009 /*xcpt? */ false, false }, \ 1010 \ 1011 /* QNan, SNan (Unmasked). */ \ 1012 { { /*src2 */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_V1), FP64_QNAN_V(0, FP64_FRAC_V2), FP64_QNAN_V(0, FP64_FRAC_V3) } }, \ 1013 { /*src1 */ { FP64_SNAN(0), FP64_SNAN_V(1, FP64_FRAC_V2), FP64_SNAN_V(1, FP64_FRAC_V3), FP64_SNAN_V(0, FP64_FRAC_V2) } }, \ 1014 { /* => */ { FP64_QNAN_V(0, 1), FP64_QNAN_V(1, FP64_FRAC_V2), FP64_SNAN_V(1, FP64_FRAC_V3), FP64_SNAN_V(0, FP64_FRAC_V2) } }, \ 1015 /*mxcsr:in */ 0, \ 1016 /*128:out */ X86_MXCSR_IE, \ 1017 /*256:out */ X86_MXCSR_IE, \ 1018 /*xcpt? */ true, true }, \ 1019 { { /*src2 */ { FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V0), FP64_QNAN_V(0, FP64_FRAC_V1) } }, \ 1020 { /*src1 */ { FP64_SNAN_V(0, FP64_FRAC_NORM_MIN), FP64_SNAN_V(0, FP64_FRAC_NORM_MIN), FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_SNAN_V(0, FP64_FRAC_V2) } }, \ 1021 { /* => */ { FP64_QNAN_V(0, 1), FP64_SNAN_V(0, FP64_FRAC_NORM_MIN), FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_SNAN_V(0, FP64_FRAC_V2) } }, \ 1022 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, \ 1023 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN | X86_MXCSR_IE, \ 1024 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN | X86_MXCSR_IE, \ 1025 /*xcpt? */ true, true }, \ 1026 { { /*src2 */ { FP64_QNAN_V(0, FP64_FRAC_V1), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V0), FP64_QNAN_V(0, FP64_FRAC_V1) } }, \ 1027 { /*src1 */ { FP64_SNAN_V(0, FP64_FRAC_V2), FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V2) } }, \ 1028 { /* => */ { FP64_SNAN_V(0, FP64_FRAC_V2), FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V2) } }, \ 1029 /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, \ 1030 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, \ 1031 /*256:out */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, \ 1032 /*xcpt? */ false, false }, \ 1033 /* SNan, QNan (Unmasked). */ \ 1034 { { /*src2 */ { FP64_SNAN(0), FP64_SNAN_V(0, FP64_FRAC_NORM_MIN), FP64_SNAN_V(0, FP64_FRAC_V1), FP64_SNAN_V(0, FP64_FRAC_V1) } }, \ 1035 { /*src1 */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V3), FP64_QNAN_V(0, FP64_FRAC_V2) } }, \ 1036 { /* => */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V3), FP64_QNAN_V(0, FP64_FRAC_V2) } }, \ 1037 /*mxcsr:in */ X86_MXCSR_DAZ, \ 1038 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_IE, \ 1039 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_IE, \ 1040 /*xcpt? */ true, true }, \ 1041 { { /*src2 */ { FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_SNAN_V(0, FP64_FRAC_V1), FP64_SNAN_V(1, FP64_FRAC_V1) } }, \ 1042 { /*src1 */ { FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(1, FP64_FRAC_V2), FP64_QNAN_V(1, FP64_FRAC_V0) } }, \ 1043 { /* => */ { FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(1, FP64_FRAC_V2), FP64_QNAN_V(1, FP64_FRAC_V0) } }, \ 1044 /*mxcsr:in */ X86_MXCSR_RC_UP, \ 1045 /*128:out */ X86_MXCSR_RC_UP, \ 1046 /*256:out */ X86_MXCSR_RC_UP, \ 1047 /*xcpt? */ false, false }, \ 1048 { { /*src2 */ { FP64_SNAN_V(0, FP64_FRAC_V0), FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_SNAN_V(0, FP64_FRAC_V1), FP64_SNAN_V(1, FP64_FRAC_V1) } }, \ 1049 { /*src1 */ { FP64_QNAN_V(0, FP64_FRAC_V3), FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(1, FP64_FRAC_V2), FP64_QNAN_V(1, FP64_FRAC_V3) } }, \ 1050 { /* => */ { FP64_QNAN_V(0, FP64_FRAC_V3), FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(1, FP64_FRAC_V2), FP64_QNAN_V(1, FP64_FRAC_V3) } }, \ 1051 /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, \ 1052 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, \ 1053 /*256:out */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, \ 1054 /*xcpt? */ false, false }, \ 1055 /* SNan, SNan (Unmasked). */ \ 1056 /*23*/{ { /*src2 */ { FP64_SNAN(0), FP64_SNAN_V(0, FP64_FRAC_NORM_MIN), FP64_SNAN_V(0, FP64_FRAC_V1), FP64_SNAN_V(0, FP64_FRAC_V2) } }, \ 1057 { /*src1 */ { FP64_SNAN(0), FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_SNAN_V(0, FP64_FRAC_V2), FP64_SNAN_V(1, FP64_FRAC_V0) } }, \ 1058 { /* => */ { FP64_QNAN_V(0, 1), FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_SNAN_V(0, FP64_FRAC_V2), FP64_SNAN_V(1, FP64_FRAC_V0) } }, \ 1059 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ, \ 1060 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_IE, \ 1061 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_IE, \ 1062 /*xcpt? */ true, true }, \ 1063 { { /*src2 */ { FP64_SNAN_V(0, FP64_FRAC_NORM_MIN), FP64_SNAN_V(0, FP64_FRAC_V2), FP64_SNAN_V(0, FP64_FRAC_V1), FP64_SNAN_V(1, FP32_FRAC_V2) } }, \ 1064 { /*src1 */ { FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_SNAN_V(0, FP64_FRAC_V0), FP64_SNAN_V(1, FP64_FRAC_V2), FP64_SNAN_V(1, FP32_FRAC_V3) } }, \ 1065 { /* => */ { FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_SNAN_V(0, FP64_FRAC_V0), FP64_SNAN_V(1, FP64_FRAC_V2), FP64_SNAN_V(1, FP32_FRAC_V3) } }, \ 1066 /*mxcsr:in */ X86_MXCSR_RC_ZERO, \ 1067 /*128:out */ X86_MXCSR_RC_ZERO | X86_MXCSR_IE, \ 1068 /*256:out */ X86_MXCSR_RC_ZERO | X86_MXCSR_IE, \ 1069 /*xcpt? */ true, true }, \ 1070 { { /*src2 */ { FP64_SNAN_V(0, FP64_FRAC_V1), FP64_SNAN_V(0, FP64_FRAC_V2), FP64_SNAN_V(1, FP64_FRAC_V0), FP64_SNAN_V(0, FP64_FRAC_V2) } }, \ 1071 { /*src1 */ { FP64_SNAN_V(0, FP64_FRAC_V2), FP64_SNAN_V(1, FP64_FRAC_V3), FP64_SNAN_V(1, FP64_FRAC_V3), FP64_SNAN_V(0, FP64_FRAC_V3) } }, \ 1072 { /* => */ { FP64_QNAN_V(0, FP64_FRAC_V2), FP64_SNAN_V(1, FP64_FRAC_V3), FP64_SNAN_V(1, FP64_FRAC_V3), FP64_SNAN_V(0, FP64_FRAC_V3) } }, \ 1073 /*mxcsr:in */ 0, \ 1074 /*128:out */ 0, \ 1075 /*256:out */ 0, \ 1076 /*xcpt? */ false, false }, \ 1077 /* QNan, Norm FP (Unmasked). */ \ 1078 { { /*src2 */ { FP64_QNAN(0), FP64_QNAN_V(1, FP64_FRAC_NORM_MAX), FP64_NORM_V0(1), FP64_QNAN_V(0, FP64_FRAC_V1) } }, \ 1079 { /*src1 */ { FP64_1(0), FP64_INF(1), FP64_QNAN_V(1, FP64_FRAC_V0), FP64_NORM_V2(1) } }, \ 1080 { /* => */ { FP64_QNAN(0), FP64_INF(1), FP64_QNAN_V(1, FP64_FRAC_V0), FP64_NORM_V2(1) } }, \ 1081 /*mxcsr:in */ X86_MXCSR_FZ, \ 1082 /*128:out */ X86_MXCSR_FZ, \ 1083 /*256:out */ X86_MXCSR_FZ, \ 1084 /*xcpt? */ false, false }, \ 1085 /* SNan, Norm FP (Unmasked). */ \ 1086 /*27*/{ { /*src2 */ { FP64_SNAN(1), FP64_SNAN_V(1, FP64_FRAC_NORM_MAX), FP64_NORM_V0(1), FP64_SNAN_V(0, FP64_FRAC_V1) } }, \ 1087 { /*src1 */ { FP64_1(0), FP64_INF(0), FP64_SNAN_V(1, FP64_FRAC_V0), FP64_NORM_V2(1) } }, \ 1088 { /* => */ { FP64_QNAN_V(1, 1), FP64_INF(0), FP64_SNAN_V(1, FP64_FRAC_V0), FP64_NORM_V2(1) } }, \ 1089 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, \ 1090 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE, \ 1091 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE, \ 1092 /*xcpt? */ true, true }, \ 1093 1094 /** Horizontally packed single-precision floating-point invalid values. */ 1095 #define BS3CPUINSTR4_H_PS_INVALIDS \ 1096 /*0 */{ { /*src2 */ { FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_V0), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V5) } }, \ 1097 { /*src1 */ { FP32_QNAN(0), FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4) } }, \ 1098 { /* => */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V0), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3) } }, \ 1099 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, \ 1100 /*128:out */ X86_MXCSR_XCPT_MASK, \ 1101 /*256:out */ X86_MXCSR_XCPT_MASK, \ 1102 /*xcpt? */ false, false }, \ 1103 { { /*src2 */ { FP32_QNAN(0), FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V5) } }, \ 1104 { /*src1 */ { FP32_QNAN(0), FP32_SNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V4) } }, \ 1105 { /* => */ { FP32_QNAN(0), FP32_QNAN(0), FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V4) } }, \ 1106 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, \ 1107 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, \ 1108 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, \ 1109 /*xcpt? */ false, false }, \ 1110 { { /*src2 */ { FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V6) } }, \ 1111 { /*src1 */ { FP32_SNAN(0), FP32_QNAN(0), FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1) } }, \ 1112 { /* => */ { FP32_QNAN_V(0, 1), FP32_QNAN_V(0, 1), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V5) } }, \ 1113 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, \ 1114 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, \ 1115 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, \ 1116 /*xcpt? */ false, false }, \ 1117 { { /*src2 */ { FP32_SNAN(0), FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_V7), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V1) } }, \ 1118 { /*src1 */ { FP32_SNAN(0), FP32_SNAN(0), FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2) } }, \ 1119 { /* => */ { FP32_QNAN_V(0, 1), FP32_QNAN_V(0, 1), FP32_QNAN_V(0, 1), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V7), FP32_QNAN_V(0, FP32_FRAC_V6) } }, \ 1120 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, \ 1121 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, \ 1122 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, \ 1123 /*xcpt? */ false, false }, \ 1124 { { /*src2 */ { FP32_QNAN(0), FP32_NORM_V1(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_NORM_V3(1), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_NORM_V5(1) } }, \ 1125 { /*src1 */ { FP32_QNAN(0), FP32_1(1), FP32_QNAN_V(1, FP32_FRAC_NORM_MAX), FP32_NORM_V2(1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_NORM_V4(0), FP32_QNAN_V(1, FP32_FRAC_V4), FP32_NORM_V6(1) } }, \ 1126 { /* => */ { FP32_QNAN(0), FP32_QNAN_V(1, FP32_FRAC_NORM_MAX), FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(1, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V5) } }, \ 1127 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, \ 1128 /*128:out */ X86_MXCSR_XCPT_MASK, \ 1129 /*256:out */ X86_MXCSR_XCPT_MASK, \ 1130 /*xcpt? */ false, false }, \ 1131 { { /*src2 */ { FP32_SNAN_V(1, FP32_FRAC_NORM_MAX), FP32_1(0), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_NORM_V3(0), FP32_SNAN_V(0, FP32_FRAC_V0), FP32_NORM_V3(1), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_NORM_V7(1) } }, \ 1132 { /*src1 */ { FP32_SNAN(0), FP32_1(1), FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_NORM_V2(1), FP32_SNAN_V(1, FP32_FRAC_V2), FP32_NORM_V4(0), FP32_SNAN_V(1, FP32_FRAC_V4), FP32_NORM_V6(1) } }, \ 1133 { /* => */ { FP32_QNAN_V(0, 1), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(1, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(1, FP32_FRAC_V2), FP32_QNAN_V(1, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V0), FP32_QNAN_V(0, FP32_FRAC_V6) } }, \ 1134 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, \ 1135 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, \ 1136 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, \ 1137 /*xcpt? */ false, false }, \ 1138 { { /*src2 */ { FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_V0), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V5) } }, \ 1139 { /*src1 */ { FP32_QNAN(0), FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4) } }, \ 1140 { /* => */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V0), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3) } }, \ 1141 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, \ 1142 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, \ 1143 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, \ 1144 /*xcpt? */ false, false }, \ 1145 { { /*src2 */ { FP32_QNAN(0), FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V5) } }, \ 1146 { /*src1 */ { FP32_QNAN(0), FP32_SNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V4) } }, \ 1147 { /* => */ { FP32_QNAN(0), FP32_QNAN(0), FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V4) } }, \ 1148 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_RC_UP, \ 1149 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_UP | X86_MXCSR_IE, \ 1150 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_UP | X86_MXCSR_IE, \ 1151 /*xcpt? */ true, true }, \ 1152 { { /*src2 */ { FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V6) } }, \ 1153 { /*src1 */ { FP32_SNAN(0), FP32_QNAN(0), FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1) } }, \ 1154 { /* => */ { FP32_QNAN_V(0, 1), FP32_QNAN_V(0, 1), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V5) } }, \ 1155 /*mxcsr:in */ 0, \ 1156 /*128:out */ X86_MXCSR_IE, \ 1157 /*256:out */ X86_MXCSR_IE, \ 1158 /*xcpt? */ true, true }, \ 1159 { { /*src2 */ { FP32_SNAN(0), FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_V7), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V1) } }, \ 1160 { /*src1 */ { FP32_SNAN(0), FP32_SNAN(0), FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2) } }, \ 1161 { /* => */ { FP32_QNAN_V(0, 1), FP32_QNAN_V(0, 1), FP32_QNAN_V(0, 1), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V7), FP32_QNAN_V(0, FP32_FRAC_V6) } }, \ 1162 /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_UP, \ 1163 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_UP | X86_MXCSR_IE, \ 1164 /*256:out */ X86_MXCSR_FZ | X86_MXCSR_RC_UP | X86_MXCSR_IE, \ 1165 /*xcpt? */ true, true }, \ 1166 { { /*src2 */ { FP32_QNAN(0), FP32_NORM_V1(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_NORM_V3(1), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_NORM_V5(1) } }, \ 1167 { /*src1 */ { FP32_QNAN(0), FP32_1(1), FP32_QNAN_V(1, FP32_FRAC_NORM_MAX), FP32_NORM_V2(1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_NORM_V4(0), FP32_QNAN_V(1, FP32_FRAC_V4), FP32_NORM_V6(1) } }, \ 1168 { /* => */ { FP32_QNAN(0), FP32_QNAN_V(1, FP32_FRAC_NORM_MAX), FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(1, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V5) } }, \ 1169 /*mxcsr:in */ 0, \ 1170 /*128:out */ 0, \ 1171 /*256:out */ 0, \ 1172 /*xcpt? */ false, false }, \ 1173 { { /*src2 */ { FP32_SNAN_V(1, FP32_FRAC_NORM_MAX), FP32_1(0), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_NORM_V3(0), FP32_SNAN_V(0, FP32_FRAC_V0), FP32_NORM_V3(1), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_NORM_V7(1) } }, \ 1174 { /*src1 */ { FP32_SNAN(0), FP32_1(1), FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_NORM_V2(1), FP32_SNAN_V(1, FP32_FRAC_V2), FP32_NORM_V4(0), FP32_SNAN_V(1, FP32_FRAC_V4), FP32_NORM_V6(1) } }, \ 1175 { /* => */ { FP32_QNAN_V(0, 1), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(1, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(1, FP32_FRAC_V2), FP32_QNAN_V(1, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V0), FP32_QNAN_V(0, FP32_FRAC_V6) } }, \ 1176 /*mxcsr:in */ X86_MXCSR_RC_UP, \ 1177 /*128:out */ X86_MXCSR_RC_UP | X86_MXCSR_IE, \ 1178 /*256:out */ X86_MXCSR_RC_UP | X86_MXCSR_IE, \ 1179 /*xcpt? */ true, true }, \ 1180 1181 /** Horizontally packed double-precision floating-point invalid values. */ 1182 #define BS3CPUINSTR4_H_PD_INVALIDS \ 1183 /*0 */{ { /*src2 */ { FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(0, FP64_FRAC_V0), FP64_QNAN_V(0, FP64_FRAC_V1) } }, \ 1184 { /*src1 */ { FP64_QNAN(0), FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX) } }, \ 1185 { /* => */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(0, FP64_FRAC_V0) } }, \ 1186 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, \ 1187 /*128:out */ X86_MXCSR_XCPT_MASK, \ 1188 /*256:out */ X86_MXCSR_XCPT_MASK, \ 1189 /*xcpt? */ false, false }, \ 1190 { { /*src2 */ { FP64_QNAN(0), FP64_SNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V1) } }, \ 1191 { /*src1 */ { FP64_QNAN(0), FP64_SNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_SNAN_V(0, FP64_FRAC_V2) } }, \ 1192 { /* => */ { FP64_QNAN(0), FP64_QNAN(0), FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX) } }, \ 1193 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, \ 1194 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, \ 1195 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, \ 1196 /*xcpt? */ false, false }, \ 1197 { { /*src2 */ { FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V2), FP64_SNAN_V(0, FP64_FRAC_V1), FP64_QNAN_V(0, FP64_FRAC_V2) } }, \ 1198 { /*src1 */ { FP64_SNAN(0), FP64_QNAN(0), FP64_SNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(0, FP64_FRAC_V3) } }, \ 1199 { /* => */ { FP64_QNAN_V(0, 1), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, 1), FP64_QNAN_V(0, FP64_FRAC_V1) } }, \ 1200 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, \ 1201 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, \ 1202 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, \ 1203 /*xcpt? */ false, false }, \ 1204 { { /*src2 */ { FP64_SNAN(0), FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_SNAN_V(0, FP64_FRAC_NORM_MIN) } }, \ 1205 { /*src1 */ { FP64_SNAN(0), FP64_SNAN(0), FP64_SNAN_V(0, FP64_FRAC_NORM_MIN), FP64_SNAN_V(0, FP64_FRAC_NORM_MAX) } }, \ 1206 { /* => */ { FP64_QNAN_V(0, 1), FP64_QNAN_V(0, 1), FP64_QNAN_V(0, 1), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX) } }, \ 1207 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, \ 1208 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, \ 1209 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, \ 1210 /*xcpt? */ false, false }, \ 1211 { { /*src2 */ { FP64_QNAN(0), FP64_NORM_V1(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V1) } }, \ 1212 { /*src1 */ { FP64_QNAN(0), FP64_1(1), FP64_QNAN_V(1, FP64_FRAC_NORM_MAX), FP64_NORM_V2(1) } }, \ 1213 { /* => */ { FP64_QNAN(0), FP64_QNAN(0), FP64_QNAN_V(1, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX) } }, \ 1214 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, \ 1215 /*128:out */ X86_MXCSR_XCPT_MASK, \ 1216 /*256:out */ X86_MXCSR_XCPT_MASK, \ 1217 /*xcpt? */ false, false }, \ 1218 { { /*src2 */ { FP64_SNAN_V(1, FP64_FRAC_NORM_MAX), FP64_1(0), FP64_SNAN_V(0, FP64_FRAC_V1), FP64_NORM_V3(0) } }, \ 1219 { /*src1 */ { FP64_SNAN(0), FP64_1(1), FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_NORM_V2(1) } }, \ 1220 { /* => */ { FP64_QNAN_V(0, 1), FP64_QNAN_V(1, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V1) } }, \ 1221 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, \ 1222 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, \ 1223 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, \ 1224 /*xcpt? */ false, false }, \ 1225 { { /*src2 */ { FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(0, FP64_FRAC_V0), FP64_QNAN_V(0, FP64_FRAC_V1) } }, \ 1226 { /*src1 */ { FP64_QNAN(0), FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX) } }, \ 1227 { /* => */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(0, FP64_FRAC_V0) } }, \ 1228 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, \ 1229 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, \ 1230 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, \ 1231 /*xcpt? */ false, false }, \ 1232 { { /*src2 */ { FP64_QNAN(0), FP64_SNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V1) } }, \ 1233 { /*src1 */ { FP64_QNAN(0), FP64_SNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_SNAN_V(0, FP64_FRAC_V2) } }, \ 1234 { /* => */ { FP64_QNAN(0), FP64_QNAN(0), FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX) } }, \ 1235 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_RC_UP, \ 1236 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_UP | X86_MXCSR_IE, \ 1237 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_UP | X86_MXCSR_IE, \ 1238 /*xcpt? */ true, true }, \ 1239 { { /*src2 */ { FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V2), FP64_SNAN_V(0, FP64_FRAC_V1), FP64_QNAN_V(0, FP64_FRAC_V2) } }, \ 1240 { /*src1 */ { FP64_SNAN(0), FP64_QNAN(0), FP64_SNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(0, FP64_FRAC_V3) } }, \ 1241 { /* => */ { FP64_QNAN_V(0, 1), FP64_QNAN_V(0, 1), FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(0, FP64_FRAC_V1) } }, \ 1242 /*mxcsr:in */ 0, \ 1243 /*128:out */ X86_MXCSR_IE, \ 1244 /*256:out */ X86_MXCSR_IE, \ 1245 /*xcpt? */ true, true }, \ 1246 { { /*src2 */ { FP64_SNAN(0), FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_SNAN_V(0, FP64_FRAC_NORM_MIN) } }, \ 1247 { /*src1 */ { FP64_SNAN(0), FP64_SNAN(0), FP64_SNAN_V(0, FP64_FRAC_NORM_MIN), FP64_SNAN_V(0, FP64_FRAC_NORM_MAX) } }, \ 1248 { /* => */ { FP64_QNAN_V(0, 1), FP64_QNAN_V(0, 1), FP64_QNAN_V(0, 1), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX) } }, \ 1249 /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_UP, \ 1250 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_UP | X86_MXCSR_IE, \ 1251 /*256:out */ X86_MXCSR_FZ | X86_MXCSR_RC_UP | X86_MXCSR_IE, \ 1252 /*xcpt? */ true, true }, \ 1253 { { /*src2 */ { FP64_QNAN(0), FP64_NORM_V1(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V1) } }, \ 1254 { /*src1 */ { FP64_QNAN(0), FP64_1(1), FP64_QNAN_V(1, FP64_FRAC_NORM_MAX), FP64_NORM_V2(1) } }, \ 1255 { /* => */ { FP64_QNAN(0), FP64_QNAN(0), FP64_QNAN_V(1, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX) } }, \ 1256 /*mxcsr:in */ 0, \ 1257 /*128:out */ 0, \ 1258 /*256:out */ 0, \ 1259 /*xcpt? */ false, false }, \ 1260 /*11*/{ { /*src2 */ { FP64_SNAN_V(1, FP64_FRAC_NORM_MAX), FP64_1(0), FP64_SNAN_V(0, FP64_FRAC_V1), FP64_NORM_V3(0) } }, \ 1261 { /*src1 */ { FP64_SNAN(0), FP64_1(1), FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_NORM_V2(1) } }, \ 1262 { /* => */ { FP64_QNAN_V(0, 1), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(1, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V1) } }, \ 1263 /*mxcsr:in */ X86_MXCSR_RC_UP, \ 1264 /*128:out */ X86_MXCSR_RC_UP|X86_MXCSR_IE, \ 1265 /*256:out */ X86_MXCSR_RC_UP|X86_MXCSR_IE, \ 1266 /*xcpt? */ true, true }, \ 1267 496 1268 497 1269 /** … … 1811 2583 * Invalids. 1812 2584 */ 1813 /*32*/{ { /*src2 */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V0), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V5) } }, 1814 { /*src1 */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4) } }, 1815 { /* => */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4) } }, 1816 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 1817 /*128:out */ X86_MXCSR_XCPT_MASK, 1818 /*256:out */ X86_MXCSR_XCPT_MASK, 1819 /*xcpt? */ false, false }, 1820 { { /*src2 */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V0), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V5) } }, 1821 { /*src1 */ { FP32_SNAN(0), FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V4) } }, 1822 { /* => */ { FP32_QNAN_V(0, 1), FP32_QNAN_V(0, 1), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4) } }, 1823 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 1824 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, 1825 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, 1826 /*xcpt? */ false, false }, 1827 { { /*src2 */ { FP32_SNAN(0), FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V6) } }, 1828 { /*src1 */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1) } }, 1829 { /* => */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1) } }, 1830 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ, 1831 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_IE, 1832 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_IE, 1833 /*xcpt? */ false, false }, 1834 { { /*src2 */ { FP32_SNAN(0), FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V7), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V1) } }, 1835 { /*src1 */ { FP32_SNAN(0), FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2) } }, 1836 { /* => */ { FP32_QNAN_V(0, 1), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2) } }, 1837 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 1838 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, 1839 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, 1840 /*xcpt? */ false, false }, 1841 { { /*src2 */ { FP32_QNAN(0), FP32_QNAN_V(1, FP32_FRAC_NORM_MAX), FP32_NORM_V0(1), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_NORM_V3(0), FP32_QNAN_V(1, FP32_FRAC_V3), FP32_NORM_V5(0), FP32_QNAN_V(1, FP32_FRAC_V5) } }, 1842 { /*src1 */ { FP32_1(0), FP32_1(1), FP32_QNAN_V(1, FP32_FRAC_V0), FP32_NORM_V2(1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_NORM_V4(0), FP32_QNAN_V(1, FP32_FRAC_V4), FP32_NORM_V6(1) } }, 1843 { /* => */ { FP32_QNAN(0), FP32_QNAN_V(1, FP32_FRAC_NORM_MAX), FP32_QNAN_V(1, FP32_FRAC_V0), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(1, FP32_FRAC_V3), FP32_QNAN_V(1, FP32_FRAC_V4), FP32_QNAN_V(1, FP32_FRAC_V5) } }, 1844 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_XCPT_FLAGS, 1845 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_XCPT_FLAGS, 1846 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_XCPT_FLAGS, 1847 /*xcpt? */ false, false }, 1848 { { /*src2 */ { FP32_SNAN(1), FP32_SNAN_V(1, FP32_FRAC_NORM_MAX), FP32_NORM_V0(1), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_NORM_V3(0), FP32_SNAN_V(1, FP32_FRAC_V3), FP32_NORM_V5(0), FP32_SNAN_V(1, FP32_FRAC_V5) } }, 1849 { /*src1 */ { FP32_1(0), FP32_1(0), FP32_SNAN_V(1, FP32_FRAC_V0), FP32_NORM_V2(1), FP32_SNAN_V(1, FP32_FRAC_V2), FP32_NORM_V4(0), FP32_SNAN_V(1, FP32_FRAC_V4), FP32_NORM_V6(1) } }, 1850 { /* => */ { FP32_QNAN_V(1, 1), FP32_QNAN_V(1, FP32_FRAC_NORM_MAX), FP32_QNAN_V(1, FP32_FRAC_V0), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(1, FP32_FRAC_V2), FP32_QNAN_V(1, FP32_FRAC_V3), FP32_QNAN_V(1, FP32_FRAC_V4), FP32_QNAN_V(1, FP32_FRAC_V5) } }, 1851 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 1852 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, 1853 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, 1854 /*xcpt? */ false, false }, 1855 { { /*src2 */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V0), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V5) } }, 1856 { /*src1 */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4) } }, 1857 { /* => */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4) } }, 1858 /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 1859 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 1860 /*256:out */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 1861 /*xcpt? */ false, false }, 1862 { { /*src2 */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V0), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V5) } }, 1863 { /*src1 */ { FP32_SNAN(0), FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V4) } }, 1864 { /* => */ { FP32_QNAN_V(0, 1), FP32_QNAN_V(0, 1), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4) } }, 1865 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, 1866 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE, 1867 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE, 1868 /*xcpt? */ true, true }, 1869 { { /*src2 */ { FP32_SNAN(0), FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V6) } }, 1870 { /*src1 */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1) } }, 1871 { /* => */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1) } }, 1872 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP, 1873 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP | X86_MXCSR_IE, 1874 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP | X86_MXCSR_IE, 1875 /*xcpt? */ true, true }, 1876 { { /*src2 */ { FP32_SNAN(0), FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V7), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V1) } }, 1877 { /*src1 */ { FP32_SNAN(0), FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2) } }, 1878 { /* => */ { FP32_QNAN_V(0, 1), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2) } }, 1879 /*mxcsr:in */ X86_MXCSR_RC_UP, 1880 /*128:out */ X86_MXCSR_RC_UP | X86_MXCSR_IE, 1881 /*256:out */ X86_MXCSR_RC_UP | X86_MXCSR_IE, 1882 /*xcpt? */ true, true }, 1883 { { /*src2 */ { FP32_QNAN(0), FP32_QNAN_V(1, FP32_FRAC_NORM_MAX), FP32_NORM_V0(1), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_NORM_V3(0), FP32_QNAN_V(1, FP32_FRAC_V3), FP32_NORM_V5(0), FP32_QNAN_V(1, FP32_FRAC_V5) } }, 1884 { /*src1 */ { FP32_1(0), FP32_1(1), FP32_QNAN_V(1, FP32_FRAC_V0), FP32_NORM_V2(1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_NORM_V4(0), FP32_QNAN_V(1, FP32_FRAC_V4), FP32_NORM_V6(1) } }, 1885 { /* => */ { FP32_QNAN(0), FP32_QNAN_V(1, FP32_FRAC_NORM_MAX), FP32_QNAN_V(1, FP32_FRAC_V0), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(1, FP32_FRAC_V3), FP32_QNAN_V(1, FP32_FRAC_V4), FP32_QNAN_V(1, FP32_FRAC_V5) } }, 1886 /*mxcsr:in */ 0, 1887 /*128:out */ 0, 1888 /*256:out */ 0, 1889 /*xcpt? */ false, false }, 1890 { { /*src2 */ { FP32_SNAN(1), FP32_SNAN_V(1, FP32_FRAC_NORM_MAX), FP32_NORM_V0(1), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_NORM_V3(0), FP32_SNAN_V(1, FP32_FRAC_V3), FP32_NORM_V5(0), FP32_SNAN_V(1, FP32_FRAC_V5) } }, 1891 { /*src1 */ { FP32_1(0), FP32_1(0), FP32_SNAN_V(1, FP32_FRAC_V0), FP32_NORM_V2(1), FP32_SNAN_V(1, FP32_FRAC_V2), FP32_NORM_V4(0), FP32_SNAN_V(1, FP32_FRAC_V4), FP32_NORM_V6(1) } }, 1892 { /* => */ { FP32_QNAN_V(1, 1), FP32_QNAN_V(1, FP32_FRAC_NORM_MAX), FP32_QNAN_V(1, FP32_FRAC_V0), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(1, FP32_FRAC_V2), FP32_QNAN_V(1, FP32_FRAC_V3), FP32_QNAN_V(1, FP32_FRAC_V4), FP32_QNAN_V(1, FP32_FRAC_V5) } }, 1893 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO, 1894 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE, 1895 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE, 1896 /*xcpt? */ true, true }, 1897 /** @todo Underflow, Precision; Rounding, FZ etc. */ 2585 /*34*/ BS3CPUINSTR4_PS_INVALIDS 2586 /** @todo Underflow, Precision; Rounding; FZ etc. */ 1898 2587 }; 1899 2588 … … 2159 2848 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP, 2160 2849 /*xcpt? */ false, false }, 2161 /** @todo More denormals ; Underflow, Precision; Rounding, FZ etc. */2850 /** @todo More denormals. */ 2162 2851 /* 2163 2852 * Invalids. 2164 2853 */ 2165 /*27*/{ { /*src2 */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V0), FP64_QNAN_V(0, FP64_FRAC_V1) } }, 2166 { /*src1 */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V2) } }, 2167 { /* => */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V2) } }, 2168 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 2169 /*128:out */ X86_MXCSR_XCPT_MASK, 2170 /*256:out */ X86_MXCSR_XCPT_MASK, 2171 /*xcpt? */ false, false }, 2172 { { /*src2 */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V0), FP64_QNAN_V(0, FP64_FRAC_V2) } }, 2173 { /*src1 */ { FP64_SNAN(0), FP64_SNAN_V(0, FP64_FRAC_NORM_MIN), FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_SNAN_V(0, FP64_FRAC_V1) } }, 2174 { /* => */ { FP64_QNAN_V(0, 1), FP64_QNAN_V(0, 1), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V1) } }, 2175 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 2176 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, 2177 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, 2178 /*xcpt? */ false, false }, 2179 { { /*src2 */ { FP64_SNAN(0), FP64_SNAN_V(0, FP64_FRAC_NORM_MIN), FP64_SNAN_V(0, FP64_FRAC_V0), FP64_SNAN_V(0, FP64_FRAC_V1) } }, 2180 { /*src1 */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V2), FP64_QNAN_V(0, FP64_FRAC_V3) } }, 2181 { /* => */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V2), FP64_QNAN_V(0, FP64_FRAC_V3) } }, 2182 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 2183 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, 2184 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, 2185 /*xcpt? */ false, false }, 2186 { { /*src2 */ { FP64_SNAN(0), FP64_SNAN_V(0, FP64_FRAC_NORM_MIN), FP64_SNAN_V(0, FP64_FRAC_V1), FP64_SNAN_V(0, FP64_FRAC_V2) } }, 2187 { /*src1 */ { FP64_SNAN(0), FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_SNAN_V(0, FP64_FRAC_V3), FP64_SNAN_V(0, FP64_FRAC_V0) } }, 2188 { /* => */ { FP64_QNAN_V(0, 1), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V3), FP64_QNAN_V(0, FP64_FRAC_V0) } }, 2189 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 2190 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, 2191 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, 2192 /*xcpt? */ false, false }, 2193 { { /*src2 */ { FP64_QNAN(0), FP64_QNAN_V(1, FP64_FRAC_NORM_MAX), FP64_NORM_V0(1), FP64_QNAN_V(0, FP64_FRAC_V1) } }, 2194 { /*src1 */ { FP64_1(0), FP64_1(1), FP64_QNAN_V(1, FP64_FRAC_V0), FP64_NORM_V2(1) } }, 2195 { /* => */ { FP64_QNAN(0), FP64_QNAN_V(1, FP64_FRAC_NORM_MAX), FP64_QNAN_V(1, FP64_FRAC_V0), FP64_QNAN_V(0, FP64_FRAC_V1) } }, 2196 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 2197 /*128:out */ X86_MXCSR_XCPT_MASK, 2198 /*256:out */ X86_MXCSR_XCPT_MASK, 2199 /*xcpt? */ false, false }, 2200 { { /*src2 */ { FP64_SNAN(1), FP64_SNAN_V(1, FP64_FRAC_NORM_MAX), FP64_NORM_V0(1), FP64_SNAN_V(0, FP64_FRAC_V1) } }, 2201 { /*src1 */ { FP64_1(0), FP64_1(0), FP64_SNAN_V(1, FP64_FRAC_V0), FP64_NORM_V2(1) } }, 2202 { /* => */ { FP64_QNAN_V(1, 1), FP64_QNAN_V(1, FP64_FRAC_NORM_MAX), FP64_QNAN_V(1, FP64_FRAC_V0), FP64_QNAN_V(0, FP64_FRAC_V1) } }, 2203 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 2204 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, 2205 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, 2206 /*xcpt? */ false, false }, 2207 { { /*src2 */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V0), FP64_QNAN_V(0, FP64_FRAC_V2) } }, 2208 { /*src1 */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V3) } }, 2209 { /* => */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V3) } }, 2210 /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 2211 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 2212 /*256:out */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 2213 /*xcpt? */ false, false }, 2214 { { /*src2 */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V0), FP64_QNAN_V(0, FP32_FRAC_V1) } }, 2215 { /*src1 */ { FP64_SNAN(0), FP64_SNAN_V(0, FP64_FRAC_NORM_MIN), FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_SNAN_V(0, FP32_FRAC_V2) } }, 2216 { /* => */ { FP64_QNAN_V(0, 1), FP64_QNAN_V(0, 1), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP32_FRAC_V2) } }, 2217 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, 2218 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE, 2219 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE, 2220 /*xcpt? */ true, true }, 2221 { { /*src2 */ { FP64_SNAN(0), FP64_SNAN_V(0, FP64_FRAC_NORM_MIN), FP64_SNAN_V(0, FP64_FRAC_V1), FP64_SNAN_V(0, FP64_FRAC_V1) } }, 2222 { /*src1 */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V3), FP64_QNAN_V(0, FP64_FRAC_V2) } }, 2223 { /* => */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V3), FP64_QNAN_V(0, FP64_FRAC_V2) } }, 2224 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, 2225 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE, 2226 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE, 2227 /*xcpt? */ true, true }, 2228 { { /*src2 */ { FP64_SNAN(0), FP64_SNAN_V(0, FP64_FRAC_NORM_MIN), FP64_SNAN_V(0, FP64_FRAC_V1), FP64_SNAN_V(0, FP64_FRAC_V2) } }, 2229 { /*src1 */ { FP64_SNAN(0), FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_SNAN_V(0, FP64_FRAC_V0), FP64_SNAN_V(0, FP64_FRAC_V3) } }, 2230 { /* => */ { FP64_QNAN_V(0, 1), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V0), FP64_QNAN_V(0, FP64_FRAC_V3) } }, 2231 /*mxcsr:in */ X86_MXCSR_RC_UP, 2232 /*128:out */ X86_MXCSR_RC_UP | X86_MXCSR_IE, 2233 /*256:out */ X86_MXCSR_RC_UP | X86_MXCSR_IE, 2234 /*xcpt? */ true, true }, 2235 { { /*src2 */ { FP64_QNAN(0), FP64_QNAN_V(1, FP64_FRAC_NORM_MAX), FP64_NORM_V0(1), FP64_QNAN_V(0, FP64_FRAC_V1) } }, 2236 { /*src1 */ { FP64_1(0), FP64_1(1), FP64_QNAN_V(1, FP64_FRAC_V3), FP64_NORM_V2(1) } }, 2237 { /* => */ { FP64_QNAN(0), FP64_QNAN_V(1, FP64_FRAC_NORM_MAX), FP64_QNAN_V(1, FP64_FRAC_V3), FP64_QNAN_V(0, FP64_FRAC_V1) } }, 2238 /*mxcsr:in */ X86_MXCSR_RC_DOWN, 2239 /*128:out */ X86_MXCSR_RC_DOWN, 2240 /*256:out */ X86_MXCSR_RC_DOWN, 2241 /*xcpt? */ false, false }, 2242 { { /*src2 */ { FP64_SNAN(1), FP64_SNAN_V(1, FP64_FRAC_NORM_MAX), FP64_NORM_V0(1), FP64_SNAN_V(0, FP64_FRAC_V2) } }, 2243 { /*src1 */ { FP64_1(0), FP64_1(0), FP64_SNAN_V(1, FP64_FRAC_V3), FP64_NORM_V2(1) } }, 2244 { /* => */ { FP64_QNAN_V(1, 1), FP64_QNAN_V(1, FP64_FRAC_NORM_MAX), FP64_QNAN_V(1, FP64_FRAC_V3), FP64_QNAN_V(0, FP64_FRAC_V2) } }, 2245 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO, 2246 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE, 2247 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE, 2248 /*xcpt? */ true, true }, 2854 /*27*/ BS3CPUINSTR4_PD_INVALIDS 2855 /** @todo Underflow, Precision; Rounding; FZ etc. */ 2249 2856 }; 2250 2857 … … 2534 3141 * Invalids. 2535 3142 */ 2536 /* QNan, QNan (Masked). */ 2537 /*30*/{ { /*src2 */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V0), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V5) } }, 2538 { /*src1 */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4) } }, 2539 { /* => */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4) } }, 2540 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 2541 /*128:out */ X86_MXCSR_XCPT_MASK, 2542 /*256:out */ X86_MXCSR_XCPT_MASK, 2543 /*xcpt? */ false, false }, 2544 { { /*src2 */ { FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4) } }, 2545 { /*src1 */ { FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V1) } }, 2546 { /* => */ { FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V1) } }, 2547 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 2548 /*128:out */ X86_MXCSR_XCPT_MASK, 2549 /*256:out */ X86_MXCSR_XCPT_MASK, 2550 /*xcpt? */ false, false }, 2551 { { /*src2 */ { FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4) } }, 2552 { /*src1 */ { FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V1) } }, 2553 { /* => */ { FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V1) } }, 2554 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 2555 /*128:out */ X86_MXCSR_XCPT_MASK, 2556 /*256:out */ X86_MXCSR_XCPT_MASK, 2557 /*xcpt? */ false, false }, 2558 /* QNan, SNan (Masked). */ 2559 { { /*src2 */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4) } }, 2560 { /*src1 */ { FP32_SNAN(0), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V1) } }, 2561 { /* => */ { FP32_QNAN_V(0, 1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V1) } }, 2562 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 2563 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, 2564 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, 2565 /*xcpt? */ false, false }, 2566 { { /*src2 */ { FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V0), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V5) } }, 2567 { /*src1 */ { FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V4) } }, 2568 { /* => */ { FP32_QNAN_V(0, 1), FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V4) } }, 2569 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 2570 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, 2571 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, 2572 /*xcpt? */ false, false }, 2573 { { /*src2 */ { FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V0), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V5) } }, 2574 { /*src1 */ { FP32_SNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4) } }, 2575 { /* => */ { FP32_SNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4) } }, 2576 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 2577 /*128:out */ X86_MXCSR_XCPT_MASK, 2578 /*256:out */ X86_MXCSR_XCPT_MASK, 2579 /*xcpt? */ false, false }, 2580 /* SNan, QNan (Masked). */ 2581 { { /*src2 */ { FP32_SNAN(0), FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V6) } }, 2582 { /*src1 */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1) } }, 2583 { /* => */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1) } }, 2584 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 2585 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, 2586 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, 2587 /*xcpt? */ false, false }, 2588 { { /*src2 */ { FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V6) } }, 2589 { /*src1 */ { FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1) } }, 2590 { /* => */ { FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1) } }, 2591 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 2592 /*128:out */ X86_MXCSR_XCPT_MASK, 2593 /*256:out */ X86_MXCSR_XCPT_MASK, 2594 /*xcpt? */ false, false }, 2595 { { /*src2 */ { FP32_SNAN_V(0, FP32_FRAC_V0), FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V6) } }, 2596 { /*src1 */ { FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1) } }, 2597 { /* => */ { FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1) } }, 2598 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 2599 /*128:out */ X86_MXCSR_XCPT_MASK, 2600 /*256:out */ X86_MXCSR_XCPT_MASK, 2601 /*xcpt? */ false, false }, 2602 /* SNan, SNan (Masked). */ 2603 { { /*src2 */ { FP32_SNAN(0), FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V7), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V1) } }, 2604 { /*src1 */ { FP32_SNAN(0), FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2) } }, 2605 { /* => */ { FP32_QNAN_V(0, 1), FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2) } }, 2606 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 2607 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, 2608 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, 2609 /*xcpt? */ false, false }, 2610 { { /*src2 */ { FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V7), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V1) } }, 2611 { /*src1 */ { FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V0), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2) } }, 2612 { /* => */ { FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V0), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2) } }, 2613 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 2614 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, 2615 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, 2616 /*xcpt? */ false, false }, 2617 { { /*src2 */ { FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V7), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V1) } }, 2618 { /*src1 */ { FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V0) } }, 2619 { /* => */ { FP32_QNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V0) } }, 2620 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 2621 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, 2622 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, 2623 /*xcpt? */ false, false }, 2624 /* QNan, Norm FP (Masked). */ 2625 { { /*src2 */ { FP32_QNAN(0), FP32_QNAN_V(1, FP32_FRAC_NORM_MAX), FP32_NORM_V0(1), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_NORM_V3(0), FP32_QNAN_V(1, FP32_FRAC_V3), FP32_NORM_V5(0), FP32_QNAN_V(1, FP32_FRAC_V5) } }, 2626 { /*src1 */ { FP32_1(0), FP32_1(1), FP32_QNAN_V(1, FP32_FRAC_V0), FP32_NORM_V2(1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_NORM_V4(0), FP32_QNAN_V(1, FP32_FRAC_V4), FP32_NORM_V6(1) } }, 2627 { /* => */ { FP32_QNAN(0), FP32_1(1), FP32_QNAN_V(1, FP32_FRAC_V0), FP32_NORM_V2(1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_NORM_V4(0), FP32_QNAN_V(1, FP32_FRAC_V4), FP32_NORM_V6(1) } }, 2628 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 2629 /*128:out */ X86_MXCSR_XCPT_MASK, 2630 /*256:out */ X86_MXCSR_XCPT_MASK, 2631 /*xcpt? */ false, false }, 2632 /* SNan, Norm FP (Masked). */ 2633 { { /*src2 */ { FP32_SNAN(1), FP32_SNAN_V(1, FP32_FRAC_NORM_MAX), FP32_NORM_V0(1), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_NORM_V3(0), FP32_SNAN_V(1, FP32_FRAC_V3), FP32_NORM_V5(0), FP32_SNAN_V(1, FP32_FRAC_V5) } }, 2634 { /*src1 */ { FP32_1(0), FP32_1(0), FP32_SNAN_V(1, FP32_FRAC_V0), FP32_NORM_V2(1), FP32_SNAN_V(1, FP32_FRAC_V2), FP32_NORM_V4(0), FP32_SNAN_V(1, FP32_FRAC_V4), FP32_NORM_V6(1) } }, 2635 { /* => */ { FP32_QNAN_V(1, 1), FP32_1(0), FP32_SNAN_V(1, FP32_FRAC_V0), FP32_NORM_V2(1), FP32_SNAN_V(1, FP32_FRAC_V2), FP32_NORM_V4(0), FP32_SNAN_V(1, FP32_FRAC_V4), FP32_NORM_V6(1) } }, 2636 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 2637 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, 2638 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, 2639 /*xcpt? */ false, false }, 2640 /* QNan, QNan (Unmasked). */ 2641 /*44*/{ { /*src2 */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V0), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V5) } }, 2642 { /*src1 */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4) } }, 2643 { /* => */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4) } }, 2644 /*mxcsr:in */ 0, 2645 /*128:out */ 0, 2646 /*256:out */ 0, 2647 /*xcpt? */ false, false }, 2648 { { /*src2 */ { FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4) } }, 2649 { /*src1 */ { FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V1) } }, 2650 { /* => */ { FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V1) } }, 2651 /*mxcsr:in */ 0, 2652 /*128:out */ 0, 2653 /*256:out */ 0, 2654 /*xcpt? */ false, false }, 2655 { { /*src2 */ { FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4) } }, 2656 { /*src1 */ { FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V1) } }, 2657 { /* => */ { FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V1) } }, 2658 /*mxcsr:in */ 0, 2659 /*128:out */ 0, 2660 /*256:out */ 0, 2661 /*xcpt? */ false, false }, 2662 2663 /* QNan, SNan (Unmasked). */ 2664 { { /*src2 */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4) } }, 2665 { /*src1 */ { FP32_SNAN(0), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V1) } }, 2666 { /* => */ { FP32_QNAN_V(0, 1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V1) } }, 2667 /*mxcsr:in */ 0, 2668 /*128:out */ X86_MXCSR_IE, 2669 /*256:out */ X86_MXCSR_IE, 2670 /*xcpt? */ true, true }, 2671 { { /*src2 */ { FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V0), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V5) } }, 2672 { /*src1 */ { FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V4) } }, 2673 { /* => */ { FP32_QNAN_V(0, 1), FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V4) } }, 2674 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 2675 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN | X86_MXCSR_IE, 2676 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN | X86_MXCSR_IE, 2677 /*xcpt? */ true, true }, 2678 { { /*src2 */ { FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V0), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V5) } }, 2679 { /*src1 */ { FP32_SNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4) } }, 2680 { /* => */ { FP32_SNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4) } }, 2681 /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, 2682 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, 2683 /*256:out */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, 2684 /*xcpt? */ false, false }, 2685 /* SNan, QNan (Unmasked). */ 2686 { { /*src2 */ { FP32_SNAN(0), FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V6) } }, 2687 { /*src1 */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1) } }, 2688 { /* => */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1) } }, 2689 /*mxcsr:in */ X86_MXCSR_DAZ, 2690 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_IE, 2691 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_IE, 2692 /*xcpt? */ true, true }, 2693 { { /*src2 */ { FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V6) } }, 2694 { /*src1 */ { FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1) } }, 2695 { /* => */ { FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1) } }, 2696 /*mxcsr:in */ X86_MXCSR_RC_UP, 2697 /*128:out */ X86_MXCSR_RC_UP, 2698 /*256:out */ X86_MXCSR_RC_UP, 2699 /*xcpt? */ false, false }, 2700 { { /*src2 */ { FP32_SNAN_V(0, FP32_FRAC_V0), FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V6) } }, 2701 { /*src1 */ { FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1) } }, 2702 { /* => */ { FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1) } }, 2703 /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 2704 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 2705 /*256:out */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 2706 /*xcpt? */ false, false }, 2707 /* SNan, SNan (Unmasked). */ 2708 /*54*/{ { /*src2 */ { FP32_SNAN(0), FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V7), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V1) } }, 2709 { /*src1 */ { FP32_SNAN(0), FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2) } }, 2710 { /* => */ { FP32_QNAN_V(0, 1), FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2) } }, 2711 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ, 2712 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_IE, 2713 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_IE, 2714 /*xcpt? */ true, true }, 2715 { { /*src2 */ { FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V7), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V1) } }, 2716 { /*src1 */ { FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V0), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2) } }, 2717 { /* => */ { FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V0), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2) } }, 2718 /*mxcsr:in */ X86_MXCSR_RC_ZERO, 2719 /*128:out */ X86_MXCSR_RC_ZERO | X86_MXCSR_IE, 2720 /*256:out */ X86_MXCSR_RC_ZERO | X86_MXCSR_IE, 2721 /*xcpt? */ true, true }, 2722 { { /*src2 */ { FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V7), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V1) } }, 2723 { /*src1 */ { FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V0) } }, 2724 { /* => */ { FP32_QNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V0) } }, 2725 /*mxcsr:in */ 0, 2726 /*128:out */ X86_MXCSR_IE, 2727 /*256:out */ X86_MXCSR_IE, 2728 /*xcpt? */ true, true }, 2729 /* QNan, Norm FP (Unmasked). */ 2730 { { /*src2 */ { FP32_QNAN(0), FP32_QNAN_V(1, FP32_FRAC_NORM_MAX), FP32_NORM_V0(1), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_NORM_V3(0), FP32_QNAN_V(1, FP32_FRAC_V3), FP32_NORM_V5(0), FP32_QNAN_V(1, FP32_FRAC_V5) } }, 2731 { /*src1 */ { FP32_1(0), FP32_1(1), FP32_QNAN_V(1, FP32_FRAC_V0), FP32_NORM_V2(1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_NORM_V4(0), FP32_QNAN_V(1, FP32_FRAC_V4), FP32_NORM_V6(1) } }, 2732 { /* => */ { FP32_QNAN(0), FP32_1(1), FP32_QNAN_V(1, FP32_FRAC_V0), FP32_NORM_V2(1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_NORM_V4(0), FP32_QNAN_V(1, FP32_FRAC_V4), FP32_NORM_V6(1) } }, 2733 /*mxcsr:in */ X86_MXCSR_FZ, 2734 /*128:out */ X86_MXCSR_FZ, 2735 /*256:out */ X86_MXCSR_FZ, 2736 /*xcpt? */ false, false }, 2737 /* SNan, Norm FP (Unmasked). */ 2738 /*58*/{ { /*src2 */ { FP32_SNAN(1), FP32_SNAN_V(1, FP32_FRAC_NORM_MAX), FP32_NORM_V0(1), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_NORM_V3(0), FP32_SNAN_V(1, FP32_FRAC_V3), FP32_NORM_V5(0), FP32_SNAN_V(1, FP32_FRAC_V5) } }, 2739 { /*src1 */ { FP32_1(0), FP32_1(0), FP32_SNAN_V(1, FP32_FRAC_V0), FP32_NORM_V2(1), FP32_SNAN_V(1, FP32_FRAC_V2), FP32_NORM_V4(0), FP32_SNAN_V(1, FP32_FRAC_V4), FP32_NORM_V6(1) } }, 2740 { /* => */ { FP32_QNAN_V(1, 1), FP32_1(0), FP32_SNAN_V(1, FP32_FRAC_V0), FP32_NORM_V2(1), FP32_SNAN_V(1, FP32_FRAC_V2), FP32_NORM_V4(0), FP32_SNAN_V(1, FP32_FRAC_V4), FP32_NORM_V6(1) } }, 2741 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, 2742 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE, 2743 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE, 2744 /*xcpt? */ true, true }, 2745 /** @todo Underflow, Precision; Rounding, FZ etc. */ 3143 /*30*/ BS3CPUINSTR4_SS_INVALIDS 3144 /** @todo Underflow; Precision; Rounding; FZ etc. */ 2746 3145 }; 2747 3146 … … 3034 3433 * Invalids. 3035 3434 */ 3036 /* QNan, QNan (Masked). */ 3037 /*32*/{ { /*src2 */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V0), FP64_QNAN_V(0, FP64_FRAC_V1) } }, 3038 { /*src1 */ { FP64_QNAN(0), FP64_QNAN_V(1, FP64_FRAC_NORM_MIN), FP64_QNAN_V(1, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V2) } }, 3039 { /* => */ { FP64_QNAN(0), FP64_QNAN_V(1, FP64_FRAC_NORM_MIN), FP64_QNAN_V(1, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V2) } }, 3040 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 3041 /*128:out */ X86_MXCSR_XCPT_MASK, 3042 /*256:out */ X86_MXCSR_XCPT_MASK, 3043 /*xcpt? */ false, false }, 3044 { { /*src2 */ { FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(1, FP64_FRAC_V1), FP64_QNAN_V(0, FP64_FRAC_V2), FP64_INF(0) } }, 3045 { /*src1 */ { FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(1, FP64_FRAC_V2), FP64_QNAN_V(1, FP64_FRAC_V3), FP64_SNAN(1) } }, 3046 { /* => */ { FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(1, FP64_FRAC_V2), FP64_QNAN_V(1, FP64_FRAC_V3), FP64_SNAN(1) } }, 3047 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 3048 /*128:out */ X86_MXCSR_XCPT_MASK, 3049 /*256:out */ X86_MXCSR_XCPT_MASK, 3050 /*xcpt? */ false, false }, 3051 { { /*src2 */ { FP64_QNAN_V(0, FP64_FRAC_V1), FP64_QNAN_V(0, FP64_FRAC_V1), FP64_QNAN_V(0, FP64_FRAC_V2), FP64_INF(1) } }, 3052 { /*src1 */ { FP64_QNAN_V(0, FP64_FRAC_V0), FP64_QNAN_V(0, FP64_FRAC_V2), FP64_QNAN_V(1, FP64_FRAC_V3), FP64_QNAN(0) } }, 3053 { /* => */ { FP64_QNAN_V(0, FP64_FRAC_V0), FP64_QNAN_V(0, FP64_FRAC_V2), FP64_QNAN_V(1, FP64_FRAC_V3), FP64_QNAN(0) } }, 3054 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 3055 /*128:out */ X86_MXCSR_XCPT_MASK, 3056 /*256:out */ X86_MXCSR_XCPT_MASK, 3057 /*xcpt? */ false, false }, 3058 /* QNan, SNan (Masked). */ 3059 { { /*src2 */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_V1), FP64_QNAN_V(0, FP64_FRAC_V2), FP64_QNAN_V(0, FP64_FRAC_V3) } }, 3060 { /*src1 */ { FP64_SNAN(0), FP64_SNAN_V(1, FP64_FRAC_V2), FP64_SNAN_V(0, FP64_FRAC_V1), FP64_SNAN_V(1, FP64_FRAC_V2) } }, 3061 { /* => */ { FP64_QNAN_V(0, 1), FP64_QNAN_V(1, FP64_FRAC_V2), FP64_SNAN_V(0, FP64_FRAC_V1), FP64_SNAN_V(1, FP64_FRAC_V2) } }, 3062 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 3063 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, 3064 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, 3065 /*xcpt? */ false, false }, 3066 { { /*src2 */ { FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V0), FP64_QNAN_V(0, FP64_FRAC_V1) } }, 3067 { /*src1 */ { FP64_SNAN_V(0, FP64_FRAC_NORM_MIN), FP64_SNAN_V(1, FP64_FRAC_NORM_MIN), FP64_SNAN_V(1, FP64_FRAC_NORM_MAX), FP64_SNAN_V(0, FP64_FRAC_V2) } }, 3068 { /* => */ { FP64_QNAN_V(0, 1), FP64_SNAN_V(1, FP64_FRAC_NORM_MIN), FP64_SNAN_V(1, FP64_FRAC_NORM_MAX), FP64_SNAN_V(0, FP64_FRAC_V2) } }, 3069 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 3070 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, 3071 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, 3072 /*xcpt? */ false, false }, 3073 { { /*src2 */ { FP64_QNAN_V(0, FP64_FRAC_V1), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V0), FP64_INF(0) } }, 3074 { /*src1 */ { FP64_SNAN_V(0, FP64_FRAC_V2), FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(1, FP64_FRAC_NORM_MAX), FP64_QNAN(1) } }, 3075 { /* => */ { FP64_SNAN_V(0, FP64_FRAC_V2), FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(1, FP64_FRAC_NORM_MAX), FP64_QNAN(1) } }, 3076 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 3077 /*128:out */ X86_MXCSR_XCPT_MASK, 3078 /*256:out */ X86_MXCSR_XCPT_MASK, 3079 /*xcpt? */ false, false }, 3080 /* SNan, QNan (Masked). */ 3081 { { /*src2 */ { FP64_SNAN(0), FP64_SNAN_V(0, FP64_FRAC_NORM_MIN), FP64_SNAN_V(0, FP64_FRAC_V1), FP64_SNAN_V(1, FP64_FRAC_V1) } }, 3082 { /*src1 */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(1, FP64_FRAC_V3), FP64_QNAN_V(1, FP64_FRAC_V2) } }, 3083 { /* => */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(1, FP64_FRAC_V3), FP64_QNAN_V(1, FP64_FRAC_V2) } }, 3084 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 3085 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, 3086 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, 3087 /*xcpt? */ false, false }, 3088 { { /*src2 */ { FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_SNAN_V(1, FP64_FRAC_NORM_MAX), FP64_SNAN_V(0, FP64_FRAC_V1), FP64_SNAN_V(0, FP64_FRAC_V1) } }, 3089 { /*src1 */ { FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(1, FP64_FRAC_NORM_MIN), FP64_QNAN_V(1, FP64_FRAC_V3), FP64_QNAN_V(0, FP64_FRAC_V2) } }, 3090 { /* => */ { FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(1, FP64_FRAC_NORM_MIN), FP64_QNAN_V(1, FP64_FRAC_V3), FP64_QNAN_V(0, FP64_FRAC_V2) } }, 3091 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 3092 /*128:out */ X86_MXCSR_XCPT_MASK, 3093 /*256:out */ X86_MXCSR_XCPT_MASK, 3094 /*xcpt? */ false, false }, 3095 { { /*src2 */ { FP64_SNAN_V(0, FP64_FRAC_V0), FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_SNAN_V(0, FP64_FRAC_V1), FP64_SNAN_V(0, FP64_FRAC_V1) } }, 3096 { /*src1 */ { FP64_QNAN_V(0, FP64_FRAC_V1), FP64_QNAN_V(1, FP64_FRAC_NORM_MIN), FP64_QNAN_V(1, FP64_FRAC_V2), FP64_QNAN_V(1, FP64_FRAC_V3) } }, 3097 { /* => */ { FP64_QNAN_V(0, FP64_FRAC_V1), FP64_QNAN_V(1, FP64_FRAC_NORM_MIN), FP64_QNAN_V(1, FP64_FRAC_V2), FP64_QNAN_V(1, FP64_FRAC_V3) } }, 3098 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 3099 /*128:out */ X86_MXCSR_XCPT_MASK, 3100 /*256:out */ X86_MXCSR_XCPT_MASK, 3101 /*xcpt? */ false, false }, 3102 /* SNan, SNan (Masked). */ 3103 { { /*src2 */ { FP64_SNAN(0), FP64_SNAN_V(0, FP64_FRAC_NORM_MIN), FP64_SNAN_V(0, FP64_FRAC_V1), FP64_SNAN_V(0, FP64_FRAC_V2) } }, 3104 { /*src1 */ { FP64_SNAN(0), FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_SNAN_V(0, FP64_FRAC_V0), FP64_SNAN_V(0, FP64_FRAC_V3) } }, 3105 { /* => */ { FP64_QNAN_V(0, 1), FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_SNAN_V(0, FP64_FRAC_V0), FP64_SNAN_V(0, FP64_FRAC_V3) } }, 3106 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 3107 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, 3108 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, 3109 /*xcpt? */ false, false }, 3110 { { /*src2 */ { FP64_SNAN_V(0, FP64_FRAC_NORM_MIN), FP64_SNAN_V(0, FP64_FRAC_V2), FP64_SNAN_V(0, FP64_FRAC_V1), FP64_SNAN_V(0, FP64_FRAC_V2) } }, 3111 { /*src1 */ { FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_SNAN_V(0, FP64_FRAC_V0), FP64_SNAN_V(0, FP64_FRAC_V2), FP64_SNAN_V(1, FP64_FRAC_V3) } }, 3112 { /* => */ { FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_SNAN_V(0, FP64_FRAC_V0), FP64_SNAN_V(0, FP64_FRAC_V2), FP64_SNAN_V(1, FP64_FRAC_V3) } }, 3113 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 3114 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, 3115 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, 3116 /*xcpt? */ false, false }, 3117 { { /*src2 */ { FP64_SNAN_V(0, FP64_FRAC_V1), FP64_SNAN_V(0, FP64_FRAC_V2), FP64_SNAN_V(0, FP64_FRAC_V1), FP64_SNAN_V(0, FP64_FRAC_V2) } }, 3118 { /*src1 */ { FP64_SNAN_V(0, FP64_FRAC_V0), FP64_SNAN_V(0, FP64_FRAC_V3), FP64_SNAN_V(0, FP64_FRAC_V0), FP64_SNAN_V(0, FP64_FRAC_V3) } }, 3119 { /* => */ { FP64_QNAN_V(0, FP64_FRAC_V0), FP64_SNAN_V(0, FP64_FRAC_V3), FP64_SNAN_V(0, FP64_FRAC_V0), FP64_SNAN_V(0, FP64_FRAC_V3) } }, 3120 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 3121 /*128:out */ X86_MXCSR_XCPT_MASK, 3122 /*256:out */ X86_MXCSR_XCPT_MASK, 3123 /*xcpt? */ false, false }, 3124 /* QNan, Norm FP (Masked). */ 3125 { { /*src2 */ { FP64_QNAN(0), FP64_QNAN_V(1, FP64_FRAC_NORM_MAX), FP64_NORM_V0(1), FP64_QNAN_V(0, FP64_FRAC_V1) } }, 3126 { /*src1 */ { FP64_1(0), FP64_1(1), FP64_QNAN_V(1, FP64_FRAC_V0), FP64_NORM_V2(1) } }, 3127 { /* => */ { FP64_QNAN(0), FP64_1(1), FP64_QNAN_V(1, FP64_FRAC_V0), FP64_NORM_V2(1) } }, 3128 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 3129 /*128:out */ X86_MXCSR_XCPT_MASK, 3130 /*256:out */ X86_MXCSR_XCPT_MASK, 3131 /*xcpt? */ false, false }, 3132 /* SNan, Norm FP (Masked). */ 3133 { { /*src2 */ { FP64_SNAN(1), FP64_SNAN_V(1, FP64_FRAC_NORM_MAX), FP64_NORM_V0(1), FP64_SNAN_V(0, FP64_FRAC_V1) } }, 3134 { /*src1 */ { FP64_1(0), FP64_1(0), FP64_SNAN_V(1, FP64_FRAC_V0), FP64_NORM_V2(1) } }, 3135 { /* => */ { FP64_QNAN_V(1, 1), FP64_1(0), FP64_SNAN_V(1, FP64_FRAC_V0), FP64_NORM_V2(1) } }, 3136 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 3137 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, 3138 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, 3139 /*xcpt? */ false, false }, 3140 /* QNan, QNan (Unmasked). */ 3141 /*46*/{ { /*src2 */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V0), FP64_QNAN_V(0, FP64_FRAC_V1) } }, 3142 { /*src1 */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V2) } }, 3143 { /* => */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V2) } }, 3144 /*mxcsr:in */ 0, 3145 /*128:out */ 0, 3146 /*256:out */ 0, 3147 /*xcpt? */ false, false }, 3148 { { /*src2 */ { FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V1), FP64_QNAN_V(0, FP64_FRAC_V2), FP64_QNAN_V(0, FP64_FRAC_V3) } }, 3149 { /*src1 */ { FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(0, FP64_FRAC_V2), FP64_QNAN_V(0, FP64_FRAC_V0), FP64_QNAN_V(0, FP64_FRAC_V2) } }, 3150 { /* => */ { FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(0, FP64_FRAC_V2), FP64_QNAN_V(0, FP64_FRAC_V0), FP64_QNAN_V(0, FP64_FRAC_V2) } }, 3151 /*mxcsr:in */ 0, 3152 /*128:out */ 0, 3153 /*256:out */ 0, 3154 /*xcpt? */ false, false }, 3155 { { /*src2 */ { FP64_QNAN_V(0, FP64_FRAC_V1), FP64_QNAN_V(0, FP64_FRAC_V1), FP64_QNAN_V(0, FP64_FRAC_V2), FP64_QNAN_V(0, FP64_FRAC_V3) } }, 3156 { /*src1 */ { FP64_QNAN_V(0, FP64_FRAC_V2), FP64_QNAN_V(1, FP64_FRAC_V2), FP64_QNAN_V(0, FP64_FRAC_V0), FP64_QNAN_V(1, FP64_FRAC_V0) } }, 3157 { /* => */ { FP64_QNAN_V(0, FP64_FRAC_V2), FP64_QNAN_V(1, FP64_FRAC_V2), FP64_QNAN_V(0, FP64_FRAC_V0), FP64_QNAN_V(1, FP64_FRAC_V0) } }, 3158 /*mxcsr:in */ 0, 3159 /*128:out */ 0, 3160 /*256:out */ 0, 3161 /*xcpt? */ false, false }, 3162 3163 /* QNan, SNan (Unmasked). */ 3164 { { /*src2 */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_V1), FP64_QNAN_V(0, FP64_FRAC_V2), FP64_QNAN_V(0, FP64_FRAC_V3) } }, 3165 { /*src1 */ { FP64_SNAN(0), FP64_SNAN_V(1, FP64_FRAC_V2), FP64_SNAN_V(1, FP64_FRAC_V3), FP64_SNAN_V(0, FP64_FRAC_V2) } }, 3166 { /* => */ { FP64_QNAN_V(0, 1), FP64_QNAN_V(1, FP64_FRAC_V2), FP64_SNAN_V(1, FP64_FRAC_V3), FP64_SNAN_V(0, FP64_FRAC_V2) } }, 3167 /*mxcsr:in */ 0, 3168 /*128:out */ X86_MXCSR_IE, 3169 /*256:out */ X86_MXCSR_IE, 3170 /*xcpt? */ true, true }, 3171 { { /*src2 */ { FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V0), FP64_QNAN_V(0, FP64_FRAC_V1) } }, 3172 { /*src1 */ { FP64_SNAN_V(0, FP64_FRAC_NORM_MIN), FP64_SNAN_V(0, FP64_FRAC_NORM_MIN), FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_SNAN_V(0, FP64_FRAC_V2) } }, 3173 { /* => */ { FP64_QNAN_V(0, 1), FP64_SNAN_V(0, FP64_FRAC_NORM_MIN), FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_SNAN_V(0, FP64_FRAC_V2) } }, 3174 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 3175 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN | X86_MXCSR_IE, 3176 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN | X86_MXCSR_IE, 3177 /*xcpt? */ true, true }, 3178 { { /*src2 */ { FP64_QNAN_V(0, FP64_FRAC_V1), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V0), FP64_QNAN_V(0, FP64_FRAC_V1) } }, 3179 { /*src1 */ { FP64_SNAN_V(0, FP64_FRAC_V2), FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V2) } }, 3180 { /* => */ { FP64_SNAN_V(0, FP64_FRAC_V2), FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V2) } }, 3181 /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, 3182 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, 3183 /*256:out */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, 3184 /*xcpt? */ false, false }, 3185 /* SNan, QNan (Unmasked). */ 3186 { { /*src2 */ { FP64_SNAN(0), FP64_SNAN_V(0, FP64_FRAC_NORM_MIN), FP64_SNAN_V(0, FP64_FRAC_V1), FP64_SNAN_V(0, FP64_FRAC_V1) } }, 3187 { /*src1 */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V3), FP64_QNAN_V(0, FP64_FRAC_V2) } }, 3188 { /* => */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V3), FP64_QNAN_V(0, FP64_FRAC_V2) } }, 3189 /*mxcsr:in */ X86_MXCSR_DAZ, 3190 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_IE, 3191 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_IE, 3192 /*xcpt? */ true, true }, 3193 { { /*src2 */ { FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_SNAN_V(0, FP64_FRAC_V1), FP64_SNAN_V(1, FP64_FRAC_V1) } }, 3194 { /*src1 */ { FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(1, FP64_FRAC_V2), FP64_QNAN_V(1, FP64_FRAC_V0) } }, 3195 { /* => */ { FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(1, FP64_FRAC_V2), FP64_QNAN_V(1, FP64_FRAC_V0) } }, 3196 /*mxcsr:in */ X86_MXCSR_RC_UP, 3197 /*128:out */ X86_MXCSR_RC_UP, 3198 /*256:out */ X86_MXCSR_RC_UP, 3199 /*xcpt? */ false, false }, 3200 { { /*src2 */ { FP64_SNAN_V(0, FP64_FRAC_V0), FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_SNAN_V(0, FP64_FRAC_V1), FP64_SNAN_V(1, FP64_FRAC_V1) } }, 3201 { /*src1 */ { FP64_QNAN_V(0, FP64_FRAC_V3), FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(1, FP64_FRAC_V2), FP64_QNAN_V(1, FP64_FRAC_V3) } }, 3202 { /* => */ { FP64_QNAN_V(0, FP64_FRAC_V3), FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(1, FP64_FRAC_V2), FP64_QNAN_V(1, FP64_FRAC_V3) } }, 3203 /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 3204 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 3205 /*256:out */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 3206 /*xcpt? */ false, false }, 3207 /* SNan, SNan (Unmasked). */ 3208 /*55*/{ { /*src2 */ { FP64_SNAN(0), FP64_SNAN_V(0, FP64_FRAC_NORM_MIN), FP64_SNAN_V(0, FP64_FRAC_V1), FP64_SNAN_V(0, FP64_FRAC_V2) } }, 3209 { /*src1 */ { FP64_SNAN(0), FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_SNAN_V(0, FP64_FRAC_V2), FP64_SNAN_V(1, FP64_FRAC_V0) } }, 3210 { /* => */ { FP64_QNAN_V(0, 1), FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_SNAN_V(0, FP64_FRAC_V2), FP64_SNAN_V(1, FP64_FRAC_V0) } }, 3211 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ, 3212 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_IE, 3213 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_IE, 3214 /*xcpt? */ true, true }, 3215 { { /*src2 */ { FP64_SNAN_V(0, FP64_FRAC_NORM_MIN), FP64_SNAN_V(0, FP64_FRAC_V2), FP64_SNAN_V(0, FP64_FRAC_V1), FP64_SNAN_V(1, FP32_FRAC_V2) } }, 3216 { /*src1 */ { FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_SNAN_V(0, FP64_FRAC_V0), FP64_SNAN_V(1, FP64_FRAC_V2), FP64_SNAN_V(1, FP32_FRAC_V3) } }, 3217 { /* => */ { FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_SNAN_V(0, FP64_FRAC_V0), FP64_SNAN_V(1, FP64_FRAC_V2), FP64_SNAN_V(1, FP32_FRAC_V3) } }, 3218 /*mxcsr:in */ X86_MXCSR_RC_ZERO, 3219 /*128:out */ X86_MXCSR_RC_ZERO | X86_MXCSR_IE, 3220 /*256:out */ X86_MXCSR_RC_ZERO | X86_MXCSR_IE, 3221 /*xcpt? */ true, true }, 3222 { { /*src2 */ { FP64_SNAN_V(0, FP64_FRAC_V1), FP64_SNAN_V(0, FP64_FRAC_V2), FP64_SNAN_V(1, FP64_FRAC_V0), FP64_SNAN_V(0, FP64_FRAC_V2) } }, 3223 { /*src1 */ { FP64_SNAN_V(0, FP64_FRAC_V2), FP64_SNAN_V(1, FP64_FRAC_V3), FP64_SNAN_V(1, FP64_FRAC_V3), FP64_SNAN_V(0, FP64_FRAC_V3) } }, 3224 { /* => */ { FP64_QNAN_V(0, FP64_FRAC_V2), FP64_SNAN_V(1, FP64_FRAC_V3), FP64_SNAN_V(1, FP64_FRAC_V3), FP64_SNAN_V(0, FP64_FRAC_V3) } }, 3225 /*mxcsr:in */ 0, 3226 /*128:out */ 0, 3227 /*256:out */ 0, 3228 /*xcpt? */ false, false }, 3229 /* QNan, Norm FP (Unmasked). */ 3230 { { /*src2 */ { FP64_QNAN(0), FP64_QNAN_V(1, FP64_FRAC_NORM_MAX), FP64_NORM_V0(1), FP64_QNAN_V(0, FP64_FRAC_V1) } }, 3231 { /*src1 */ { FP64_1(0), FP64_INF(1), FP64_QNAN_V(1, FP64_FRAC_V0), FP64_NORM_V2(1) } }, 3232 { /* => */ { FP64_QNAN(0), FP64_INF(1), FP64_QNAN_V(1, FP64_FRAC_V0), FP64_NORM_V2(1) } }, 3233 /*mxcsr:in */ X86_MXCSR_FZ, 3234 /*128:out */ X86_MXCSR_FZ, 3235 /*256:out */ X86_MXCSR_FZ, 3236 /*xcpt? */ false, false }, 3237 /* SNan, Norm FP (Unmasked). */ 3238 /*59*/{ { /*src2 */ { FP64_SNAN(1), FP64_SNAN_V(1, FP64_FRAC_NORM_MAX), FP64_NORM_V0(1), FP64_SNAN_V(0, FP64_FRAC_V1) } }, 3239 { /*src1 */ { FP64_1(0), FP64_INF(0), FP64_SNAN_V(1, FP64_FRAC_V0), FP64_NORM_V2(1) } }, 3240 { /* => */ { FP64_QNAN_V(1, 1), FP64_INF(0), FP64_SNAN_V(1, FP64_FRAC_V0), FP64_NORM_V2(1) } }, 3241 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, 3242 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE, 3243 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE, 3244 /*xcpt? */ true, true }, 3245 /** @todo Underflow, Precision; Rounding, FZ etc. */ 3435 /*32*/ BS3CPUINSTR4_SD_INVALIDS 3436 /** @todo Underflow, Precision; Rounding; FZ etc. */ 3246 3437 }; 3247 3248 3438 3249 3439 static BS3CPUINSTR4_TEST1_T const s_aTests16[] = … … 3531 3721 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_UP, 3532 3722 /*xcpt? */ false, false }, 3533 /** @todo Denormals; Rounding, FZ etc. */3723 /** @todo More Denormals. */ 3534 3724 /* 3535 3725 * Invalids. 3536 3726 */ 3537 /*32*/{ { /*src2 */ { FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_V0), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V5) } }, 3538 { /*src1 */ { FP32_QNAN(0), FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4) } }, 3539 { /* => */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V0), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3) } }, 3540 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 3541 /*128:out */ X86_MXCSR_XCPT_MASK, 3542 /*256:out */ X86_MXCSR_XCPT_MASK, 3543 /*xcpt? */ false, false }, 3544 { { /*src2 */ { FP32_QNAN(0), FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V5) } }, 3545 { /*src1 */ { FP32_QNAN(0), FP32_SNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V4) } }, 3546 { /* => */ { FP32_QNAN(0), FP32_QNAN(0), FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V4) } }, 3547 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 3548 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, 3549 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, 3550 /*xcpt? */ false, false }, 3551 { { /*src2 */ { FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V6) } }, 3552 { /*src1 */ { FP32_SNAN(0), FP32_QNAN(0), FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1) } }, 3553 { /* => */ { FP32_QNAN_V(0, 1), FP32_QNAN_V(0, 1), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V5) } }, 3554 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 3555 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, 3556 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, 3557 /*xcpt? */ false, false }, 3558 { { /*src2 */ { FP32_SNAN(0), FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_V7), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V1) } }, 3559 { /*src1 */ { FP32_SNAN(0), FP32_SNAN(0), FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2) } }, 3560 { /* => */ { FP32_QNAN_V(0, 1), FP32_QNAN_V(0, 1), FP32_QNAN_V(0, 1), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V7), FP32_QNAN_V(0, FP32_FRAC_V6) } }, 3561 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 3562 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, 3563 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, 3564 /*xcpt? */ false, false }, 3565 { { /*src2 */ { FP32_QNAN(0), FP32_NORM_V1(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_NORM_V3(1), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_NORM_V5(1) } }, 3566 { /*src1 */ { FP32_QNAN(0), FP32_1(1), FP32_QNAN_V(1, FP32_FRAC_NORM_MAX), FP32_NORM_V2(1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_NORM_V4(0), FP32_QNAN_V(1, FP32_FRAC_V4), FP32_NORM_V6(1) } }, 3567 { /* => */ { FP32_QNAN(0), FP32_QNAN_V(1, FP32_FRAC_NORM_MAX), FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(1, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V5) } }, 3568 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 3569 /*128:out */ X86_MXCSR_XCPT_MASK, 3570 /*256:out */ X86_MXCSR_XCPT_MASK, 3571 /*xcpt? */ false, false }, 3572 { { /*src2 */ { FP32_SNAN_V(1, FP32_FRAC_NORM_MAX), FP32_1(0), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_NORM_V3(0), FP32_SNAN_V(0, FP32_FRAC_V0), FP32_NORM_V3(1), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_NORM_V7(1) } }, 3573 { /*src1 */ { FP32_SNAN(0), FP32_1(1), FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_NORM_V2(1), FP32_SNAN_V(1, FP32_FRAC_V2), FP32_NORM_V4(0), FP32_SNAN_V(1, FP32_FRAC_V4), FP32_NORM_V6(1) } }, 3574 { /* => */ { FP32_QNAN_V(0, 1), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(1, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(1, FP32_FRAC_V2), FP32_QNAN_V(1, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V0), FP32_QNAN_V(0, FP32_FRAC_V6) } }, 3575 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 3576 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, 3577 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, 3578 /*xcpt? */ false, false }, 3579 { { /*src2 */ { FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_V0), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V5) } }, 3580 { /*src1 */ { FP32_QNAN(0), FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4) } }, 3581 { /* => */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V0), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3) } }, 3582 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, 3583 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, 3584 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, 3585 /*xcpt? */ false, false }, 3586 { { /*src2 */ { FP32_QNAN(0), FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V5) } }, 3587 { /*src1 */ { FP32_QNAN(0), FP32_SNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V4) } }, 3588 { /* => */ { FP32_QNAN(0), FP32_QNAN(0), FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V4) } }, 3589 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_RC_UP, 3590 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_UP | X86_MXCSR_IE, 3591 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_UP | X86_MXCSR_IE, 3592 /*xcpt? */ true, true }, 3593 { { /*src2 */ { FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V6) } }, 3594 { /*src1 */ { FP32_SNAN(0), FP32_QNAN(0), FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1) } }, 3595 { /* => */ { FP32_QNAN_V(0, 1), FP32_QNAN_V(0, 1), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V5) } }, 3596 /*mxcsr:in */ 0, 3597 /*128:out */ X86_MXCSR_IE, 3598 /*256:out */ X86_MXCSR_IE, 3599 /*xcpt? */ true, true }, 3600 { { /*src2 */ { FP32_SNAN(0), FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_V7), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V1) } }, 3601 { /*src1 */ { FP32_SNAN(0), FP32_SNAN(0), FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2) } }, 3602 { /* => */ { FP32_QNAN_V(0, 1), FP32_QNAN_V(0, 1), FP32_QNAN_V(0, 1), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V7), FP32_QNAN_V(0, FP32_FRAC_V6) } }, 3603 /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_UP, 3604 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_UP | X86_MXCSR_IE, 3605 /*256:out */ X86_MXCSR_FZ | X86_MXCSR_RC_UP | X86_MXCSR_IE, 3606 /*xcpt? */ true, true }, 3607 { { /*src2 */ { FP32_QNAN(0), FP32_NORM_V1(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_NORM_V3(1), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_NORM_V5(1) } }, 3608 { /*src1 */ { FP32_QNAN(0), FP32_1(1), FP32_QNAN_V(1, FP32_FRAC_NORM_MAX), FP32_NORM_V2(1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_NORM_V4(0), FP32_QNAN_V(1, FP32_FRAC_V4), FP32_NORM_V6(1) } }, 3609 { /* => */ { FP32_QNAN(0), FP32_QNAN_V(1, FP32_FRAC_NORM_MAX), FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(1, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V5) } }, 3610 /*mxcsr:in */ 0, 3611 /*128:out */ 0, 3612 /*256:out */ 0, 3613 /*xcpt? */ false, false }, 3614 { { /*src2 */ { FP32_SNAN_V(1, FP32_FRAC_NORM_MAX), FP32_1(0), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_NORM_V3(0), FP32_SNAN_V(0, FP32_FRAC_V0), FP32_NORM_V3(1), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_NORM_V7(1) } }, 3615 { /*src1 */ { FP32_SNAN(0), FP32_1(1), FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_NORM_V2(1), FP32_SNAN_V(1, FP32_FRAC_V2), FP32_NORM_V4(0), FP32_SNAN_V(1, FP32_FRAC_V4), FP32_NORM_V6(1) } }, 3616 { /* => */ { FP32_QNAN_V(0, 1), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(1, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(1, FP32_FRAC_V2), FP32_QNAN_V(1, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V0), FP32_QNAN_V(0, FP32_FRAC_V6) } }, 3617 /*mxcsr:in */ X86_MXCSR_RC_UP, 3618 /*128:out */ X86_MXCSR_RC_UP|X86_MXCSR_IE, 3619 /*256:out */ X86_MXCSR_RC_UP|X86_MXCSR_IE, 3620 /*xcpt? */ true, true }, 3621 /** @todo Underflow, Precision; Rounding, FZ etc. */ 3727 /*32*/ BS3CPUINSTR4_H_PS_INVALIDS 3728 /** @todo Underflow; Precision; Rounding; FZ etc. */ 3622 3729 }; 3623 3730 … … 3913 4020 * Invalids. 3914 4021 */ 3915 /*31*/{ { /*src2 */ { FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(0, FP64_FRAC_V0), FP64_QNAN_V(0, FP64_FRAC_V1) } }, 3916 { /*src1 */ { FP64_QNAN(0), FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX) } }, 3917 { /* => */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(0, FP64_FRAC_V0) } }, 3918 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 3919 /*128:out */ X86_MXCSR_XCPT_MASK, 3920 /*256:out */ X86_MXCSR_XCPT_MASK, 3921 /*xcpt? */ false, false }, 3922 { { /*src2 */ { FP64_QNAN(0), FP64_SNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V1) } }, 3923 { /*src1 */ { FP64_QNAN(0), FP64_SNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_SNAN_V(0, FP64_FRAC_V2) } }, 3924 { /* => */ { FP64_QNAN(0), FP64_QNAN(0), FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX) } }, 3925 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 3926 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, 3927 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, 3928 /*xcpt? */ false, false }, 3929 { { /*src2 */ { FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V2), FP64_SNAN_V(0, FP64_FRAC_V1), FP64_QNAN_V(0, FP64_FRAC_V2) } }, 3930 { /*src1 */ { FP64_SNAN(0), FP64_QNAN(0), FP64_SNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(0, FP64_FRAC_V3) } }, 3931 { /* => */ { FP64_QNAN_V(0, 1), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, 1), FP64_QNAN_V(0, FP64_FRAC_V1) } }, 3932 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 3933 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, 3934 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, 3935 /*xcpt? */ false, false }, 3936 { { /*src2 */ { FP64_SNAN(0), FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_SNAN_V(0, FP64_FRAC_NORM_MIN) } }, 3937 { /*src1 */ { FP64_SNAN(0), FP64_SNAN(0), FP64_SNAN_V(0, FP64_FRAC_NORM_MIN), FP64_SNAN_V(0, FP64_FRAC_NORM_MAX) } }, 3938 { /* => */ { FP64_QNAN_V(0, 1), FP64_QNAN_V(0, 1), FP64_QNAN_V(0, 1), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX) } }, 3939 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 3940 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, 3941 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, 3942 /*xcpt? */ false, false }, 3943 { { /*src2 */ { FP64_QNAN(0), FP64_NORM_V1(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V1) } }, 3944 { /*src1 */ { FP64_QNAN(0), FP64_1(1), FP64_QNAN_V(1, FP64_FRAC_NORM_MAX), FP64_NORM_V2(1) } }, 3945 { /* => */ { FP64_QNAN(0), FP64_QNAN(0), FP64_QNAN_V(1, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX) } }, 3946 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 3947 /*128:out */ X86_MXCSR_XCPT_MASK, 3948 /*256:out */ X86_MXCSR_XCPT_MASK, 3949 /*xcpt? */ false, false }, 3950 { { /*src2 */ { FP64_SNAN_V(1, FP64_FRAC_NORM_MAX), FP64_1(0), FP64_SNAN_V(0, FP64_FRAC_V1), FP64_NORM_V3(0) } }, 3951 { /*src1 */ { FP64_SNAN(0), FP64_1(1), FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_NORM_V2(1) } }, 3952 { /* => */ { FP64_QNAN_V(0, 1), FP64_QNAN_V(1, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V1) } }, 3953 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 3954 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, 3955 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, 3956 /*xcpt? */ false, false }, 3957 { { /*src2 */ { FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(0, FP64_FRAC_V0), FP64_QNAN_V(0, FP64_FRAC_V1) } }, 3958 { /*src1 */ { FP64_QNAN(0), FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX) } }, 3959 { /* => */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(0, FP64_FRAC_V0) } }, 3960 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, 3961 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, 3962 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, 3963 /*xcpt? */ false, false }, 3964 { { /*src2 */ { FP64_QNAN(0), FP64_SNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V1) } }, 3965 { /*src1 */ { FP64_QNAN(0), FP64_SNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_SNAN_V(0, FP64_FRAC_V2) } }, 3966 { /* => */ { FP64_QNAN(0), FP64_QNAN(0), FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX) } }, 3967 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_RC_UP, 3968 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_UP | X86_MXCSR_IE, 3969 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_UP | X86_MXCSR_IE, 3970 /*xcpt? */ true, true }, 3971 { { /*src2 */ { FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V2), FP64_SNAN_V(0, FP64_FRAC_V1), FP64_QNAN_V(0, FP64_FRAC_V2) } }, 3972 { /*src1 */ { FP64_SNAN(0), FP64_QNAN(0), FP64_SNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(0, FP64_FRAC_V3) } }, 3973 { /* => */ { FP64_QNAN_V(0, 1), FP64_QNAN_V(0, 1), FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(0, FP64_FRAC_V1) } }, 3974 /*mxcsr:in */ 0, 3975 /*128:out */ X86_MXCSR_IE, 3976 /*256:out */ X86_MXCSR_IE, 3977 /*xcpt? */ true, true }, 3978 { { /*src2 */ { FP64_SNAN(0), FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_SNAN_V(0, FP64_FRAC_NORM_MIN) } }, 3979 { /*src1 */ { FP64_SNAN(0), FP64_SNAN(0), FP64_SNAN_V(0, FP64_FRAC_NORM_MIN), FP64_SNAN_V(0, FP64_FRAC_NORM_MAX) } }, 3980 { /* => */ { FP64_QNAN_V(0, 1), FP64_QNAN_V(0, 1), FP64_QNAN_V(0, 1), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX) } }, 3981 /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_UP, 3982 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_UP | X86_MXCSR_IE, 3983 /*256:out */ X86_MXCSR_FZ | X86_MXCSR_RC_UP | X86_MXCSR_IE, 3984 /*xcpt? */ true, true }, 3985 { { /*src2 */ { FP64_QNAN(0), FP64_NORM_V1(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V1) } }, 3986 { /*src1 */ { FP64_QNAN(0), FP64_1(1), FP64_QNAN_V(1, FP64_FRAC_NORM_MAX), FP64_NORM_V2(1) } }, 3987 { /* => */ { FP64_QNAN(0), FP64_QNAN(0), FP64_QNAN_V(1, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX) } }, 3988 /*mxcsr:in */ 0, 3989 /*128:out */ 0, 3990 /*256:out */ 0, 3991 /*xcpt? */ false, false }, 3992 { { /*src2 */ { FP64_SNAN_V(1, FP64_FRAC_NORM_MAX), FP64_1(0), FP64_SNAN_V(0, FP64_FRAC_V1), FP64_NORM_V3(0) } }, 3993 { /*src1 */ { FP64_SNAN(0), FP64_1(1), FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_NORM_V2(1) } }, 3994 { /* => */ { FP64_QNAN_V(0, 1), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(1, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V1) } }, 3995 /*mxcsr:in */ X86_MXCSR_RC_UP, 3996 /*128:out */ X86_MXCSR_RC_UP|X86_MXCSR_IE, 3997 /*256:out */ X86_MXCSR_RC_UP|X86_MXCSR_IE, 3998 /*xcpt? */ true, true }, 3999 /** @todo Underflow, Precision; Rounding, FZ etc. */ 4022 /*31*/ BS3CPUINSTR4_H_PD_INVALIDS 4023 /** @todo Underflow; Precision; Rounding; FZ etc. */ 4000 4024 }; 4001 4025 … … 4309 4333 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP | X86_MXCSR_XCPT_MASK, 4310 4334 /*xcpt? */ false, false }, 4311 /** @todo More denormals ; Underflow, Precision; Rounding, FZ etc. */4335 /** @todo More denormals. */ 4312 4336 /* 4313 4337 * Invalids. 4314 4338 */ 4315 /*34*/{ { /*src2 */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V0), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V5) } }, 4316 { /*src1 */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4) } }, 4317 { /* => */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4) } }, 4318 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 4319 /*128:out */ X86_MXCSR_XCPT_MASK, 4320 /*256:out */ X86_MXCSR_XCPT_MASK, 4321 /*xcpt? */ false, false }, 4322 { { /*src2 */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V0), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V5) } }, 4323 { /*src1 */ { FP32_SNAN(0), FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V4) } }, 4324 { /* => */ { FP32_QNAN_V(0, 1), FP32_QNAN_V(0, 1), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4) } }, 4325 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 4326 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, 4327 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, 4328 /*xcpt? */ false, false }, 4329 { { /*src2 */ { FP32_SNAN(0), FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V6) } }, 4330 { /*src1 */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1) } }, 4331 { /* => */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1) } }, 4332 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ, 4333 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_IE, 4334 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_IE, 4335 /*xcpt? */ false, false }, 4336 { { /*src2 */ { FP32_SNAN(0), FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V7), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V1) } }, 4337 { /*src1 */ { FP32_SNAN(0), FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2) } }, 4338 { /* => */ { FP32_QNAN_V(0, 1), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2) } }, 4339 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 4340 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, 4341 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, 4342 /*xcpt? */ false, false }, 4343 { { /*src2 */ { FP32_QNAN(0), FP32_QNAN_V(1, FP32_FRAC_NORM_MAX), FP32_NORM_V0(1), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_NORM_V3(0), FP32_QNAN_V(1, FP32_FRAC_V3), FP32_NORM_V5(0), FP32_QNAN_V(1, FP32_FRAC_V5) } }, 4344 { /*src1 */ { FP32_1(0), FP32_1(1), FP32_QNAN_V(1, FP32_FRAC_V0), FP32_NORM_V2(1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_NORM_V4(0), FP32_QNAN_V(1, FP32_FRAC_V4), FP32_NORM_V6(1) } }, 4345 { /* => */ { FP32_QNAN(0), FP32_QNAN_V(1, FP32_FRAC_NORM_MAX), FP32_QNAN_V(1, FP32_FRAC_V0), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(1, FP32_FRAC_V3), FP32_QNAN_V(1, FP32_FRAC_V4), FP32_QNAN_V(1, FP32_FRAC_V5) } }, 4346 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 4347 /*128:out */ X86_MXCSR_XCPT_MASK, 4348 /*256:out */ X86_MXCSR_XCPT_MASK, 4349 /*xcpt? */ false, false }, 4350 { { /*src2 */ { FP32_SNAN(1), FP32_SNAN_V(1, FP32_FRAC_NORM_MAX), FP32_NORM_V0(1), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_NORM_V3(0), FP32_SNAN_V(1, FP32_FRAC_V3), FP32_NORM_V5(0), FP32_SNAN_V(1, FP32_FRAC_V5) } }, 4351 { /*src1 */ { FP32_1(0), FP32_1(0), FP32_SNAN_V(1, FP32_FRAC_V0), FP32_NORM_V2(1), FP32_SNAN_V(1, FP32_FRAC_V2), FP32_NORM_V4(0), FP32_SNAN_V(1, FP32_FRAC_V4), FP32_NORM_V6(1) } }, 4352 { /* => */ { FP32_QNAN_V(1, 1), FP32_QNAN_V(1, FP32_FRAC_NORM_MAX), FP32_QNAN_V(1, FP32_FRAC_V0), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(1, FP32_FRAC_V2), FP32_QNAN_V(1, FP32_FRAC_V3), FP32_QNAN_V(1, FP32_FRAC_V4), FP32_QNAN_V(1, FP32_FRAC_V5) } }, 4353 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 4354 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, 4355 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, 4356 /*xcpt? */ false, false }, 4357 { { /*src2 */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V0), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V5) } }, 4358 { /*src1 */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4) } }, 4359 { /* => */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4) } }, 4360 /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 4361 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 4362 /*256:out */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 4363 /*xcpt? */ false, false }, 4364 { { /*src2 */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V0), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V5) } }, 4365 { /*src1 */ { FP32_SNAN(0), FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V4) } }, 4366 { /* => */ { FP32_QNAN_V(0, 1), FP32_QNAN_V(0, 1), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4) } }, 4367 /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, 4368 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE, 4369 /*256:out */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE, 4370 /*xcpt? */ true, true }, 4371 { { /*src2 */ { FP32_SNAN(0), FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V6) } }, 4372 { /*src1 */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1) } }, 4373 { /* => */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1) } }, 4374 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, 4375 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE, 4376 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE, 4377 /*xcpt? */ true, true }, 4378 { { /*src2 */ { FP32_SNAN(0), FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V7), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V1) } }, 4379 { /*src1 */ { FP32_SNAN(0), FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2) } }, 4380 { /* => */ { FP32_QNAN_V(0, 1), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2) } }, 4381 /*mxcsr:in */ X86_MXCSR_RC_UP, 4382 /*128:out */ X86_MXCSR_RC_UP | X86_MXCSR_IE, 4383 /*256:out */ X86_MXCSR_RC_UP | X86_MXCSR_IE, 4384 /*xcpt? */ true, true }, 4385 { { /*src2 */ { FP32_QNAN(0), FP32_QNAN_V(1, FP32_FRAC_NORM_MAX), FP32_NORM_V0(1), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_NORM_V3(0), FP32_QNAN_V(1, FP32_FRAC_V3), FP32_NORM_V5(0), FP32_QNAN_V(1, FP32_FRAC_V5) } }, 4386 { /*src1 */ { FP32_1(0), FP32_1(1), FP32_QNAN_V(1, FP32_FRAC_V0), FP32_NORM_V2(1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_NORM_V4(0), FP32_QNAN_V(1, FP32_FRAC_V4), FP32_NORM_V6(1) } }, 4387 { /* => */ { FP32_QNAN(0), FP32_QNAN_V(1, FP32_FRAC_NORM_MAX), FP32_QNAN_V(1, FP32_FRAC_V0), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(1, FP32_FRAC_V3), FP32_QNAN_V(1, FP32_FRAC_V4), FP32_QNAN_V(1, FP32_FRAC_V5) } }, 4388 /*mxcsr:in */ X86_MXCSR_RC_DOWN, 4389 /*128:out */ X86_MXCSR_RC_DOWN, 4390 /*256:out */ X86_MXCSR_RC_DOWN, 4391 /*xcpt? */ false, false }, 4392 { { /*src2 */ { FP32_SNAN(1), FP32_SNAN_V(1, FP32_FRAC_NORM_MAX), FP32_NORM_V0(1), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_NORM_V3(0), FP32_SNAN_V(1, FP32_FRAC_V3), FP32_NORM_V5(0), FP32_SNAN_V(1, FP32_FRAC_V5) } }, 4393 { /*src1 */ { FP32_1(0), FP32_1(0), FP32_SNAN_V(1, FP32_FRAC_V0), FP32_NORM_V2(1), FP32_SNAN_V(1, FP32_FRAC_V2), FP32_NORM_V4(0), FP32_SNAN_V(1, FP32_FRAC_V4), FP32_NORM_V6(1) } }, 4394 { /* => */ { FP32_QNAN_V(1, 1), FP32_QNAN_V(1, FP32_FRAC_NORM_MAX), FP32_QNAN_V(1, FP32_FRAC_V0), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(1, FP32_FRAC_V2), FP32_QNAN_V(1, FP32_FRAC_V3), FP32_QNAN_V(1, FP32_FRAC_V4), FP32_QNAN_V(1, FP32_FRAC_V5) } }, 4395 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO, 4396 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE, 4397 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE, 4398 /*xcpt? */ true, true }, 4339 /*34*/ BS3CPUINSTR4_PS_INVALIDS 4340 /** @todo Underflow; Precision; Rounding; FZ etc. */ 4399 4341 }; 4400 4342 … … 4691 4633 * Invalids. 4692 4634 */ 4693 /*31*/{ { /*src2 */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V0), FP64_QNAN_V(0, FP64_FRAC_V0) } }, 4694 { /*src1 */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V3) } }, 4695 { /* => */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V3) } }, 4696 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 4697 /*128:out */ X86_MXCSR_XCPT_MASK, 4698 /*256:out */ X86_MXCSR_XCPT_MASK, 4699 /*xcpt? */ false, false }, 4700 { { /*src2 */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V0), FP64_QNAN_V(0, FP64_FRAC_V2) } }, 4701 { /*src1 */ { FP64_SNAN(0), FP64_SNAN_V(0, FP64_FRAC_NORM_MIN), FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_SNAN_V(0, FP64_FRAC_V0) } }, 4702 { /* => */ { FP64_QNAN_V(0, 1), FP64_QNAN_V(0, 1), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V0) } }, 4703 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 4704 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, 4705 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, 4706 /*xcpt? */ false, false }, 4707 { { /*src2 */ { FP64_SNAN(0), FP64_SNAN_V(0, FP64_FRAC_NORM_MIN), FP64_SNAN_V(0, FP64_FRAC_V0), FP64_SNAN_V(0, FP64_FRAC_V1) } }, 4708 { /*src1 */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V2), FP64_QNAN_V(0, FP64_FRAC_V3) } }, 4709 { /* => */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V2), FP64_QNAN_V(0, FP64_FRAC_V3) } }, 4710 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 4711 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, 4712 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, 4713 /*xcpt? */ false, false }, 4714 { { /*src2 */ { FP64_SNAN(0), FP64_SNAN_V(0, FP64_FRAC_NORM_MIN), FP64_SNAN_V(0, FP64_FRAC_V1), FP64_SNAN_V(0, FP64_FRAC_V2) } }, 4715 { /*src1 */ { FP64_SNAN(0), FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_SNAN_V(0, FP64_FRAC_V3), FP64_SNAN_V(0, FP64_FRAC_V0) } }, 4716 { /* => */ { FP64_QNAN_V(0, 1), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V3), FP64_QNAN_V(0, FP64_FRAC_V0) } }, 4717 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 4718 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, 4719 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, 4720 /*xcpt? */ false, false }, 4721 { { /*src2 */ { FP64_QNAN(0), FP64_QNAN_V(1, FP64_FRAC_NORM_MAX), FP64_NORM_V0(1), FP64_QNAN_V(0, FP64_FRAC_V1) } }, 4722 { /*src1 */ { FP64_1(0), FP64_1(1), FP64_QNAN_V(1, FP64_FRAC_V0), FP64_NORM_V2(1) } }, 4723 { /* => */ { FP64_QNAN(0), FP64_QNAN_V(1, FP64_FRAC_NORM_MAX), FP64_QNAN_V(1, FP64_FRAC_V0), FP64_QNAN_V(0, FP64_FRAC_V1) } }, 4724 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 4725 /*128:out */ X86_MXCSR_XCPT_MASK, 4726 /*256:out */ X86_MXCSR_XCPT_MASK, 4727 /*xcpt? */ false, false }, 4728 { { /*src2 */ { FP64_SNAN(1), FP64_SNAN_V(1, FP64_FRAC_NORM_MAX), FP64_NORM_V0(1), FP64_SNAN_V(0, FP64_FRAC_V1) } }, 4729 { /*src1 */ { FP64_1(0), FP64_1(0), FP64_SNAN_V(1, FP64_FRAC_V0), FP64_NORM_V2(1) } }, 4730 { /* => */ { FP64_QNAN_V(1, 1), FP64_QNAN_V(1, FP64_FRAC_NORM_MAX), FP64_QNAN_V(1, FP64_FRAC_V0), FP64_QNAN_V(0, FP64_FRAC_V1) } }, 4731 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 4732 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, 4733 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, 4734 /*xcpt? */ false, false }, 4735 { { /*src2 */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V0) , FP64_QNAN_V(0, FP64_FRAC_V1) } }, 4736 { /*src1 */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V3) } }, 4737 { /* => */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V3) } }, 4738 /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 4739 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 4740 /*256:out */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 4741 /*xcpt? */ false, false }, 4742 { { /*src2 */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V0), FP64_QNAN_V(0, FP32_FRAC_V1) } }, 4743 { /*src1 */ { FP64_SNAN(0), FP64_SNAN_V(0, FP64_FRAC_NORM_MIN), FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_SNAN_V(0, FP32_FRAC_V2) } }, 4744 { /* => */ { FP64_QNAN_V(0, 1), FP64_QNAN_V(0, 1), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP32_FRAC_V2) } }, 4745 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, 4746 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE, 4747 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE, 4748 /*xcpt? */ true, true }, 4749 { { /*src2 */ { FP64_SNAN(0), FP64_SNAN_V(0, FP64_FRAC_NORM_MIN), FP64_SNAN_V(0, FP64_FRAC_V1), FP64_SNAN_V(0, FP64_FRAC_V1) } }, 4750 { /*src1 */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V3), FP64_QNAN_V(0, FP64_FRAC_V2) } }, 4751 { /* => */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V3), FP64_QNAN_V(0, FP64_FRAC_V2) } }, 4752 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP, 4753 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP | X86_MXCSR_IE, 4754 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP | X86_MXCSR_IE, 4755 /*xcpt? */ true, true }, 4756 { { /*src2 */ { FP64_SNAN(0), FP64_SNAN_V(0, FP64_FRAC_NORM_MIN), FP64_SNAN_V(0, FP64_FRAC_V1), FP64_SNAN_V(0, FP64_FRAC_V2) } }, 4757 { /*src1 */ { FP64_SNAN(0), FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_SNAN_V(0, FP64_FRAC_V0), FP64_SNAN_V(0, FP64_FRAC_V3) } }, 4758 { /* => */ { FP64_QNAN_V(0, 1), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V0), FP64_QNAN_V(0, FP64_FRAC_V3) } }, 4759 /*mxcsr:in */ X86_MXCSR_RC_UP, 4760 /*128:out */ X86_MXCSR_RC_UP | X86_MXCSR_IE, 4761 /*256:out */ X86_MXCSR_RC_UP | X86_MXCSR_IE, 4762 /*xcpt? */ true, true }, 4763 { { /*src2 */ { FP64_QNAN(0), FP64_QNAN_V(1, FP64_FRAC_NORM_MAX), FP64_NORM_V0(1), FP64_QNAN_V(0, FP64_FRAC_V1) } }, 4764 { /*src1 */ { FP64_1(0), FP64_1(1), FP64_QNAN_V(1, FP64_FRAC_V3), FP64_NORM_V2(1) } }, 4765 { /* => */ { FP64_QNAN(0), FP64_QNAN_V(1, FP64_FRAC_NORM_MAX), FP64_QNAN_V(1, FP64_FRAC_V3), FP64_QNAN_V(0, FP64_FRAC_V1) } }, 4766 /*mxcsr:in */ X86_MXCSR_RC_DOWN, 4767 /*128:out */ X86_MXCSR_RC_DOWN, 4768 /*256:out */ X86_MXCSR_RC_DOWN, 4769 /*xcpt? */ false, false }, 4770 { { /*src2 */ { FP64_SNAN(1), FP64_SNAN_V(1, FP64_FRAC_NORM_MAX), FP64_NORM_V0(1), FP64_SNAN_V(0, FP64_FRAC_V2) } }, 4771 { /*src1 */ { FP64_1(0), FP64_1(0), FP64_SNAN_V(1, FP64_FRAC_V3), FP64_NORM_V2(1) } }, 4772 { /* => */ { FP64_QNAN_V(1, 1), FP64_QNAN_V(1, FP64_FRAC_NORM_MAX), FP64_QNAN_V(1, FP64_FRAC_V3), FP64_QNAN_V(0, FP64_FRAC_V2) } }, 4773 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO, 4774 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE, 4775 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE, 4776 /*xcpt? */ true, true }, 4777 /** @todo Underflow, Precision; Rounding, FZ etc. */ 4635 /*31*/ BS3CPUINSTR4_PD_INVALIDS 4636 /** @todo Underflow; Precision; Rounding; FZ etc. */ 4778 4637 }; 4779 4638 … … 5080 4939 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_UP, 5081 4940 /*xcpt? */ false, false }, 5082 /** @todo More denormals; Underflow, Precision; Rounding, FZ etc. */ 4941 /** @todo More denormals. */ 4942 /* 4943 * Invalids. 4944 */ 4945 /*30*/ BS3CPUINSTR4_SS_INVALIDS 4946 /** @todo Underflow; Precision; Rounding; FZ etc. */ 5083 4947 }; 5084 4948 … … 5406 5270 * Invalids. 5407 5271 */ 5408 /* QNan, QNan (Masked). */ 5409 /*32*/{ { /*src2 */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V0), FP64_QNAN_V(0, FP64_FRAC_V1) } }, 5410 { /*src1 */ { FP64_QNAN(0), FP64_QNAN_V(1, FP64_FRAC_NORM_MIN), FP64_QNAN_V(1, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V2) } }, 5411 { /* => */ { FP64_QNAN(0), FP64_QNAN_V(1, FP64_FRAC_NORM_MIN), FP64_QNAN_V(1, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V2) } }, 5412 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 5413 /*128:out */ X86_MXCSR_XCPT_MASK, 5414 /*256:out */ X86_MXCSR_XCPT_MASK, 5415 /*xcpt? */ false, false }, 5416 { { /*src2 */ { FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(1, FP64_FRAC_V1), FP64_QNAN_V(0, FP64_FRAC_V2), FP64_INF(0) } }, 5417 { /*src1 */ { FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(1, FP64_FRAC_V2), FP64_QNAN_V(1, FP64_FRAC_V3), FP64_SNAN(1) } }, 5418 { /* => */ { FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(1, FP64_FRAC_V2), FP64_QNAN_V(1, FP64_FRAC_V3), FP64_SNAN(1) } }, 5419 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 5420 /*128:out */ X86_MXCSR_XCPT_MASK, 5421 /*256:out */ X86_MXCSR_XCPT_MASK, 5422 /*xcpt? */ false, false }, 5423 { { /*src2 */ { FP64_QNAN_V(0, FP64_FRAC_V1), FP64_QNAN_V(0, FP64_FRAC_V1), FP64_QNAN_V(0, FP64_FRAC_V2), FP64_INF(1) } }, 5424 { /*src1 */ { FP64_QNAN_V(0, FP64_FRAC_V0), FP64_QNAN_V(0, FP64_FRAC_V2), FP64_QNAN_V(1, FP64_FRAC_V3), FP64_QNAN(0) } }, 5425 { /* => */ { FP64_QNAN_V(0, FP64_FRAC_V0), FP64_QNAN_V(0, FP64_FRAC_V2), FP64_QNAN_V(1, FP64_FRAC_V3), FP64_QNAN(0) } }, 5426 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 5427 /*128:out */ X86_MXCSR_XCPT_MASK, 5428 /*256:out */ X86_MXCSR_XCPT_MASK, 5429 /*xcpt? */ false, false }, 5430 /* QNan, SNan (Masked). */ 5431 { { /*src2 */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_V1), FP64_QNAN_V(0, FP64_FRAC_V2), FP64_QNAN_V(0, FP64_FRAC_V3) } }, 5432 { /*src1 */ { FP64_SNAN(0), FP64_SNAN_V(1, FP64_FRAC_V2), FP64_SNAN_V(0, FP64_FRAC_V1), FP64_SNAN_V(1, FP64_FRAC_V2) } }, 5433 { /* => */ { FP64_QNAN_V(0, 1), FP64_QNAN_V(1, FP64_FRAC_V2), FP64_SNAN_V(0, FP64_FRAC_V1), FP64_SNAN_V(1, FP64_FRAC_V2) } }, 5434 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 5435 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, 5436 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, 5437 /*xcpt? */ false, false }, 5438 { { /*src2 */ { FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V0), FP64_QNAN_V(0, FP64_FRAC_V1) } }, 5439 { /*src1 */ { FP64_SNAN_V(0, FP64_FRAC_NORM_MIN), FP64_SNAN_V(1, FP64_FRAC_NORM_MIN), FP64_SNAN_V(1, FP64_FRAC_NORM_MAX), FP64_SNAN_V(0, FP64_FRAC_V2) } }, 5440 { /* => */ { FP64_QNAN_V(0, 1), FP64_SNAN_V(1, FP64_FRAC_NORM_MIN), FP64_SNAN_V(1, FP64_FRAC_NORM_MAX), FP64_SNAN_V(0, FP64_FRAC_V2) } }, 5441 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 5442 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, 5443 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, 5444 /*xcpt? */ false, false }, 5445 { { /*src2 */ { FP64_QNAN_V(0, FP64_FRAC_V1), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V0), FP64_INF(0) } }, 5446 { /*src1 */ { FP64_SNAN_V(0, FP64_FRAC_V2), FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(1, FP64_FRAC_NORM_MAX), FP64_QNAN(1) } }, 5447 { /* => */ { FP64_SNAN_V(0, FP64_FRAC_V2), FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(1, FP64_FRAC_NORM_MAX), FP64_QNAN(1) } }, 5448 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 5449 /*128:out */ X86_MXCSR_XCPT_MASK, 5450 /*256:out */ X86_MXCSR_XCPT_MASK, 5451 /*xcpt? */ false, false }, 5452 /* SNan, QNan (Masked). */ 5453 { { /*src2 */ { FP64_SNAN(0), FP64_SNAN_V(0, FP64_FRAC_NORM_MIN), FP64_SNAN_V(0, FP64_FRAC_V1), FP64_SNAN_V(1, FP64_FRAC_V1) } }, 5454 { /*src1 */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(1, FP64_FRAC_V3), FP64_QNAN_V(1, FP64_FRAC_V2) } }, 5455 { /* => */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(1, FP64_FRAC_V3), FP64_QNAN_V(1, FP64_FRAC_V2) } }, 5456 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 5457 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, 5458 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, 5459 /*xcpt? */ false, false }, 5460 { { /*src2 */ { FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_SNAN_V(1, FP64_FRAC_NORM_MAX), FP64_SNAN_V(0, FP64_FRAC_V1), FP64_SNAN_V(0, FP64_FRAC_V1) } }, 5461 { /*src1 */ { FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(1, FP64_FRAC_NORM_MIN), FP64_QNAN_V(1, FP64_FRAC_V3), FP64_QNAN_V(0, FP64_FRAC_V2) } }, 5462 { /* => */ { FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(1, FP64_FRAC_NORM_MIN), FP64_QNAN_V(1, FP64_FRAC_V3), FP64_QNAN_V(0, FP64_FRAC_V2) } }, 5463 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 5464 /*128:out */ X86_MXCSR_XCPT_MASK, 5465 /*256:out */ X86_MXCSR_XCPT_MASK, 5466 /*xcpt? */ false, false }, 5467 { { /*src2 */ { FP64_SNAN_V(0, FP64_FRAC_V0), FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_SNAN_V(0, FP64_FRAC_V1), FP64_SNAN_V(0, FP64_FRAC_V1) } }, 5468 { /*src1 */ { FP64_QNAN_V(0, FP64_FRAC_V1), FP64_QNAN_V(1, FP64_FRAC_NORM_MIN), FP64_QNAN_V(1, FP64_FRAC_V2), FP64_QNAN_V(1, FP64_FRAC_V3) } }, 5469 { /* => */ { FP64_QNAN_V(0, FP64_FRAC_V1), FP64_QNAN_V(1, FP64_FRAC_NORM_MIN), FP64_QNAN_V(1, FP64_FRAC_V2), FP64_QNAN_V(1, FP64_FRAC_V3) } }, 5470 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 5471 /*128:out */ X86_MXCSR_XCPT_MASK, 5472 /*256:out */ X86_MXCSR_XCPT_MASK, 5473 /*xcpt? */ false, false }, 5474 /* SNan, SNan (Masked). */ 5475 { { /*src2 */ { FP64_SNAN(0), FP64_SNAN_V(0, FP64_FRAC_NORM_MIN), FP64_SNAN_V(0, FP64_FRAC_V1), FP64_SNAN_V(0, FP64_FRAC_V2) } }, 5476 { /*src1 */ { FP64_SNAN(0), FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_SNAN_V(0, FP64_FRAC_V0), FP64_SNAN_V(0, FP64_FRAC_V3) } }, 5477 { /* => */ { FP64_QNAN_V(0, 1), FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_SNAN_V(0, FP64_FRAC_V0), FP64_SNAN_V(0, FP64_FRAC_V3) } }, 5478 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 5479 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, 5480 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, 5481 /*xcpt? */ false, false }, 5482 { { /*src2 */ { FP64_SNAN_V(0, FP64_FRAC_NORM_MIN), FP64_SNAN_V(0, FP64_FRAC_V2), FP64_SNAN_V(0, FP64_FRAC_V1), FP64_SNAN_V(0, FP64_FRAC_V2) } }, 5483 { /*src1 */ { FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_SNAN_V(0, FP64_FRAC_V0), FP64_SNAN_V(0, FP64_FRAC_V2), FP64_SNAN_V(1, FP64_FRAC_V3) } }, 5484 { /* => */ { FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_SNAN_V(0, FP64_FRAC_V0), FP64_SNAN_V(0, FP64_FRAC_V2), FP64_SNAN_V(1, FP64_FRAC_V3) } }, 5485 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 5486 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, 5487 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, 5488 /*xcpt? */ false, false }, 5489 { { /*src2 */ { FP64_SNAN_V(0, FP64_FRAC_V1), FP64_SNAN_V(0, FP64_FRAC_V2), FP64_SNAN_V(0, FP64_FRAC_V1), FP64_SNAN_V(0, FP64_FRAC_V2) } }, 5490 { /*src1 */ { FP64_SNAN_V(0, FP64_FRAC_V0), FP64_SNAN_V(0, FP64_FRAC_V3), FP64_SNAN_V(0, FP64_FRAC_V0), FP64_SNAN_V(0, FP64_FRAC_V3) } }, 5491 { /* => */ { FP64_QNAN_V(0, FP64_FRAC_V0), FP64_SNAN_V(0, FP64_FRAC_V3), FP64_SNAN_V(0, FP64_FRAC_V0), FP64_SNAN_V(0, FP64_FRAC_V3) } }, 5492 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 5493 /*128:out */ X86_MXCSR_XCPT_MASK, 5494 /*256:out */ X86_MXCSR_XCPT_MASK, 5495 /*xcpt? */ false, false }, 5496 /* QNan, Norm FP (Masked). */ 5497 { { /*src2 */ { FP64_QNAN(0), FP64_QNAN_V(1, FP64_FRAC_NORM_MAX), FP64_NORM_V0(1), FP64_QNAN_V(0, FP64_FRAC_V1) } }, 5498 { /*src1 */ { FP64_1(0), FP64_1(1), FP64_QNAN_V(1, FP64_FRAC_V0), FP64_NORM_V2(1) } }, 5499 { /* => */ { FP64_QNAN(0), FP64_1(1), FP64_QNAN_V(1, FP64_FRAC_V0), FP64_NORM_V2(1) } }, 5500 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 5501 /*128:out */ X86_MXCSR_XCPT_MASK, 5502 /*256:out */ X86_MXCSR_XCPT_MASK, 5503 /*xcpt? */ false, false }, 5504 /* SNan, Norm FP (Masked). */ 5505 { { /*src2 */ { FP64_SNAN(1), FP64_SNAN_V(1, FP64_FRAC_NORM_MAX), FP64_NORM_V0(1), FP64_SNAN_V(0, FP64_FRAC_V1) } }, 5506 { /*src1 */ { FP64_1(0), FP64_1(0), FP64_SNAN_V(1, FP64_FRAC_V0), FP64_NORM_V2(1) } }, 5507 { /* => */ { FP64_QNAN_V(1, 1), FP64_1(0), FP64_SNAN_V(1, FP64_FRAC_V0), FP64_NORM_V2(1) } }, 5508 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 5509 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, 5510 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, 5511 /*xcpt? */ false, false }, 5512 /* QNan, QNan (Unmasked). */ 5513 /*46*/{ { /*src2 */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V0), FP64_QNAN_V(0, FP64_FRAC_V1) } }, 5514 { /*src1 */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V2) } }, 5515 { /* => */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V2) } }, 5516 /*mxcsr:in */ 0, 5517 /*128:out */ 0, 5518 /*256:out */ 0, 5519 /*xcpt? */ false, false }, 5520 { { /*src2 */ { FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V1), FP64_QNAN_V(0, FP64_FRAC_V2), FP64_QNAN_V(0, FP64_FRAC_V3) } }, 5521 { /*src1 */ { FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(0, FP64_FRAC_V2), FP64_QNAN_V(0, FP64_FRAC_V0), FP64_QNAN_V(0, FP64_FRAC_V2) } }, 5522 { /* => */ { FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(0, FP64_FRAC_V2), FP64_QNAN_V(0, FP64_FRAC_V0), FP64_QNAN_V(0, FP64_FRAC_V2) } }, 5523 /*mxcsr:in */ 0, 5524 /*128:out */ 0, 5525 /*256:out */ 0, 5526 /*xcpt? */ false, false }, 5527 { { /*src2 */ { FP64_QNAN_V(0, FP64_FRAC_V1), FP64_QNAN_V(0, FP64_FRAC_V1), FP64_QNAN_V(0, FP64_FRAC_V2), FP64_QNAN_V(0, FP64_FRAC_V3) } }, 5528 { /*src1 */ { FP64_QNAN_V(0, FP64_FRAC_V2), FP64_QNAN_V(1, FP64_FRAC_V2), FP64_QNAN_V(0, FP64_FRAC_V0), FP64_QNAN_V(1, FP64_FRAC_V0) } }, 5529 { /* => */ { FP64_QNAN_V(0, FP64_FRAC_V2), FP64_QNAN_V(1, FP64_FRAC_V2), FP64_QNAN_V(0, FP64_FRAC_V0), FP64_QNAN_V(1, FP64_FRAC_V0) } }, 5530 /*mxcsr:in */ 0, 5531 /*128:out */ 0, 5532 /*256:out */ 0, 5533 /*xcpt? */ false, false }, 5534 5535 /* QNan, SNan (Unmasked). */ 5536 { { /*src2 */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_V1), FP64_QNAN_V(0, FP64_FRAC_V2), FP64_QNAN_V(0, FP64_FRAC_V3) } }, 5537 { /*src1 */ { FP64_SNAN(0), FP64_SNAN_V(1, FP64_FRAC_V2), FP64_SNAN_V(1, FP64_FRAC_V3), FP64_SNAN_V(0, FP64_FRAC_V2) } }, 5538 { /* => */ { FP64_QNAN_V(0, 1), FP64_QNAN_V(1, FP64_FRAC_V2), FP64_SNAN_V(1, FP64_FRAC_V3), FP64_SNAN_V(0, FP64_FRAC_V2) } }, 5539 /*mxcsr:in */ 0, 5540 /*128:out */ X86_MXCSR_IE, 5541 /*256:out */ X86_MXCSR_IE, 5542 /*xcpt? */ true, true }, 5543 { { /*src2 */ { FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V0), FP64_QNAN_V(0, FP64_FRAC_V1) } }, 5544 { /*src1 */ { FP64_SNAN_V(0, FP64_FRAC_NORM_MIN), FP64_SNAN_V(0, FP64_FRAC_NORM_MIN), FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_SNAN_V(0, FP64_FRAC_V2) } }, 5545 { /* => */ { FP64_QNAN_V(0, 1), FP64_SNAN_V(0, FP64_FRAC_NORM_MIN), FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_SNAN_V(0, FP64_FRAC_V2) } }, 5546 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 5547 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN | X86_MXCSR_IE, 5548 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN | X86_MXCSR_IE, 5549 /*xcpt? */ true, true }, 5550 { { /*src2 */ { FP64_QNAN_V(0, FP64_FRAC_V1), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V0), FP64_QNAN_V(0, FP64_FRAC_V1) } }, 5551 { /*src1 */ { FP64_SNAN_V(0, FP64_FRAC_V2), FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V2) } }, 5552 { /* => */ { FP64_SNAN_V(0, FP64_FRAC_V2), FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V2) } }, 5553 /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, 5554 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, 5555 /*256:out */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, 5556 /*xcpt? */ false, false }, 5557 /* SNan, QNan (Unmasked). */ 5558 { { /*src2 */ { FP64_SNAN(0), FP64_SNAN_V(0, FP64_FRAC_NORM_MIN), FP64_SNAN_V(0, FP64_FRAC_V1), FP64_SNAN_V(0, FP64_FRAC_V1) } }, 5559 { /*src1 */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V3), FP64_QNAN_V(0, FP64_FRAC_V2) } }, 5560 { /* => */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V3), FP64_QNAN_V(0, FP64_FRAC_V2) } }, 5561 /*mxcsr:in */ X86_MXCSR_DAZ, 5562 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_IE, 5563 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_IE, 5564 /*xcpt? */ true, true }, 5565 { { /*src2 */ { FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_SNAN_V(0, FP64_FRAC_V1), FP64_SNAN_V(1, FP64_FRAC_V1) } }, 5566 { /*src1 */ { FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(1, FP64_FRAC_V2), FP64_QNAN_V(1, FP64_FRAC_V0) } }, 5567 { /* => */ { FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(1, FP64_FRAC_V2), FP64_QNAN_V(1, FP64_FRAC_V0) } }, 5568 /*mxcsr:in */ X86_MXCSR_RC_UP, 5569 /*128:out */ X86_MXCSR_RC_UP, 5570 /*256:out */ X86_MXCSR_RC_UP, 5571 /*xcpt? */ false, false }, 5572 { { /*src2 */ { FP64_SNAN_V(0, FP64_FRAC_V0), FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_SNAN_V(0, FP64_FRAC_V1), FP64_SNAN_V(1, FP64_FRAC_V1) } }, 5573 { /*src1 */ { FP64_QNAN_V(0, FP64_FRAC_V3), FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(1, FP64_FRAC_V2), FP64_QNAN_V(1, FP64_FRAC_V3) } }, 5574 { /* => */ { FP64_QNAN_V(0, FP64_FRAC_V3), FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(1, FP64_FRAC_V2), FP64_QNAN_V(1, FP64_FRAC_V3) } }, 5575 /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 5576 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 5577 /*256:out */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 5578 /*xcpt? */ false, false }, 5579 /* SNan, SNan (Unmasked). */ 5580 /*55*/{ { /*src2 */ { FP64_SNAN(0), FP64_SNAN_V(0, FP64_FRAC_NORM_MIN), FP64_SNAN_V(0, FP64_FRAC_V1), FP64_SNAN_V(0, FP64_FRAC_V2) } }, 5581 { /*src1 */ { FP64_SNAN(0), FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_SNAN_V(0, FP64_FRAC_V2), FP64_SNAN_V(1, FP64_FRAC_V0) } }, 5582 { /* => */ { FP64_QNAN_V(0, 1), FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_SNAN_V(0, FP64_FRAC_V2), FP64_SNAN_V(1, FP64_FRAC_V0) } }, 5583 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ, 5584 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_IE, 5585 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_IE, 5586 /*xcpt? */ true, true }, 5587 { { /*src2 */ { FP64_SNAN_V(0, FP64_FRAC_NORM_MIN), FP64_SNAN_V(0, FP64_FRAC_V2), FP64_SNAN_V(0, FP64_FRAC_V1), FP64_SNAN_V(1, FP32_FRAC_V2) } }, 5588 { /*src1 */ { FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_SNAN_V(0, FP64_FRAC_V0), FP64_SNAN_V(1, FP64_FRAC_V2), FP64_SNAN_V(1, FP32_FRAC_V3) } }, 5589 { /* => */ { FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_SNAN_V(0, FP64_FRAC_V0), FP64_SNAN_V(1, FP64_FRAC_V2), FP64_SNAN_V(1, FP32_FRAC_V3) } }, 5590 /*mxcsr:in */ X86_MXCSR_RC_ZERO, 5591 /*128:out */ X86_MXCSR_RC_ZERO | X86_MXCSR_IE, 5592 /*256:out */ X86_MXCSR_RC_ZERO | X86_MXCSR_IE, 5593 /*xcpt? */ true, true }, 5594 { { /*src2 */ { FP64_SNAN_V(0, FP64_FRAC_V1), FP64_SNAN_V(0, FP64_FRAC_V2), FP64_SNAN_V(1, FP64_FRAC_V0), FP64_SNAN_V(0, FP64_FRAC_V2) } }, 5595 { /*src1 */ { FP64_SNAN_V(0, FP64_FRAC_V2), FP64_SNAN_V(1, FP64_FRAC_V3), FP64_SNAN_V(1, FP64_FRAC_V3), FP64_SNAN_V(0, FP64_FRAC_V3) } }, 5596 { /* => */ { FP64_QNAN_V(0, FP64_FRAC_V2), FP64_SNAN_V(1, FP64_FRAC_V3), FP64_SNAN_V(1, FP64_FRAC_V3), FP64_SNAN_V(0, FP64_FRAC_V3) } }, 5597 /*mxcsr:in */ 0, 5598 /*128:out */ 0, 5599 /*256:out */ 0, 5600 /*xcpt? */ false, false }, 5601 /* QNan, Norm FP (Unmasked). */ 5602 { { /*src2 */ { FP64_QNAN(0), FP64_QNAN_V(1, FP64_FRAC_NORM_MAX), FP64_NORM_V0(1), FP64_QNAN_V(0, FP64_FRAC_V1) } }, 5603 { /*src1 */ { FP64_1(0), FP64_INF(1), FP64_QNAN_V(1, FP64_FRAC_V0), FP64_NORM_V2(1) } }, 5604 { /* => */ { FP64_QNAN(0), FP64_INF(1), FP64_QNAN_V(1, FP64_FRAC_V0), FP64_NORM_V2(1) } }, 5605 /*mxcsr:in */ X86_MXCSR_FZ, 5606 /*128:out */ X86_MXCSR_FZ, 5607 /*256:out */ X86_MXCSR_FZ, 5608 /*xcpt? */ false, false }, 5609 /* SNan, Norm FP (Unmasked). */ 5610 /*59*/{ { /*src2 */ { FP64_SNAN(1), FP64_SNAN_V(1, FP64_FRAC_NORM_MAX), FP64_NORM_V0(1), FP64_SNAN_V(0, FP64_FRAC_V1) } }, 5611 { /*src1 */ { FP64_1(0), FP64_INF(0), FP64_SNAN_V(1, FP64_FRAC_V0), FP64_NORM_V2(1) } }, 5612 { /* => */ { FP64_QNAN_V(1, 1), FP64_INF(0), FP64_SNAN_V(1, FP64_FRAC_V0), FP64_NORM_V2(1) } }, 5613 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, 5614 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE, 5615 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE, 5616 /*xcpt? */ true, true }, 5617 /** @todo Underflow, Precision; Rounding, FZ etc. */ 5272 /*32*/ BS3CPUINSTR4_SD_INVALIDS 5273 /** @todo Underflow; Precision; Rounding; FZ etc. */ 5618 5274 }; 5619 5275 … … 5917 5573 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_UP, 5918 5574 /*xcpt? */ false, false }, 5919 /** @todo Denormals; Rounding, FZ etc. */5575 /** @todo More Denormals. */ 5920 5576 /* 5921 5577 * Invalids. 5922 5578 */ 5923 /*32*/{ { /*src2 */ { FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_V0), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V5) } }, 5924 { /*src1 */ { FP32_QNAN(0), FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4) } }, 5925 { /* => */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V0), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3) } }, 5926 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 5927 /*128:out */ X86_MXCSR_XCPT_MASK, 5928 /*256:out */ X86_MXCSR_XCPT_MASK, 5929 /*xcpt? */ false, false }, 5930 { { /*src2 */ { FP32_QNAN(0), FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V5) } }, 5931 { /*src1 */ { FP32_QNAN(0), FP32_SNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V4) } }, 5932 { /* => */ { FP32_QNAN(0), FP32_QNAN(0), FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V4) } }, 5933 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 5934 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, 5935 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, 5936 /*xcpt? */ false, false }, 5937 { { /*src2 */ { FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V6) } }, 5938 { /*src1 */ { FP32_SNAN(0), FP32_QNAN(0), FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1) } }, 5939 { /* => */ { FP32_QNAN_V(0, 1), FP32_QNAN_V(0, 1), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V5) } }, 5940 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 5941 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, 5942 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, 5943 /*xcpt? */ false, false }, 5944 { { /*src2 */ { FP32_SNAN(0), FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_V7), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V1) } }, 5945 { /*src1 */ { FP32_SNAN(0), FP32_SNAN(0), FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2) } }, 5946 { /* => */ { FP32_QNAN_V(0, 1), FP32_QNAN_V(0, 1), FP32_QNAN_V(0, 1), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V7), FP32_QNAN_V(0, FP32_FRAC_V6) } }, 5947 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 5948 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, 5949 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, 5950 /*xcpt? */ false, false }, 5951 { { /*src2 */ { FP32_QNAN(0), FP32_NORM_V1(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_NORM_V3(1), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_NORM_V5(1) } }, 5952 { /*src1 */ { FP32_QNAN(0), FP32_1(1), FP32_QNAN_V(1, FP32_FRAC_NORM_MAX), FP32_NORM_V2(1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_NORM_V4(0), FP32_QNAN_V(1, FP32_FRAC_V4), FP32_NORM_V6(1) } }, 5953 { /* => */ { FP32_QNAN(0), FP32_QNAN_V(1, FP32_FRAC_NORM_MAX), FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(1, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V5) } }, 5954 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 5955 /*128:out */ X86_MXCSR_XCPT_MASK, 5956 /*256:out */ X86_MXCSR_XCPT_MASK, 5957 /*xcpt? */ false, false }, 5958 { { /*src2 */ { FP32_SNAN_V(1, FP32_FRAC_NORM_MAX), FP32_1(0), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_NORM_V3(0), FP32_SNAN_V(0, FP32_FRAC_V0), FP32_NORM_V3(1), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_NORM_V7(1) } }, 5959 { /*src1 */ { FP32_SNAN(0), FP32_1(1), FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_NORM_V2(1), FP32_SNAN_V(1, FP32_FRAC_V2), FP32_NORM_V4(0), FP32_SNAN_V(1, FP32_FRAC_V4), FP32_NORM_V6(1) } }, 5960 { /* => */ { FP32_QNAN_V(0, 1), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(1, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(1, FP32_FRAC_V2), FP32_QNAN_V(1, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V0), FP32_QNAN_V(0, FP32_FRAC_V6) } }, 5961 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 5962 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, 5963 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, 5964 /*xcpt? */ false, false }, 5965 { { /*src2 */ { FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_V0), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V5) } }, 5966 { /*src1 */ { FP32_QNAN(0), FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4) } }, 5967 { /* => */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V0), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3) } }, 5968 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, 5969 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, 5970 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, 5971 /*xcpt? */ false, false }, 5972 { { /*src2 */ { FP32_QNAN(0), FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V5) } }, 5973 { /*src1 */ { FP32_QNAN(0), FP32_SNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V4) } }, 5974 { /* => */ { FP32_QNAN(0), FP32_QNAN(0), FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V4) } }, 5975 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_RC_UP, 5976 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_UP | X86_MXCSR_IE, 5977 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_UP | X86_MXCSR_IE, 5978 /*xcpt? */ true, true }, 5979 { { /*src2 */ { FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V6) } }, 5980 { /*src1 */ { FP32_SNAN(0), FP32_QNAN(0), FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1) } }, 5981 { /* => */ { FP32_QNAN_V(0, 1), FP32_QNAN_V(0, 1), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V5) } }, 5982 /*mxcsr:in */ 0, 5983 /*128:out */ X86_MXCSR_IE, 5984 /*256:out */ X86_MXCSR_IE, 5985 /*xcpt? */ true, true }, 5986 { { /*src2 */ { FP32_SNAN(0), FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_V7), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V1) } }, 5987 { /*src1 */ { FP32_SNAN(0), FP32_SNAN(0), FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2) } }, 5988 { /* => */ { FP32_QNAN_V(0, 1), FP32_QNAN_V(0, 1), FP32_QNAN_V(0, 1), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V7), FP32_QNAN_V(0, FP32_FRAC_V6) } }, 5989 /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_UP, 5990 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_UP | X86_MXCSR_IE, 5991 /*256:out */ X86_MXCSR_FZ | X86_MXCSR_RC_UP | X86_MXCSR_IE, 5992 /*xcpt? */ true, true }, 5993 { { /*src2 */ { FP32_QNAN(0), FP32_NORM_V1(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_NORM_V3(1), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_NORM_V5(1) } }, 5994 { /*src1 */ { FP32_QNAN(0), FP32_1(1), FP32_QNAN_V(1, FP32_FRAC_NORM_MAX), FP32_NORM_V2(1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_NORM_V4(0), FP32_QNAN_V(1, FP32_FRAC_V4), FP32_NORM_V6(1) } }, 5995 { /* => */ { FP32_QNAN(0), FP32_QNAN_V(1, FP32_FRAC_NORM_MAX), FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(1, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V5) } }, 5996 /*mxcsr:in */ 0, 5997 /*128:out */ 0, 5998 /*256:out */ 0, 5999 /*xcpt? */ false, false }, 6000 { { /*src2 */ { FP32_SNAN_V(1, FP32_FRAC_NORM_MAX), FP32_1(0), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_NORM_V3(0), FP32_SNAN_V(0, FP32_FRAC_V0), FP32_NORM_V3(1), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_NORM_V7(1) } }, 6001 { /*src1 */ { FP32_SNAN(0), FP32_1(1), FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_NORM_V2(1), FP32_SNAN_V(1, FP32_FRAC_V2), FP32_NORM_V4(0), FP32_SNAN_V(1, FP32_FRAC_V4), FP32_NORM_V6(1) } }, 6002 { /* => */ { FP32_QNAN_V(0, 1), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(1, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(1, FP32_FRAC_V2), FP32_QNAN_V(1, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V0), FP32_QNAN_V(0, FP32_FRAC_V6) } }, 6003 /*mxcsr:in */ X86_MXCSR_RC_UP, 6004 /*128:out */ X86_MXCSR_RC_UP|X86_MXCSR_IE, 6005 /*256:out */ X86_MXCSR_RC_UP|X86_MXCSR_IE, 6006 /*xcpt? */ true, true }, 6007 /** @todo Underflow, Precision; Rounding, FZ etc. */ 5579 /*32*/ BS3CPUINSTR4_H_PS_INVALIDS 5580 /** @todo Underflow; Precision; Rounding; FZ etc. */ 6008 5581 }; 6009 5582 … … 6268 5841 * Invalids. 6269 5842 */ 6270 /*27*/{ { /*src2 */ { FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(0, FP64_FRAC_V0), FP64_QNAN_V(0, FP64_FRAC_V1) } }, 6271 { /*src1 */ { FP64_QNAN(0), FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX) } }, 6272 { /* => */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(0, FP64_FRAC_V0) } }, 6273 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 6274 /*128:out */ X86_MXCSR_XCPT_MASK, 6275 /*256:out */ X86_MXCSR_XCPT_MASK, 6276 /*xcpt? */ false, false }, 6277 { { /*src2 */ { FP64_QNAN(0), FP64_SNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V1) } }, 6278 { /*src1 */ { FP64_QNAN(0), FP64_SNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_SNAN_V(0, FP64_FRAC_V2) } }, 6279 { /* => */ { FP64_QNAN(0), FP64_QNAN(0), FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX) } }, 6280 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 6281 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, 6282 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, 6283 /*xcpt? */ false, false }, 6284 { { /*src2 */ { FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V2), FP64_SNAN_V(0, FP64_FRAC_V1), FP64_QNAN_V(0, FP64_FRAC_V2) } }, 6285 { /*src1 */ { FP64_SNAN(0), FP64_QNAN(0), FP64_SNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(0, FP64_FRAC_V3) } }, 6286 { /* => */ { FP64_QNAN_V(0, 1), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, 1), FP64_QNAN_V(0, FP64_FRAC_V1) } }, 6287 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 6288 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, 6289 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, 6290 /*xcpt? */ false, false }, 6291 { { /*src2 */ { FP64_SNAN(0), FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_SNAN_V(0, FP64_FRAC_NORM_MIN) } }, 6292 { /*src1 */ { FP64_SNAN(0), FP64_SNAN(0), FP64_SNAN_V(0, FP64_FRAC_NORM_MIN), FP64_SNAN_V(0, FP64_FRAC_NORM_MAX) } }, 6293 { /* => */ { FP64_QNAN_V(0, 1), FP64_QNAN_V(0, 1), FP64_QNAN_V(0, 1), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX) } }, 6294 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 6295 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, 6296 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, 6297 /*xcpt? */ false, false }, 6298 { { /*src2 */ { FP64_QNAN(0), FP64_NORM_V1(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V1) } }, 6299 { /*src1 */ { FP64_QNAN(0), FP64_1(1), FP64_QNAN_V(1, FP64_FRAC_NORM_MAX), FP64_NORM_V2(1) } }, 6300 { /* => */ { FP64_QNAN(0), FP64_QNAN(0), FP64_QNAN_V(1, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX) } }, 6301 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 6302 /*128:out */ X86_MXCSR_XCPT_MASK, 6303 /*256:out */ X86_MXCSR_XCPT_MASK, 6304 /*xcpt? */ false, false }, 6305 { { /*src2 */ { FP64_SNAN_V(1, FP64_FRAC_NORM_MAX), FP64_1(0), FP64_SNAN_V(0, FP64_FRAC_V1), FP64_NORM_V3(0) } }, 6306 { /*src1 */ { FP64_SNAN(0), FP64_1(1), FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_NORM_V2(1) } }, 6307 { /* => */ { FP64_QNAN_V(0, 1), FP64_QNAN_V(1, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V1) } }, 6308 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 6309 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, 6310 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, 6311 /*xcpt? */ false, false }, 6312 { { /*src2 */ { FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(0, FP64_FRAC_V0), FP64_QNAN_V(0, FP64_FRAC_V1) } }, 6313 { /*src1 */ { FP64_QNAN(0), FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX) } }, 6314 { /* => */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(0, FP64_FRAC_V0) } }, 6315 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, 6316 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, 6317 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, 6318 /*xcpt? */ false, false }, 6319 { { /*src2 */ { FP64_QNAN(0), FP64_SNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V1) } }, 6320 { /*src1 */ { FP64_QNAN(0), FP64_SNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_SNAN_V(0, FP64_FRAC_V2) } }, 6321 { /* => */ { FP64_QNAN(0), FP64_QNAN(0), FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX) } }, 6322 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_RC_UP, 6323 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_UP | X86_MXCSR_IE, 6324 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_UP | X86_MXCSR_IE, 6325 /*xcpt? */ true, true }, 6326 { { /*src2 */ { FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V2), FP64_SNAN_V(0, FP64_FRAC_V1), FP64_QNAN_V(0, FP64_FRAC_V2) } }, 6327 { /*src1 */ { FP64_SNAN(0), FP64_QNAN(0), FP64_SNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(0, FP64_FRAC_V3) } }, 6328 { /* => */ { FP64_QNAN_V(0, 1), FP64_QNAN_V(0, 1), FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(0, FP64_FRAC_V1) } }, 6329 /*mxcsr:in */ 0, 6330 /*128:out */ X86_MXCSR_IE, 6331 /*256:out */ X86_MXCSR_IE, 6332 /*xcpt? */ true, true }, 6333 { { /*src2 */ { FP64_SNAN(0), FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_SNAN_V(0, FP64_FRAC_NORM_MIN) } }, 6334 { /*src1 */ { FP64_SNAN(0), FP64_SNAN(0), FP64_SNAN_V(0, FP64_FRAC_NORM_MIN), FP64_SNAN_V(0, FP64_FRAC_NORM_MAX) } }, 6335 { /* => */ { FP64_QNAN_V(0, 1), FP64_QNAN_V(0, 1), FP64_QNAN_V(0, 1), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX) } }, 6336 /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_UP, 6337 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_UP | X86_MXCSR_IE, 6338 /*256:out */ X86_MXCSR_FZ | X86_MXCSR_RC_UP | X86_MXCSR_IE, 6339 /*xcpt? */ true, true }, 6340 { { /*src2 */ { FP64_QNAN(0), FP64_NORM_V1(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V1) } }, 6341 { /*src1 */ { FP64_QNAN(0), FP64_1(1), FP64_QNAN_V(1, FP64_FRAC_NORM_MAX), FP64_NORM_V2(1) } }, 6342 { /* => */ { FP64_QNAN(0), FP64_QNAN(0), FP64_QNAN_V(1, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX) } }, 6343 /*mxcsr:in */ 0, 6344 /*128:out */ 0, 6345 /*256:out */ 0, 6346 /*xcpt? */ false, false }, 6347 { { /*src2 */ { FP64_SNAN_V(1, FP64_FRAC_NORM_MAX), FP64_1(0), FP64_SNAN_V(0, FP64_FRAC_V1), FP64_NORM_V3(0) } }, 6348 { /*src1 */ { FP64_SNAN(0), FP64_1(1), FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_NORM_V2(1) } }, 6349 { /* => */ { FP64_QNAN_V(0, 1), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(1, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V1) } }, 6350 /*mxcsr:in */ X86_MXCSR_RC_UP, 6351 /*128:out */ X86_MXCSR_RC_UP|X86_MXCSR_IE, 6352 /*256:out */ X86_MXCSR_RC_UP|X86_MXCSR_IE, 6353 /*xcpt? */ true, true }, 6354 /** @todo Underflow, Precision; Rounding, FZ etc. */ 5843 /*27*/ BS3CPUINSTR4_H_PD_INVALIDS 5844 /** @todo Underflow; Precision; Rounding; FZ etc. */ 6355 5845 }; 6356 5846 … … 6712 6202 * Invalids. 6713 6203 */ 6714 /*40*/{ { /*src2 */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V0), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V5) } }, 6715 { /*src1 */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4) } }, 6716 { /* => */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4) } }, 6717 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 6718 /*128:out */ X86_MXCSR_XCPT_MASK, 6719 /*256:out */ X86_MXCSR_XCPT_MASK, 6720 /*xcpt? */ false, false }, 6721 { { /*src2 */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V0), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V5) } }, 6722 { /*src1 */ { FP32_SNAN(0), FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V4) } }, 6723 { /* => */ { FP32_QNAN_V(0, 1), FP32_QNAN_V(0, 1), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4) } }, 6724 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 6725 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, 6726 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, 6727 /*xcpt? */ false, false }, 6728 { { /*src2 */ { FP32_SNAN(0), FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V6) } }, 6729 { /*src1 */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1) } }, 6730 { /* => */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1) } }, 6731 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ, 6732 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_IE, 6733 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_IE, 6734 /*xcpt? */ false, false }, 6735 { { /*src2 */ { FP32_SNAN(0), FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V7), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V1) } }, 6736 { /*src1 */ { FP32_SNAN(0), FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2) } }, 6737 { /* => */ { FP32_QNAN_V(0, 1), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2) } }, 6738 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 6739 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, 6740 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, 6741 /*xcpt? */ false, false }, 6742 { { /*src2 */ { FP32_QNAN(0), FP32_QNAN_V(1, FP32_FRAC_NORM_MAX), FP32_NORM_V0(1), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_NORM_V3(0), FP32_QNAN_V(1, FP32_FRAC_V3), FP32_NORM_V5(0), FP32_QNAN_V(1, FP32_FRAC_V5) } }, 6743 { /*src1 */ { FP32_1(0), FP32_1(1), FP32_QNAN_V(1, FP32_FRAC_V0), FP32_NORM_V2(1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_NORM_V4(0), FP32_QNAN_V(1, FP32_FRAC_V4), FP32_NORM_V6(1) } }, 6744 { /* => */ { FP32_QNAN(0), FP32_QNAN_V(1, FP32_FRAC_NORM_MAX), FP32_QNAN_V(1, FP32_FRAC_V0), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(1, FP32_FRAC_V3), FP32_QNAN_V(1, FP32_FRAC_V4), FP32_QNAN_V(1, FP32_FRAC_V5) } }, 6745 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_XCPT_FLAGS, 6746 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_XCPT_FLAGS, 6747 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_XCPT_FLAGS, 6748 /*xcpt? */ false, false }, 6749 { { /*src2 */ { FP32_SNAN(1), FP32_SNAN_V(1, FP32_FRAC_NORM_MAX), FP32_NORM_V0(1), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_NORM_V3(0), FP32_SNAN_V(1, FP32_FRAC_V3), FP32_NORM_V5(0), FP32_SNAN_V(1, FP32_FRAC_V5) } }, 6750 { /*src1 */ { FP32_1(0), FP32_1(0), FP32_SNAN_V(1, FP32_FRAC_V0), FP32_NORM_V2(1), FP32_SNAN_V(1, FP32_FRAC_V2), FP32_NORM_V4(0), FP32_SNAN_V(1, FP32_FRAC_V4), FP32_NORM_V6(1) } }, 6751 { /* => */ { FP32_QNAN_V(1, 1), FP32_QNAN_V(1, FP32_FRAC_NORM_MAX), FP32_QNAN_V(1, FP32_FRAC_V0), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(1, FP32_FRAC_V2), FP32_QNAN_V(1, FP32_FRAC_V3), FP32_QNAN_V(1, FP32_FRAC_V4), FP32_QNAN_V(1, FP32_FRAC_V5) } }, 6752 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 6753 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, 6754 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, 6755 /*xcpt? */ false, false }, 6756 { { /*src2 */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V0), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V5) } }, 6757 { /*src1 */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4) } }, 6758 { /* => */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4) } }, 6759 /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 6760 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 6761 /*256:out */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 6762 /*xcpt? */ false, false }, 6763 { { /*src2 */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V0), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V5) } }, 6764 { /*src1 */ { FP32_SNAN(0), FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V4) } }, 6765 { /* => */ { FP32_QNAN_V(0, 1), FP32_QNAN_V(0, 1), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4) } }, 6766 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, 6767 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE, 6768 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE, 6769 /*xcpt? */ true, true }, 6770 { { /*src2 */ { FP32_SNAN(0), FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V6) } }, 6771 { /*src1 */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1) } }, 6772 { /* => */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1) } }, 6773 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP, 6774 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP | X86_MXCSR_IE, 6775 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP | X86_MXCSR_IE, 6776 /*xcpt? */ true, true }, 6777 { { /*src2 */ { FP32_SNAN(0), FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V7), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V1) } }, 6778 { /*src1 */ { FP32_SNAN(0), FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2) } }, 6779 { /* => */ { FP32_QNAN_V(0, 1), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2) } }, 6780 /*mxcsr:in */ X86_MXCSR_RC_UP, 6781 /*128:out */ X86_MXCSR_RC_UP | X86_MXCSR_IE, 6782 /*256:out */ X86_MXCSR_RC_UP | X86_MXCSR_IE, 6783 /*xcpt? */ true, true }, 6784 { { /*src2 */ { FP32_QNAN(0), FP32_QNAN_V(1, FP32_FRAC_NORM_MAX), FP32_NORM_V0(1), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_NORM_V3(0), FP32_QNAN_V(1, FP32_FRAC_V3), FP32_NORM_V5(0), FP32_QNAN_V(1, FP32_FRAC_V5) } }, 6785 { /*src1 */ { FP32_1(0), FP32_1(1), FP32_QNAN_V(1, FP32_FRAC_V0), FP32_NORM_V2(1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_NORM_V4(0), FP32_QNAN_V(1, FP32_FRAC_V4), FP32_NORM_V6(1) } }, 6786 { /* => */ { FP32_QNAN(0), FP32_QNAN_V(1, FP32_FRAC_NORM_MAX), FP32_QNAN_V(1, FP32_FRAC_V0), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(1, FP32_FRAC_V3), FP32_QNAN_V(1, FP32_FRAC_V4), FP32_QNAN_V(1, FP32_FRAC_V5) } }, 6787 /*mxcsr:in */ 0, 6788 /*128:out */ 0, 6789 /*256:out */ 0, 6790 /*xcpt? */ false, false }, 6791 { { /*src2 */ { FP32_SNAN(1), FP32_SNAN_V(1, FP32_FRAC_NORM_MAX), FP32_NORM_V0(1), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_NORM_V3(0), FP32_SNAN_V(1, FP32_FRAC_V3), FP32_NORM_V5(0), FP32_SNAN_V(1, FP32_FRAC_V5) } }, 6792 { /*src1 */ { FP32_1(0), FP32_1(0), FP32_SNAN_V(1, FP32_FRAC_V0), FP32_NORM_V2(1), FP32_SNAN_V(1, FP32_FRAC_V2), FP32_NORM_V4(0), FP32_SNAN_V(1, FP32_FRAC_V4), FP32_NORM_V6(1) } }, 6793 { /* => */ { FP32_QNAN_V(1, 1), FP32_QNAN_V(1, FP32_FRAC_NORM_MAX), FP32_QNAN_V(1, FP32_FRAC_V0), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(1, FP32_FRAC_V2), FP32_QNAN_V(1, FP32_FRAC_V3), FP32_QNAN_V(1, FP32_FRAC_V4), FP32_QNAN_V(1, FP32_FRAC_V5) } }, 6794 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO, 6795 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE, 6796 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE, 6797 /*xcpt? */ true, true }, 6798 /** @todo Underflow, Precision; Rounding, FZ etc. */ 6204 /*40*/ BS3CPUINSTR4_PS_INVALIDS 6205 /** @todo Underflow, Precision; Rounding; FZ etc. */ 6799 6206 }; 6800 6207 … … 7105 6512 * Invalids. 7106 6513 */ 7107 /*33*/{ { /*src2 */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V0), FP64_QNAN_V(0, FP64_FRAC_V1) } }, 7108 { /*src1 */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V2) } }, 7109 { /* => */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V2) } }, 7110 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 7111 /*128:out */ X86_MXCSR_XCPT_MASK, 7112 /*256:out */ X86_MXCSR_XCPT_MASK, 7113 /*xcpt? */ false, false }, 7114 { { /*src2 */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V0), FP64_QNAN_V(0, FP64_FRAC_V2) } }, 7115 { /*src1 */ { FP64_SNAN(0), FP64_SNAN_V(0, FP64_FRAC_NORM_MIN), FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_SNAN_V(0, FP64_FRAC_V1) } }, 7116 { /* => */ { FP64_QNAN_V(0, 1), FP64_QNAN_V(0, 1), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V1) } }, 7117 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 7118 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, 7119 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, 7120 /*xcpt? */ false, false }, 7121 { { /*src2 */ { FP64_SNAN(0), FP64_SNAN_V(0, FP64_FRAC_NORM_MIN), FP64_SNAN_V(0, FP64_FRAC_V0), FP64_SNAN_V(0, FP64_FRAC_V1) } }, 7122 { /*src1 */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V2), FP64_QNAN_V(0, FP64_FRAC_V3) } }, 7123 { /* => */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V2), FP64_QNAN_V(0, FP64_FRAC_V3) } }, 7124 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 7125 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, 7126 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, 7127 /*xcpt? */ false, false }, 7128 { { /*src2 */ { FP64_SNAN(0), FP64_SNAN_V(0, FP64_FRAC_NORM_MIN), FP64_SNAN_V(0, FP64_FRAC_V1), FP64_SNAN_V(0, FP64_FRAC_V2) } }, 7129 { /*src1 */ { FP64_SNAN(0), FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_SNAN_V(0, FP64_FRAC_V3), FP64_SNAN_V(0, FP64_FRAC_V0) } }, 7130 { /* => */ { FP64_QNAN_V(0, 1), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V3), FP64_QNAN_V(0, FP64_FRAC_V0) } }, 7131 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 7132 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, 7133 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, 7134 /*xcpt? */ false, false }, 7135 { { /*src2 */ { FP64_QNAN(0), FP64_QNAN_V(1, FP64_FRAC_NORM_MAX), FP64_NORM_V0(1), FP64_QNAN_V(0, FP64_FRAC_V1) } }, 7136 { /*src1 */ { FP64_1(0), FP64_1(1), FP64_QNAN_V(1, FP64_FRAC_V0), FP64_NORM_V2(1) } }, 7137 { /* => */ { FP64_QNAN(0), FP64_QNAN_V(1, FP64_FRAC_NORM_MAX), FP64_QNAN_V(1, FP64_FRAC_V0), FP64_QNAN_V(0, FP64_FRAC_V1) } }, 7138 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 7139 /*128:out */ X86_MXCSR_XCPT_MASK, 7140 /*256:out */ X86_MXCSR_XCPT_MASK, 7141 /*xcpt? */ false, false }, 7142 { { /*src2 */ { FP64_SNAN(1), FP64_SNAN_V(1, FP64_FRAC_NORM_MAX), FP64_NORM_V0(1), FP64_SNAN_V(0, FP64_FRAC_V1) } }, 7143 { /*src1 */ { FP64_1(0), FP64_1(0), FP64_SNAN_V(1, FP64_FRAC_V0), FP64_NORM_V2(1) } }, 7144 { /* => */ { FP64_QNAN_V(1, 1), FP64_QNAN_V(1, FP64_FRAC_NORM_MAX), FP64_QNAN_V(1, FP64_FRAC_V0), FP64_QNAN_V(0, FP64_FRAC_V1) } }, 7145 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 7146 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, 7147 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, 7148 /*xcpt? */ false, false }, 7149 { { /*src2 */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V0), FP64_QNAN_V(0, FP64_FRAC_V2) } }, 7150 { /*src1 */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V3) } }, 7151 { /* => */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V3) } }, 7152 /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 7153 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 7154 /*256:out */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 7155 /*xcpt? */ false, false }, 7156 { { /*src2 */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V0), FP64_QNAN_V(0, FP32_FRAC_V1) } }, 7157 { /*src1 */ { FP64_SNAN(0), FP64_SNAN_V(0, FP64_FRAC_NORM_MIN), FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_SNAN_V(0, FP32_FRAC_V2) } }, 7158 { /* => */ { FP64_QNAN_V(0, 1), FP64_QNAN_V(0, 1), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP32_FRAC_V2) } }, 7159 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, 7160 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE, 7161 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE, 7162 /*xcpt? */ true, true }, 7163 { { /*src2 */ { FP64_SNAN(0), FP64_SNAN_V(0, FP64_FRAC_NORM_MIN), FP64_SNAN_V(0, FP64_FRAC_V1), FP64_SNAN_V(0, FP64_FRAC_V1) } }, 7164 { /*src1 */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V3), FP64_QNAN_V(0, FP64_FRAC_V2) } }, 7165 { /* => */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V3), FP64_QNAN_V(0, FP64_FRAC_V2) } }, 7166 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, 7167 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE, 7168 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE, 7169 /*xcpt? */ true, true }, 7170 { { /*src2 */ { FP64_SNAN(0), FP64_SNAN_V(0, FP64_FRAC_NORM_MIN), FP64_SNAN_V(0, FP64_FRAC_V1), FP64_SNAN_V(0, FP64_FRAC_V2) } }, 7171 { /*src1 */ { FP64_SNAN(0), FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_SNAN_V(0, FP64_FRAC_V0), FP64_SNAN_V(0, FP64_FRAC_V3) } }, 7172 { /* => */ { FP64_QNAN_V(0, 1), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V0), FP64_QNAN_V(0, FP64_FRAC_V3) } }, 7173 /*mxcsr:in */ X86_MXCSR_RC_UP, 7174 /*128:out */ X86_MXCSR_RC_UP | X86_MXCSR_IE, 7175 /*256:out */ X86_MXCSR_RC_UP | X86_MXCSR_IE, 7176 /*xcpt? */ true, true }, 7177 { { /*src2 */ { FP64_QNAN(0), FP64_QNAN_V(1, FP64_FRAC_NORM_MAX), FP64_NORM_V0(1), FP64_QNAN_V(0, FP64_FRAC_V1) } }, 7178 { /*src1 */ { FP64_1(0), FP64_1(1), FP64_QNAN_V(1, FP64_FRAC_V3), FP64_NORM_V2(1) } }, 7179 { /* => */ { FP64_QNAN(0), FP64_QNAN_V(1, FP64_FRAC_NORM_MAX), FP64_QNAN_V(1, FP64_FRAC_V3), FP64_QNAN_V(0, FP64_FRAC_V1) } }, 7180 /*mxcsr:in */ X86_MXCSR_RC_DOWN, 7181 /*128:out */ X86_MXCSR_RC_DOWN, 7182 /*256:out */ X86_MXCSR_RC_DOWN, 7183 /*xcpt? */ false, false }, 7184 { { /*src2 */ { FP64_SNAN(1), FP64_SNAN_V(1, FP64_FRAC_NORM_MAX), FP64_NORM_V0(1), FP64_SNAN_V(0, FP64_FRAC_V2) } }, 7185 { /*src1 */ { FP64_1(0), FP64_1(0), FP64_SNAN_V(1, FP64_FRAC_V3), FP64_NORM_V2(1) } }, 7186 { /* => */ { FP64_QNAN_V(1, 1), FP64_QNAN_V(1, FP64_FRAC_NORM_MAX), FP64_QNAN_V(1, FP64_FRAC_V3), FP64_QNAN_V(0, FP64_FRAC_V2) } }, 7187 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO, 7188 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE, 7189 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE, 7190 /*xcpt? */ true, true }, 7191 /** @todo Underflow, Precision; Rounding, FZ etc. */ 6514 /*33*/ BS3CPUINSTR4_PD_INVALIDS 6515 /** @todo Underflow, Precision; Rounding; FZ etc. */ 7192 6516 }; 7193 6517 … … 7461 6785 * Invalids. 7462 6786 */ 7463 /* QNan, QNan (Masked). */ 7464 /*28*/{ { /*src2 */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V0), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V5) } }, 7465 { /*src1 */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4) } }, 7466 { /* => */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4) } }, 7467 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 7468 /*128:out */ X86_MXCSR_XCPT_MASK, 7469 /*256:out */ X86_MXCSR_XCPT_MASK, 7470 /*xcpt? */ false, false }, 7471 { { /*src2 */ { FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4) } }, 7472 { /*src1 */ { FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V1) } }, 7473 { /* => */ { FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V1) } }, 7474 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 7475 /*128:out */ X86_MXCSR_XCPT_MASK, 7476 /*256:out */ X86_MXCSR_XCPT_MASK, 7477 /*xcpt? */ false, false }, 7478 { { /*src2 */ { FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4) } }, 7479 { /*src1 */ { FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V1) } }, 7480 { /* => */ { FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V1) } }, 7481 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 7482 /*128:out */ X86_MXCSR_XCPT_MASK, 7483 /*256:out */ X86_MXCSR_XCPT_MASK, 7484 /*xcpt? */ false, false }, 7485 /* QNan, SNan (Masked). */ 7486 { { /*src2 */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4) } }, 7487 { /*src1 */ { FP32_SNAN(0), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V1) } }, 7488 { /* => */ { FP32_QNAN_V(0, 1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V1) } }, 7489 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 7490 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, 7491 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, 7492 /*xcpt? */ false, false }, 7493 { { /*src2 */ { FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V0), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V5) } }, 7494 { /*src1 */ { FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V4) } }, 7495 { /* => */ { FP32_QNAN_V(0, 1), FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V4) } }, 7496 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 7497 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, 7498 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, 7499 /*xcpt? */ false, false }, 7500 { { /*src2 */ { FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V0), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V5) } }, 7501 { /*src1 */ { FP32_SNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4) } }, 7502 { /* => */ { FP32_SNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4) } }, 7503 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 7504 /*128:out */ X86_MXCSR_XCPT_MASK, 7505 /*256:out */ X86_MXCSR_XCPT_MASK, 7506 /*xcpt? */ false, false }, 7507 /* SNan, QNan (Masked). */ 7508 { { /*src2 */ { FP32_SNAN(0), FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V6) } }, 7509 { /*src1 */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1) } }, 7510 { /* => */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1) } }, 7511 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 7512 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, 7513 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, 7514 /*xcpt? */ false, false }, 7515 { { /*src2 */ { FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V6) } }, 7516 { /*src1 */ { FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1) } }, 7517 { /* => */ { FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1) } }, 7518 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 7519 /*128:out */ X86_MXCSR_XCPT_MASK, 7520 /*256:out */ X86_MXCSR_XCPT_MASK, 7521 /*xcpt? */ false, false }, 7522 { { /*src2 */ { FP32_SNAN_V(0, FP32_FRAC_V0), FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V6) } }, 7523 { /*src1 */ { FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1) } }, 7524 { /* => */ { FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1) } }, 7525 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 7526 /*128:out */ X86_MXCSR_XCPT_MASK, 7527 /*256:out */ X86_MXCSR_XCPT_MASK, 7528 /*xcpt? */ false, false }, 7529 /* SNan, SNan (Masked). */ 7530 { { /*src2 */ { FP32_SNAN(0), FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V7), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V1) } }, 7531 { /*src1 */ { FP32_SNAN(0), FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2) } }, 7532 { /* => */ { FP32_QNAN_V(0, 1), FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2) } }, 7533 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 7534 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, 7535 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, 7536 /*xcpt? */ false, false }, 7537 { { /*src2 */ { FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V7), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V1) } }, 7538 { /*src1 */ { FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V0), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2) } }, 7539 { /* => */ { FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V0), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2) } }, 7540 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 7541 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, 7542 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, 7543 /*xcpt? */ false, false }, 7544 { { /*src2 */ { FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V7), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V1) } }, 7545 { /*src1 */ { FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V0) } }, 7546 { /* => */ { FP32_QNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V0) } }, 7547 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 7548 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, 7549 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, 7550 /*xcpt? */ false, false }, 7551 /* QNan, Norm FP (Masked). */ 7552 { { /*src2 */ { FP32_QNAN(0), FP32_QNAN_V(1, FP32_FRAC_NORM_MAX), FP32_NORM_V0(1), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_NORM_V3(0), FP32_QNAN_V(1, FP32_FRAC_V3), FP32_NORM_V5(0), FP32_QNAN_V(1, FP32_FRAC_V5) } }, 7553 { /*src1 */ { FP32_1(0), FP32_1(1), FP32_QNAN_V(1, FP32_FRAC_V0), FP32_NORM_V2(1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_NORM_V4(0), FP32_QNAN_V(1, FP32_FRAC_V4), FP32_NORM_V6(1) } }, 7554 { /* => */ { FP32_QNAN(0), FP32_1(1), FP32_QNAN_V(1, FP32_FRAC_V0), FP32_NORM_V2(1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_NORM_V4(0), FP32_QNAN_V(1, FP32_FRAC_V4), FP32_NORM_V6(1) } }, 7555 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 7556 /*128:out */ X86_MXCSR_XCPT_MASK, 7557 /*256:out */ X86_MXCSR_XCPT_MASK, 7558 /*xcpt? */ false, false }, 7559 /* SNan, Norm FP (Masked). */ 7560 { { /*src2 */ { FP32_SNAN(1), FP32_SNAN_V(1, FP32_FRAC_NORM_MAX), FP32_NORM_V0(1), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_NORM_V3(0), FP32_SNAN_V(1, FP32_FRAC_V3), FP32_NORM_V5(0), FP32_SNAN_V(1, FP32_FRAC_V5) } }, 7561 { /*src1 */ { FP32_1(0), FP32_1(0), FP32_SNAN_V(1, FP32_FRAC_V0), FP32_NORM_V2(1), FP32_SNAN_V(1, FP32_FRAC_V2), FP32_NORM_V4(0), FP32_SNAN_V(1, FP32_FRAC_V4), FP32_NORM_V6(1) } }, 7562 { /* => */ { FP32_QNAN_V(1, 1), FP32_1(0), FP32_SNAN_V(1, FP32_FRAC_V0), FP32_NORM_V2(1), FP32_SNAN_V(1, FP32_FRAC_V2), FP32_NORM_V4(0), FP32_SNAN_V(1, FP32_FRAC_V4), FP32_NORM_V6(1) } }, 7563 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 7564 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, 7565 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, 7566 /*xcpt? */ false, false }, 7567 /* QNan, QNan (Unmasked). */ 7568 /*44*/{ { /*src2 */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V0), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V5) } }, 7569 { /*src1 */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4) } }, 7570 { /* => */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4) } }, 7571 /*mxcsr:in */ 0, 7572 /*128:out */ 0, 7573 /*256:out */ 0, 7574 /*xcpt? */ false, false }, 7575 { { /*src2 */ { FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4) } }, 7576 { /*src1 */ { FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V1) } }, 7577 { /* => */ { FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V1) } }, 7578 /*mxcsr:in */ 0, 7579 /*128:out */ 0, 7580 /*256:out */ 0, 7581 /*xcpt? */ false, false }, 7582 { { /*src2 */ { FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4) } }, 7583 { /*src1 */ { FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V1) } }, 7584 { /* => */ { FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V1) } }, 7585 /*mxcsr:in */ 0, 7586 /*128:out */ 0, 7587 /*256:out */ 0, 7588 /*xcpt? */ false, false }, 7589 7590 /* QNan, SNan (Unmasked). */ 7591 { { /*src2 */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4) } }, 7592 { /*src1 */ { FP32_SNAN(0), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V1) } }, 7593 { /* => */ { FP32_QNAN_V(0, 1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V1) } }, 7594 /*mxcsr:in */ 0, 7595 /*128:out */ X86_MXCSR_IE, 7596 /*256:out */ X86_MXCSR_IE, 7597 /*xcpt? */ true, true }, 7598 { { /*src2 */ { FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V0), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V5) } }, 7599 { /*src1 */ { FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V4) } }, 7600 { /* => */ { FP32_QNAN_V(0, 1), FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V4) } }, 7601 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 7602 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN | X86_MXCSR_IE, 7603 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN | X86_MXCSR_IE, 7604 /*xcpt? */ true, true }, 7605 { { /*src2 */ { FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V0), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V5) } }, 7606 { /*src1 */ { FP32_SNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4) } }, 7607 { /* => */ { FP32_SNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4) } }, 7608 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, 7609 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, 7610 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, 7611 /*xcpt? */ false, false }, 7612 /* SNan, QNan (Unmasked). */ 7613 { { /*src2 */ { FP32_SNAN(0), FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V6) } }, 7614 { /*src1 */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1) } }, 7615 { /* => */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1) } }, 7616 /*mxcsr:in */ X86_MXCSR_DAZ, 7617 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_IE, 7618 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_IE, 7619 /*xcpt? */ true, true }, 7620 { { /*src2 */ { FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V6) } }, 7621 { /*src1 */ { FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1) } }, 7622 { /* => */ { FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1) } }, 7623 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_RC_UP, 7624 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_UP, 7625 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_UP, 7626 /*xcpt? */ false, false }, 7627 { { /*src2 */ { FP32_SNAN_V(0, FP32_FRAC_V0), FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V6) } }, 7628 { /*src1 */ { FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1) } }, 7629 { /* => */ { FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1) } }, 7630 /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 7631 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 7632 /*256:out */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 7633 /*xcpt? */ false, false }, 7634 /* SNan, SNan (Unmasked). */ 7635 /*54*/{ { /*src2 */ { FP32_SNAN(0), FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V7), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V1) } }, 7636 { /*src1 */ { FP32_SNAN(0), FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2) } }, 7637 { /* => */ { FP32_QNAN_V(0, 1), FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2) } }, 7638 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ, 7639 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_IE, 7640 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_IE, 7641 /*xcpt? */ true, true }, 7642 { { /*src2 */ { FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V7), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V1) } }, 7643 { /*src1 */ { FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V0), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2) } }, 7644 { /* => */ { FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V0), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2) } }, 7645 /*mxcsr:in */ X86_MXCSR_RC_ZERO, 7646 /*128:out */ X86_MXCSR_RC_ZERO | X86_MXCSR_IE, 7647 /*256:out */ X86_MXCSR_RC_ZERO | X86_MXCSR_IE, 7648 /*xcpt? */ true, true }, 7649 { { /*src2 */ { FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V7), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V1) } }, 7650 { /*src1 */ { FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V0) } }, 7651 { /* => */ { FP32_QNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V0) } }, 7652 /*mxcsr:in */ X86_MXCSR_FZ, 7653 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_IE, 7654 /*256:out */ X86_MXCSR_FZ | X86_MXCSR_IE, 7655 /*xcpt? */ true, true }, 7656 /* QNan, Norm FP (Unmasked). */ 7657 { { /*src2 */ { FP32_QNAN(0), FP32_QNAN_V(1, FP32_FRAC_NORM_MAX), FP32_NORM_V0(1), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_NORM_V3(0), FP32_QNAN_V(1, FP32_FRAC_V3), FP32_NORM_V5(0), FP32_QNAN_V(1, FP32_FRAC_V5) } }, 7658 { /*src1 */ { FP32_1(0), FP32_1(1), FP32_QNAN_V(1, FP32_FRAC_V0), FP32_NORM_V2(1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_NORM_V4(0), FP32_QNAN_V(1, FP32_FRAC_V4), FP32_NORM_V6(1) } }, 7659 { /* => */ { FP32_QNAN(0), FP32_1(1), FP32_QNAN_V(1, FP32_FRAC_V0), FP32_NORM_V2(1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_NORM_V4(0), FP32_QNAN_V(1, FP32_FRAC_V4), FP32_NORM_V6(1) } }, 7660 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO, 7661 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO, 7662 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO, 7663 /*xcpt? */ false, false }, 7664 /* SNan, Norm FP (Unmasked). */ 7665 /*58*/{ { /*src2 */ { FP32_SNAN(1), FP32_SNAN_V(1, FP32_FRAC_NORM_MAX), FP32_NORM_V0(1), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_NORM_V3(0), FP32_SNAN_V(1, FP32_FRAC_V3), FP32_NORM_V5(0), FP32_SNAN_V(1, FP32_FRAC_V5) } }, 7666 { /*src1 */ { FP32_1(0), FP32_1(0), FP32_SNAN_V(1, FP32_FRAC_V0), FP32_NORM_V2(1), FP32_SNAN_V(1, FP32_FRAC_V2), FP32_NORM_V4(0), FP32_SNAN_V(1, FP32_FRAC_V4), FP32_NORM_V6(1) } }, 7667 { /* => */ { FP32_QNAN_V(1, 1), FP32_1(0), FP32_SNAN_V(1, FP32_FRAC_V0), FP32_NORM_V2(1), FP32_SNAN_V(1, FP32_FRAC_V2), FP32_NORM_V4(0), FP32_SNAN_V(1, FP32_FRAC_V4), FP32_NORM_V6(1) } }, 7668 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, 7669 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE, 7670 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE, 7671 /*xcpt? */ true, true }, 7672 /** @todo Underflow, Precision; Rounding, FZ etc. */ 6787 /*28*/ BS3CPUINSTR4_SS_INVALIDS 6788 /** @todo Underflow, Precision; Rounding; FZ etc. */ 7673 6789 }; 7674 6790 … … 7964 7080 * Invalids. 7965 7081 */ 7966 /* QNan, QNan (Masked). */ 7967 /*33*/{ { /*src2 */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V0), FP64_QNAN_V(0, FP64_FRAC_V1) } }, 7968 { /*src1 */ { FP64_QNAN(0), FP64_QNAN_V(1, FP64_FRAC_NORM_MIN), FP64_QNAN_V(1, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V2) } }, 7969 { /* => */ { FP64_QNAN(0), FP64_QNAN_V(1, FP64_FRAC_NORM_MIN), FP64_QNAN_V(1, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V2) } }, 7970 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 7971 /*128:out */ X86_MXCSR_XCPT_MASK, 7972 /*256:out */ X86_MXCSR_XCPT_MASK, 7973 /*xcpt? */ false, false }, 7974 { { /*src2 */ { FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(1, FP64_FRAC_V1), FP64_QNAN_V(0, FP64_FRAC_V2), FP64_INF(0) } }, 7975 { /*src1 */ { FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(1, FP64_FRAC_V2), FP64_QNAN_V(1, FP64_FRAC_V3), FP64_SNAN(1) } }, 7976 { /* => */ { FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(1, FP64_FRAC_V2), FP64_QNAN_V(1, FP64_FRAC_V3), FP64_SNAN(1) } }, 7977 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 7978 /*128:out */ X86_MXCSR_XCPT_MASK, 7979 /*256:out */ X86_MXCSR_XCPT_MASK, 7980 /*xcpt? */ false, false }, 7981 { { /*src2 */ { FP64_QNAN_V(0, FP64_FRAC_V1), FP64_QNAN_V(0, FP64_FRAC_V1), FP64_QNAN_V(0, FP64_FRAC_V2), FP64_INF(1) } }, 7982 { /*src1 */ { FP64_QNAN_V(0, FP64_FRAC_V0), FP64_QNAN_V(0, FP64_FRAC_V2), FP64_QNAN_V(1, FP64_FRAC_V3), FP64_QNAN(0) } }, 7983 { /* => */ { FP64_QNAN_V(0, FP64_FRAC_V0), FP64_QNAN_V(0, FP64_FRAC_V2), FP64_QNAN_V(1, FP64_FRAC_V3), FP64_QNAN(0) } }, 7984 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 7985 /*128:out */ X86_MXCSR_XCPT_MASK, 7986 /*256:out */ X86_MXCSR_XCPT_MASK, 7987 /*xcpt? */ false, false }, 7988 /* QNan, SNan (Masked). */ 7989 { { /*src2 */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_V1), FP64_QNAN_V(0, FP64_FRAC_V2), FP64_QNAN_V(0, FP64_FRAC_V3) } }, 7990 { /*src1 */ { FP64_SNAN(0), FP64_SNAN_V(1, FP64_FRAC_V2), FP64_SNAN_V(0, FP64_FRAC_V1), FP64_SNAN_V(1, FP64_FRAC_V2) } }, 7991 { /* => */ { FP64_QNAN_V(0, 1), FP64_QNAN_V(1, FP64_FRAC_V2), FP64_SNAN_V(0, FP64_FRAC_V1), FP64_SNAN_V(1, FP64_FRAC_V2) } }, 7992 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 7993 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, 7994 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, 7995 /*xcpt? */ false, false }, 7996 { { /*src2 */ { FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V0), FP64_QNAN_V(0, FP64_FRAC_V1) } }, 7997 { /*src1 */ { FP64_SNAN_V(0, FP64_FRAC_NORM_MIN), FP64_SNAN_V(1, FP64_FRAC_NORM_MIN), FP64_SNAN_V(1, FP64_FRAC_NORM_MAX), FP64_SNAN_V(0, FP64_FRAC_V2) } }, 7998 { /* => */ { FP64_QNAN_V(0, 1), FP64_SNAN_V(1, FP64_FRAC_NORM_MIN), FP64_SNAN_V(1, FP64_FRAC_NORM_MAX), FP64_SNAN_V(0, FP64_FRAC_V2) } }, 7999 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 8000 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, 8001 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, 8002 /*xcpt? */ false, false }, 8003 { { /*src2 */ { FP64_QNAN_V(0, FP64_FRAC_V1), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V0), FP64_INF(0) } }, 8004 { /*src1 */ { FP64_SNAN_V(0, FP64_FRAC_V2), FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(1, FP64_FRAC_NORM_MAX), FP64_QNAN(1) } }, 8005 { /* => */ { FP64_SNAN_V(0, FP64_FRAC_V2), FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(1, FP64_FRAC_NORM_MAX), FP64_QNAN(1) } }, 8006 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 8007 /*128:out */ X86_MXCSR_XCPT_MASK, 8008 /*256:out */ X86_MXCSR_XCPT_MASK, 8009 /*xcpt? */ false, false }, 8010 /* SNan, QNan (Masked). */ 8011 { { /*src2 */ { FP64_SNAN(0), FP64_SNAN_V(0, FP64_FRAC_NORM_MIN), FP64_SNAN_V(0, FP64_FRAC_V1), FP64_SNAN_V(1, FP64_FRAC_V1) } }, 8012 { /*src1 */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(1, FP64_FRAC_V3), FP64_QNAN_V(1, FP64_FRAC_V2) } }, 8013 { /* => */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(1, FP64_FRAC_V3), FP64_QNAN_V(1, FP64_FRAC_V2) } }, 8014 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 8015 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, 8016 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, 8017 /*xcpt? */ false, false }, 8018 { { /*src2 */ { FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_SNAN_V(1, FP64_FRAC_NORM_MAX), FP64_SNAN_V(0, FP64_FRAC_V1), FP64_SNAN_V(0, FP64_FRAC_V1) } }, 8019 { /*src1 */ { FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(1, FP64_FRAC_NORM_MIN), FP64_QNAN_V(1, FP64_FRAC_V3), FP64_QNAN_V(0, FP64_FRAC_V2) } }, 8020 { /* => */ { FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(1, FP64_FRAC_NORM_MIN), FP64_QNAN_V(1, FP64_FRAC_V3), FP64_QNAN_V(0, FP64_FRAC_V2) } }, 8021 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 8022 /*128:out */ X86_MXCSR_XCPT_MASK, 8023 /*256:out */ X86_MXCSR_XCPT_MASK, 8024 /*xcpt? */ false, false }, 8025 { { /*src2 */ { FP64_SNAN_V(0, FP64_FRAC_V0), FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_SNAN_V(0, FP64_FRAC_V1), FP64_SNAN_V(0, FP64_FRAC_V1) } }, 8026 { /*src1 */ { FP64_QNAN_V(0, FP64_FRAC_V1), FP64_QNAN_V(1, FP64_FRAC_NORM_MIN), FP64_QNAN_V(1, FP64_FRAC_V2), FP64_QNAN_V(1, FP64_FRAC_V3) } }, 8027 { /* => */ { FP64_QNAN_V(0, FP64_FRAC_V1), FP64_QNAN_V(1, FP64_FRAC_NORM_MIN), FP64_QNAN_V(1, FP64_FRAC_V2), FP64_QNAN_V(1, FP64_FRAC_V3) } }, 8028 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 8029 /*128:out */ X86_MXCSR_XCPT_MASK, 8030 /*256:out */ X86_MXCSR_XCPT_MASK, 8031 /*xcpt? */ false, false }, 8032 /* SNan, SNan (Masked). */ 8033 { { /*src2 */ { FP64_SNAN(0), FP64_SNAN_V(0, FP64_FRAC_NORM_MIN), FP64_SNAN_V(0, FP64_FRAC_V1), FP64_SNAN_V(0, FP64_FRAC_V2) } }, 8034 { /*src1 */ { FP64_SNAN(0), FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_SNAN_V(0, FP64_FRAC_V0), FP64_SNAN_V(0, FP64_FRAC_V3) } }, 8035 { /* => */ { FP64_QNAN_V(0, 1), FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_SNAN_V(0, FP64_FRAC_V0), FP64_SNAN_V(0, FP64_FRAC_V3) } }, 8036 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 8037 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, 8038 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, 8039 /*xcpt? */ false, false }, 8040 { { /*src2 */ { FP64_SNAN_V(0, FP64_FRAC_NORM_MIN), FP64_SNAN_V(0, FP64_FRAC_V2), FP64_SNAN_V(0, FP64_FRAC_V1), FP64_SNAN_V(0, FP64_FRAC_V2) } }, 8041 { /*src1 */ { FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_SNAN_V(0, FP64_FRAC_V0), FP64_SNAN_V(0, FP64_FRAC_V2), FP64_SNAN_V(1, FP64_FRAC_V3) } }, 8042 { /* => */ { FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_SNAN_V(0, FP64_FRAC_V0), FP64_SNAN_V(0, FP64_FRAC_V2), FP64_SNAN_V(1, FP64_FRAC_V3) } }, 8043 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 8044 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, 8045 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, 8046 /*xcpt? */ false, false }, 8047 { { /*src2 */ { FP64_SNAN_V(0, FP64_FRAC_V1), FP64_SNAN_V(0, FP64_FRAC_V2), FP64_SNAN_V(0, FP64_FRAC_V1), FP64_SNAN_V(0, FP64_FRAC_V2) } }, 8048 { /*src1 */ { FP64_SNAN_V(0, FP64_FRAC_V0), FP64_SNAN_V(0, FP64_FRAC_V3), FP64_SNAN_V(0, FP64_FRAC_V0), FP64_SNAN_V(0, FP64_FRAC_V3) } }, 8049 { /* => */ { FP64_QNAN_V(0, FP64_FRAC_V0), FP64_SNAN_V(0, FP64_FRAC_V3), FP64_SNAN_V(0, FP64_FRAC_V0), FP64_SNAN_V(0, FP64_FRAC_V3) } }, 8050 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 8051 /*128:out */ X86_MXCSR_XCPT_MASK, 8052 /*256:out */ X86_MXCSR_XCPT_MASK, 8053 /*xcpt? */ false, false }, 8054 /* QNan, Norm FP (Masked). */ 8055 { { /*src2 */ { FP64_QNAN(0), FP64_QNAN_V(1, FP64_FRAC_NORM_MAX), FP64_NORM_V0(1), FP64_QNAN_V(0, FP64_FRAC_V1) } }, 8056 { /*src1 */ { FP64_1(0), FP64_1(1), FP64_QNAN_V(1, FP64_FRAC_V0), FP64_NORM_V2(1) } }, 8057 { /* => */ { FP64_QNAN(0), FP64_1(1), FP64_QNAN_V(1, FP64_FRAC_V0), FP64_NORM_V2(1) } }, 8058 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 8059 /*128:out */ X86_MXCSR_XCPT_MASK, 8060 /*256:out */ X86_MXCSR_XCPT_MASK, 8061 /*xcpt? */ false, false }, 8062 /* SNan, Norm FP (Masked). */ 8063 { { /*src2 */ { FP64_SNAN(1), FP64_SNAN_V(1, FP64_FRAC_NORM_MAX), FP64_NORM_V0(1), FP64_SNAN_V(0, FP64_FRAC_V1) } }, 8064 { /*src1 */ { FP64_1(0), FP64_1(0), FP64_SNAN_V(1, FP64_FRAC_V0), FP64_NORM_V2(1) } }, 8065 { /* => */ { FP64_QNAN_V(1, 1), FP64_1(0), FP64_SNAN_V(1, FP64_FRAC_V0), FP64_NORM_V2(1) } }, 8066 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 8067 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, 8068 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, 8069 /*xcpt? */ false, false }, 8070 /* QNan, QNan (Unmasked). */ 8071 /*47*/{ { /*src2 */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V0), FP64_QNAN_V(0, FP64_FRAC_V1) } }, 8072 { /*src1 */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V2) } }, 8073 { /* => */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V2) } }, 8074 /*mxcsr:in */ 0, 8075 /*128:out */ 0, 8076 /*256:out */ 0, 8077 /*xcpt? */ false, false }, 8078 { { /*src2 */ { FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V1), FP64_QNAN_V(0, FP64_FRAC_V2), FP64_QNAN_V(0, FP64_FRAC_V3) } }, 8079 { /*src1 */ { FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(0, FP64_FRAC_V2), FP64_QNAN_V(0, FP64_FRAC_V0), FP64_QNAN_V(0, FP64_FRAC_V2) } }, 8080 { /* => */ { FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(0, FP64_FRAC_V2), FP64_QNAN_V(0, FP64_FRAC_V0), FP64_QNAN_V(0, FP64_FRAC_V2) } }, 8081 /*mxcsr:in */ 0, 8082 /*128:out */ 0, 8083 /*256:out */ 0, 8084 /*xcpt? */ false, false }, 8085 { { /*src2 */ { FP64_QNAN_V(0, FP64_FRAC_V1), FP64_QNAN_V(0, FP64_FRAC_V1), FP64_QNAN_V(0, FP64_FRAC_V2), FP64_QNAN_V(0, FP64_FRAC_V3) } }, 8086 { /*src1 */ { FP64_QNAN_V(0, FP64_FRAC_V2), FP64_QNAN_V(1, FP64_FRAC_V2), FP64_QNAN_V(0, FP64_FRAC_V0), FP64_QNAN_V(1, FP64_FRAC_V0) } }, 8087 { /* => */ { FP64_QNAN_V(0, FP64_FRAC_V2), FP64_QNAN_V(1, FP64_FRAC_V2), FP64_QNAN_V(0, FP64_FRAC_V0), FP64_QNAN_V(1, FP64_FRAC_V0) } }, 8088 /*mxcsr:in */ 0, 8089 /*128:out */ 0, 8090 /*256:out */ 0, 8091 /*xcpt? */ false, false }, 8092 8093 /* QNan, SNan (Unmasked). */ 8094 { { /*src2 */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_V1), FP64_QNAN_V(0, FP64_FRAC_V2), FP64_QNAN_V(0, FP64_FRAC_V3) } }, 8095 { /*src1 */ { FP64_SNAN(0), FP64_SNAN_V(1, FP64_FRAC_V2), FP64_SNAN_V(1, FP64_FRAC_V3), FP64_SNAN_V(0, FP64_FRAC_V2) } }, 8096 { /* => */ { FP64_QNAN_V(0, 1), FP64_QNAN_V(1, FP64_FRAC_V2), FP64_SNAN_V(1, FP64_FRAC_V3), FP64_SNAN_V(0, FP64_FRAC_V2) } }, 8097 /*mxcsr:in */ 0, 8098 /*128:out */ X86_MXCSR_IE, 8099 /*256:out */ X86_MXCSR_IE, 8100 /*xcpt? */ true, true }, 8101 { { /*src2 */ { FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V0), FP64_QNAN_V(0, FP64_FRAC_V1) } }, 8102 { /*src1 */ { FP64_SNAN_V(0, FP64_FRAC_NORM_MIN), FP64_SNAN_V(0, FP64_FRAC_NORM_MIN), FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_SNAN_V(0, FP64_FRAC_V2) } }, 8103 { /* => */ { FP64_QNAN_V(0, 1), FP64_SNAN_V(0, FP64_FRAC_NORM_MIN), FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_SNAN_V(0, FP64_FRAC_V2) } }, 8104 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 8105 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN | X86_MXCSR_IE, 8106 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN | X86_MXCSR_IE, 8107 /*xcpt? */ true, true }, 8108 { { /*src2 */ { FP64_QNAN_V(0, FP64_FRAC_V1), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V0), FP64_QNAN_V(0, FP64_FRAC_V1) } }, 8109 { /*src1 */ { FP64_SNAN_V(0, FP64_FRAC_V2), FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V2) } }, 8110 { /* => */ { FP64_SNAN_V(0, FP64_FRAC_V2), FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V2) } }, 8111 /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, 8112 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, 8113 /*256:out */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, 8114 /*xcpt? */ false, false }, 8115 /* SNan, QNan (Unmasked). */ 8116 { { /*src2 */ { FP64_SNAN(0), FP64_SNAN_V(0, FP64_FRAC_NORM_MIN), FP64_SNAN_V(0, FP64_FRAC_V1), FP64_SNAN_V(0, FP64_FRAC_V1) } }, 8117 { /*src1 */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V3), FP64_QNAN_V(0, FP64_FRAC_V2) } }, 8118 { /* => */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V3), FP64_QNAN_V(0, FP64_FRAC_V2) } }, 8119 /*mxcsr:in */ X86_MXCSR_DAZ, 8120 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_IE, 8121 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_IE, 8122 /*xcpt? */ true, true }, 8123 { { /*src2 */ { FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_SNAN_V(0, FP64_FRAC_V1), FP64_SNAN_V(1, FP64_FRAC_V1) } }, 8124 { /*src1 */ { FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(1, FP64_FRAC_V2), FP64_QNAN_V(1, FP64_FRAC_V0) } }, 8125 { /* => */ { FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(1, FP64_FRAC_V2), FP64_QNAN_V(1, FP64_FRAC_V0) } }, 8126 /*mxcsr:in */ X86_MXCSR_RC_UP, 8127 /*128:out */ X86_MXCSR_RC_UP, 8128 /*256:out */ X86_MXCSR_RC_UP, 8129 /*xcpt? */ false, false }, 8130 { { /*src2 */ { FP64_SNAN_V(0, FP64_FRAC_V0), FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_SNAN_V(0, FP64_FRAC_V1), FP64_SNAN_V(1, FP64_FRAC_V1) } }, 8131 { /*src1 */ { FP64_QNAN_V(0, FP64_FRAC_V3), FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(1, FP64_FRAC_V2), FP64_QNAN_V(1, FP64_FRAC_V3) } }, 8132 { /* => */ { FP64_QNAN_V(0, FP64_FRAC_V3), FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(1, FP64_FRAC_V2), FP64_QNAN_V(1, FP64_FRAC_V3) } }, 8133 /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 8134 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 8135 /*256:out */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 8136 /*xcpt? */ false, false }, 8137 /* SNan, SNan (Unmasked). */ 8138 /*56*/{ { /*src2 */ { FP64_SNAN(0), FP64_SNAN_V(0, FP64_FRAC_NORM_MIN), FP64_SNAN_V(0, FP64_FRAC_V1), FP64_SNAN_V(0, FP64_FRAC_V2) } }, 8139 { /*src1 */ { FP64_SNAN(0), FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_SNAN_V(0, FP64_FRAC_V2), FP64_SNAN_V(1, FP64_FRAC_V0) } }, 8140 { /* => */ { FP64_QNAN_V(0, 1), FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_SNAN_V(0, FP64_FRAC_V2), FP64_SNAN_V(1, FP64_FRAC_V0) } }, 8141 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ, 8142 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_IE, 8143 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_IE, 8144 /*xcpt? */ true, true }, 8145 { { /*src2 */ { FP64_SNAN_V(0, FP64_FRAC_NORM_MIN), FP64_SNAN_V(0, FP64_FRAC_V2), FP64_SNAN_V(0, FP64_FRAC_V1), FP64_SNAN_V(1, FP32_FRAC_V2) } }, 8146 { /*src1 */ { FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_SNAN_V(0, FP64_FRAC_V0), FP64_SNAN_V(1, FP64_FRAC_V2), FP64_SNAN_V(1, FP32_FRAC_V3) } }, 8147 { /* => */ { FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_SNAN_V(0, FP64_FRAC_V0), FP64_SNAN_V(1, FP64_FRAC_V2), FP64_SNAN_V(1, FP32_FRAC_V3) } }, 8148 /*mxcsr:in */ X86_MXCSR_RC_ZERO, 8149 /*128:out */ X86_MXCSR_RC_ZERO | X86_MXCSR_IE, 8150 /*256:out */ X86_MXCSR_RC_ZERO | X86_MXCSR_IE, 8151 /*xcpt? */ true, true }, 8152 { { /*src2 */ { FP64_SNAN_V(0, FP64_FRAC_V1), FP64_SNAN_V(0, FP64_FRAC_V2), FP64_SNAN_V(1, FP64_FRAC_V0), FP64_SNAN_V(0, FP64_FRAC_V2) } }, 8153 { /*src1 */ { FP64_SNAN_V(0, FP64_FRAC_V2), FP64_SNAN_V(1, FP64_FRAC_V3), FP64_SNAN_V(1, FP64_FRAC_V3), FP64_SNAN_V(0, FP64_FRAC_V3) } }, 8154 { /* => */ { FP64_QNAN_V(0, FP64_FRAC_V2), FP64_SNAN_V(1, FP64_FRAC_V3), FP64_SNAN_V(1, FP64_FRAC_V3), FP64_SNAN_V(0, FP64_FRAC_V3) } }, 8155 /*mxcsr:in */ 0, 8156 /*128:out */ 0, 8157 /*256:out */ 0, 8158 /*xcpt? */ false, false }, 8159 /* QNan, Norm FP (Unmasked). */ 8160 { { /*src2 */ { FP64_QNAN(0), FP64_QNAN_V(1, FP64_FRAC_NORM_MAX), FP64_NORM_V0(1), FP64_QNAN_V(0, FP64_FRAC_V1) } }, 8161 { /*src1 */ { FP64_1(0), FP64_INF(1), FP64_QNAN_V(1, FP64_FRAC_V0), FP64_NORM_V2(1) } }, 8162 { /* => */ { FP64_QNAN(0), FP64_INF(1), FP64_QNAN_V(1, FP64_FRAC_V0), FP64_NORM_V2(1) } }, 8163 /*mxcsr:in */ X86_MXCSR_FZ, 8164 /*128:out */ X86_MXCSR_FZ, 8165 /*256:out */ X86_MXCSR_FZ, 8166 /*xcpt? */ false, false }, 8167 /* SNan, Norm FP (Unmasked). */ 8168 /*60*/{ { /*src2 */ { FP64_SNAN(1), FP64_SNAN_V(1, FP64_FRAC_NORM_MAX), FP64_NORM_V0(1), FP64_SNAN_V(0, FP64_FRAC_V1) } }, 8169 { /*src1 */ { FP64_1(0), FP64_INF(0), FP64_SNAN_V(1, FP64_FRAC_V0), FP64_NORM_V2(1) } }, 8170 { /* => */ { FP64_QNAN_V(1, 1), FP64_INF(0), FP64_SNAN_V(1, FP64_FRAC_V0), FP64_NORM_V2(1) } }, 8171 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, 8172 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE, 8173 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE, 8174 /*xcpt? */ true, true }, 8175 /** @todo Underflow, Precision; Rounding, FZ etc. */ 7082 /*33*/ BS3CPUINSTR4_SD_INVALIDS 7083 /** @todo Underflow, Precision; Rounding; FZ etc. */ 8176 7084 }; 8177 7085 … … 8517 7425 * Invalids. 8518 7426 */ 8519 /*38*/{ { /*src2 */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V0), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V5) } }, 8520 { /*src1 */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4) } }, 8521 { /* => */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4) } }, 8522 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 8523 /*128:out */ X86_MXCSR_XCPT_MASK, 8524 /*256:out */ X86_MXCSR_XCPT_MASK, 8525 /*xcpt? */ false, false }, 8526 { { /*src2 */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V0), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V5) } }, 8527 { /*src1 */ { FP32_SNAN(0), FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V4) } }, 8528 { /* => */ { FP32_QNAN_V(0, 1), FP32_QNAN_V(0, 1), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4) } }, 8529 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 8530 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, 8531 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, 8532 /*xcpt? */ false, false }, 8533 { { /*src2 */ { FP32_SNAN(0), FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V6) } }, 8534 { /*src1 */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1) } }, 8535 { /* => */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1) } }, 8536 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ, 8537 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_IE, 8538 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_IE, 8539 /*xcpt? */ false, false }, 8540 { { /*src2 */ { FP32_SNAN(0), FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V7), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V1) } }, 8541 { /*src1 */ { FP32_SNAN(0), FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2) } }, 8542 { /* => */ { FP32_QNAN_V(0, 1), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2) } }, 8543 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 8544 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, 8545 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, 8546 /*xcpt? */ false, false }, 8547 { { /*src2 */ { FP32_QNAN(0), FP32_QNAN_V(1, FP32_FRAC_NORM_MAX), FP32_NORM_V0(1), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_NORM_V3(0), FP32_QNAN_V(1, FP32_FRAC_V3), FP32_NORM_V5(0), FP32_QNAN_V(1, FP32_FRAC_V5) } }, 8548 { /*src1 */ { FP32_1(0), FP32_1(1), FP32_QNAN_V(1, FP32_FRAC_V0), FP32_NORM_V2(1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_NORM_V4(0), FP32_QNAN_V(1, FP32_FRAC_V4), FP32_NORM_V6(1) } }, 8549 { /* => */ { FP32_QNAN(0), FP32_QNAN_V(1, FP32_FRAC_NORM_MAX), FP32_QNAN_V(1, FP32_FRAC_V0), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(1, FP32_FRAC_V3), FP32_QNAN_V(1, FP32_FRAC_V4), FP32_QNAN_V(1, FP32_FRAC_V5) } }, 8550 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_XCPT_FLAGS, 8551 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_XCPT_FLAGS, 8552 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_XCPT_FLAGS, 8553 /*xcpt? */ false, false }, 8554 { { /*src2 */ { FP32_SNAN(1), FP32_SNAN_V(1, FP32_FRAC_NORM_MAX), FP32_NORM_V0(1), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_NORM_V3(0), FP32_SNAN_V(1, FP32_FRAC_V3), FP32_NORM_V5(0), FP32_SNAN_V(1, FP32_FRAC_V5) } }, 8555 { /*src1 */ { FP32_1(0), FP32_1(0), FP32_SNAN_V(1, FP32_FRAC_V0), FP32_NORM_V2(1), FP32_SNAN_V(1, FP32_FRAC_V2), FP32_NORM_V4(0), FP32_SNAN_V(1, FP32_FRAC_V4), FP32_NORM_V6(1) } }, 8556 { /* => */ { FP32_QNAN_V(1, 1), FP32_QNAN_V(1, FP32_FRAC_NORM_MAX), FP32_QNAN_V(1, FP32_FRAC_V0), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(1, FP32_FRAC_V2), FP32_QNAN_V(1, FP32_FRAC_V3), FP32_QNAN_V(1, FP32_FRAC_V4), FP32_QNAN_V(1, FP32_FRAC_V5) } }, 8557 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 8558 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, 8559 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, 8560 /*xcpt? */ false, false }, 8561 { { /*src2 */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V0), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V5) } }, 8562 { /*src1 */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4) } }, 8563 { /* => */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4) } }, 8564 /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 8565 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 8566 /*256:out */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 8567 /*xcpt? */ false, false }, 8568 { { /*src2 */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V0), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V5) } }, 8569 { /*src1 */ { FP32_SNAN(0), FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V4) } }, 8570 { /* => */ { FP32_QNAN_V(0, 1), FP32_QNAN_V(0, 1), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4) } }, 8571 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, 8572 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE, 8573 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE, 8574 /*xcpt? */ true, true }, 8575 { { /*src2 */ { FP32_SNAN(0), FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V6) } }, 8576 { /*src1 */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1) } }, 8577 { /* => */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1) } }, 8578 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP, 8579 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP | X86_MXCSR_IE, 8580 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP | X86_MXCSR_IE, 8581 /*xcpt? */ true, true }, 8582 { { /*src2 */ { FP32_SNAN(0), FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V7), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V1) } }, 8583 { /*src1 */ { FP32_SNAN(0), FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2) } }, 8584 { /* => */ { FP32_QNAN_V(0, 1), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2) } }, 8585 /*mxcsr:in */ X86_MXCSR_RC_UP, 8586 /*128:out */ X86_MXCSR_RC_UP | X86_MXCSR_IE, 8587 /*256:out */ X86_MXCSR_RC_UP | X86_MXCSR_IE, 8588 /*xcpt? */ true, true }, 8589 { { /*src2 */ { FP32_QNAN(0), FP32_QNAN_V(1, FP32_FRAC_NORM_MAX), FP32_NORM_V0(1), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_NORM_V3(0), FP32_QNAN_V(1, FP32_FRAC_V3), FP32_NORM_V5(0), FP32_QNAN_V(1, FP32_FRAC_V5) } }, 8590 { /*src1 */ { FP32_1(0), FP32_1(1), FP32_QNAN_V(1, FP32_FRAC_V0), FP32_NORM_V2(1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_NORM_V4(0), FP32_QNAN_V(1, FP32_FRAC_V4), FP32_NORM_V6(1) } }, 8591 { /* => */ { FP32_QNAN(0), FP32_QNAN_V(1, FP32_FRAC_NORM_MAX), FP32_QNAN_V(1, FP32_FRAC_V0), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(1, FP32_FRAC_V3), FP32_QNAN_V(1, FP32_FRAC_V4), FP32_QNAN_V(1, FP32_FRAC_V5) } }, 8592 /*mxcsr:in */ 0, 8593 /*128:out */ 0, 8594 /*256:out */ 0, 8595 /*xcpt? */ false, false }, 8596 { { /*src2 */ { FP32_SNAN(1), FP32_SNAN_V(1, FP32_FRAC_NORM_MAX), FP32_NORM_V0(1), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_NORM_V3(0), FP32_SNAN_V(1, FP32_FRAC_V3), FP32_NORM_V5(0), FP32_SNAN_V(1, FP32_FRAC_V5) } }, 8597 { /*src1 */ { FP32_1(0), FP32_1(0), FP32_SNAN_V(1, FP32_FRAC_V0), FP32_NORM_V2(1), FP32_SNAN_V(1, FP32_FRAC_V2), FP32_NORM_V4(0), FP32_SNAN_V(1, FP32_FRAC_V4), FP32_NORM_V6(1) } }, 8598 { /* => */ { FP32_QNAN_V(1, 1), FP32_QNAN_V(1, FP32_FRAC_NORM_MAX), FP32_QNAN_V(1, FP32_FRAC_V0), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(1, FP32_FRAC_V2), FP32_QNAN_V(1, FP32_FRAC_V3), FP32_QNAN_V(1, FP32_FRAC_V4), FP32_QNAN_V(1, FP32_FRAC_V5) } }, 8599 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO, 8600 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE, 8601 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE, 8602 /*xcpt? */ true, true }, 8603 /** @todo Invalids; Rounding; FZ etc. */ 7427 /*38*/ BS3CPUINSTR4_PS_INVALIDS 7428 /** @todo Underflow; Precision; Rounding; FZ etc. */ 8604 7429 }; 8605 7430 … … 9072 7897 * Invalids. 9073 7898 */ 9074 /*56*/{ { /*src2 */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V0), FP64_QNAN_V(0, FP64_FRAC_V1) } }, 9075 { /*src1 */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V2) } }, 9076 { /* => */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V2) } }, 9077 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 9078 /*128:out */ X86_MXCSR_XCPT_MASK, 9079 /*256:out */ X86_MXCSR_XCPT_MASK, 9080 /*xcpt? */ false, false }, 9081 { { /*src2 */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V0), FP64_QNAN_V(0, FP64_FRAC_V2) } }, 9082 { /*src1 */ { FP64_SNAN(0), FP64_SNAN_V(0, FP64_FRAC_NORM_MIN), FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_SNAN_V(0, FP64_FRAC_V1) } }, 9083 { /* => */ { FP64_QNAN_V(0, 1), FP64_QNAN_V(0, 1), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V1) } }, 9084 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 9085 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, 9086 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, 9087 /*xcpt? */ false, false }, 9088 { { /*src2 */ { FP64_SNAN(0), FP64_SNAN_V(0, FP64_FRAC_NORM_MIN), FP64_SNAN_V(0, FP64_FRAC_V0), FP64_SNAN_V(0, FP64_FRAC_V1) } }, 9089 { /*src1 */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V2), FP64_QNAN_V(0, FP64_FRAC_V3) } }, 9090 { /* => */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V2), FP64_QNAN_V(0, FP64_FRAC_V3) } }, 9091 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 9092 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, 9093 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, 9094 /*xcpt? */ false, false }, 9095 { { /*src2 */ { FP64_SNAN(0), FP64_SNAN_V(0, FP64_FRAC_NORM_MIN), FP64_SNAN_V(0, FP64_FRAC_V1), FP64_SNAN_V(0, FP64_FRAC_V2) } }, 9096 { /*src1 */ { FP64_SNAN(0), FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_SNAN_V(0, FP64_FRAC_V3), FP64_SNAN_V(0, FP64_FRAC_V0) } }, 9097 { /* => */ { FP64_QNAN_V(0, 1), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V3), FP64_QNAN_V(0, FP64_FRAC_V0) } }, 9098 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 9099 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, 9100 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, 9101 /*xcpt? */ false, false }, 9102 { { /*src2 */ { FP64_QNAN(0), FP64_QNAN_V(1, FP64_FRAC_NORM_MAX), FP64_NORM_V0(1), FP64_QNAN_V(0, FP64_FRAC_V1) } }, 9103 { /*src1 */ { FP64_1(0), FP64_1(1), FP64_QNAN_V(1, FP64_FRAC_V0), FP64_NORM_V2(1) } }, 9104 { /* => */ { FP64_QNAN(0), FP64_QNAN_V(1, FP64_FRAC_NORM_MAX), FP64_QNAN_V(1, FP64_FRAC_V0), FP64_QNAN_V(0, FP64_FRAC_V1) } }, 9105 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 9106 /*128:out */ X86_MXCSR_XCPT_MASK, 9107 /*256:out */ X86_MXCSR_XCPT_MASK, 9108 /*xcpt? */ false, false }, 9109 { { /*src2 */ { FP64_SNAN(1), FP64_SNAN_V(1, FP64_FRAC_NORM_MAX), FP64_NORM_V0(1), FP64_SNAN_V(0, FP64_FRAC_V1) } }, 9110 { /*src1 */ { FP64_1(0), FP64_1(0), FP64_SNAN_V(1, FP64_FRAC_V0), FP64_NORM_V2(1) } }, 9111 { /* => */ { FP64_QNAN_V(1, 1), FP64_QNAN_V(1, FP64_FRAC_NORM_MAX), FP64_QNAN_V(1, FP64_FRAC_V0), FP64_QNAN_V(0, FP64_FRAC_V1) } }, 9112 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 9113 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, 9114 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, 9115 /*xcpt? */ false, false }, 9116 { { /*src2 */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V0), FP64_QNAN_V(0, FP64_FRAC_V2) } }, 9117 { /*src1 */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V3) } }, 9118 { /* => */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V3) } }, 9119 /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 9120 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 9121 /*256:out */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 9122 /*xcpt? */ false, false }, 9123 { { /*src2 */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V0), FP64_QNAN_V(0, FP32_FRAC_V1) } }, 9124 { /*src1 */ { FP64_SNAN(0), FP64_SNAN_V(0, FP64_FRAC_NORM_MIN), FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_SNAN_V(0, FP32_FRAC_V2) } }, 9125 { /* => */ { FP64_QNAN_V(0, 1), FP64_QNAN_V(0, 1), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP32_FRAC_V2) } }, 9126 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, 9127 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE, 9128 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE, 9129 /*xcpt? */ true, true }, 9130 { { /*src2 */ { FP64_SNAN(0), FP64_SNAN_V(0, FP64_FRAC_NORM_MIN), FP64_SNAN_V(0, FP64_FRAC_V1), FP64_SNAN_V(0, FP64_FRAC_V1) } }, 9131 { /*src1 */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V3), FP64_QNAN_V(0, FP64_FRAC_V2) } }, 9132 { /* => */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V3), FP64_QNAN_V(0, FP64_FRAC_V2) } }, 9133 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, 9134 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE, 9135 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE, 9136 /*xcpt? */ true, true }, 9137 { { /*src2 */ { FP64_SNAN(0), FP64_SNAN_V(0, FP64_FRAC_NORM_MIN), FP64_SNAN_V(0, FP64_FRAC_V1), FP64_SNAN_V(0, FP64_FRAC_V2) } }, 9138 { /*src1 */ { FP64_SNAN(0), FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_SNAN_V(0, FP64_FRAC_V0), FP64_SNAN_V(0, FP64_FRAC_V3) } }, 9139 { /* => */ { FP64_QNAN_V(0, 1), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V0), FP64_QNAN_V(0, FP64_FRAC_V3) } }, 9140 /*mxcsr:in */ X86_MXCSR_RC_UP, 9141 /*128:out */ X86_MXCSR_RC_UP | X86_MXCSR_IE, 9142 /*256:out */ X86_MXCSR_RC_UP | X86_MXCSR_IE, 9143 /*xcpt? */ true, true }, 9144 { { /*src2 */ { FP64_QNAN(0), FP64_QNAN_V(1, FP64_FRAC_NORM_MAX), FP64_NORM_V0(1), FP64_QNAN_V(0, FP64_FRAC_V1) } }, 9145 { /*src1 */ { FP64_1(0), FP64_1(1), FP64_QNAN_V(1, FP64_FRAC_V3), FP64_NORM_V2(1) } }, 9146 { /* => */ { FP64_QNAN(0), FP64_QNAN_V(1, FP64_FRAC_NORM_MAX), FP64_QNAN_V(1, FP64_FRAC_V3), FP64_QNAN_V(0, FP64_FRAC_V1) } }, 9147 /*mxcsr:in */ X86_MXCSR_RC_DOWN, 9148 /*128:out */ X86_MXCSR_RC_DOWN, 9149 /*256:out */ X86_MXCSR_RC_DOWN, 9150 /*xcpt? */ false, false }, 9151 { { /*src2 */ { FP64_SNAN(1), FP64_SNAN_V(1, FP64_FRAC_NORM_MAX), FP64_NORM_V0(1), FP64_SNAN_V(0, FP64_FRAC_V2) } }, 9152 { /*src1 */ { FP64_1(0), FP64_1(0), FP64_SNAN_V(1, FP64_FRAC_V3), FP64_NORM_V2(1) } }, 9153 { /* => */ { FP64_QNAN_V(1, 1), FP64_QNAN_V(1, FP64_FRAC_NORM_MAX), FP64_QNAN_V(1, FP64_FRAC_V3), FP64_QNAN_V(0, FP64_FRAC_V2) } }, 9154 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO, 9155 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE, 9156 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE, 9157 /*xcpt? */ true, true }, 9158 /** @todo Rounding; FZ etc. */ 7899 /*56*/ BS3CPUINSTR4_PD_INVALIDS 7900 /** @todo Underflow; Precision; Rounding; FZ etc. */ 9159 7901 }; 9160 7902 … … 9281 8023 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 9282 8024 /*xcpt? */ false, false }, 9283 /** @todo Infinity; Normals; Denormals; Underflow, Precision; Rounding ,FZ etc. */8025 /** @todo Infinity; Normals; Denormals; Underflow, Precision; Rounding; FZ etc. */ 9284 8026 }; 9285 8027
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