Changeset 106039 in vbox

Timestamp:

Sep 13, 2024 8:08:58 AM (7 months ago)

Author:

vboxsync

svn:sync-xref-src-repo-rev:

164788

Message:

ValidationKit/bootsectors: bugref:10658 SIMD FP testcase: Fix incorrect exponent value for 1.5 for double-precision floating-point (was copy/paste bug from single-precision value)

File:

• trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-4.c32 (modified) (3 diffs)

trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-4.c32

@@ -2766 +2766 @@
               /*256:out  */ X86_MXCSR_RC_ZERO | X86_MXCSR_PE,
               /*xcpt?    */ true, true },
-          /** @todo Why does the below on cause PE?! */
-          { { /*src2     */ { FP64_V(0, 0xc000000000000, 0x3ff)/* 1.75*/, FP64_NORM_MAX(0), FP64_0(0), FP64_V(0, 0,               0x3fd)/*0.25*/ } },
-            { /*src1     */ { FP64_V(1, 0,               0x07d)/*-0.25*/, FP64_NORM_MAX(1), FP64_0(0), FP64_V(0, 0,               0x3fe)/*0.50*/ } },
-            { /* =>      */ { FP64_V(0, 0xbffffffffffff, 0x3ff)/* 1.50*/, FP64_0(1),        FP64_0(0), FP64_V(0, 0x8000000000000, 0x3fe)/*0.75*/ } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN | X86_MXCSR_PE,
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN | X86_MXCSR_PE,
-              /*xcpt?    */ false, false },
     /*
      * Normals.
@@ -2826 +2818 @@
               /*256:out  */ X86_MXCSR_RC_UP,
               /*xcpt?    */ false, false },
+          { { /*src2     */ { FP64_V(0, 0xc000000000000, 0x3ff)/* 1.75*/, FP64_NORM_MAX(0), FP64_0(0), FP64_V(0, 0,               0x3fd)/*0.25*/ } },
+            { /*src1     */ { FP64_V(1, 0,               0x3fd)/*-0.25*/, FP64_NORM_MAX(1), FP64_0(0), FP64_V(0, 0,               0x3fe)/*0.50*/ } },
+            { /* =>      */ { FP64_V(0, 0x8000000000000, 0x3ff)/* 1.50*/, FP64_0(1),        FP64_0(0), FP64_V(0, 0x8000000000000, 0x3fe)/*0.75*/ } },
+              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
+              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
+              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
+              /*xcpt?    */ false, false },
     /*
      * Denormals.
      */
-    /*24*/{ { /*src2     */ { FP64_DENORM_MAX(0), FP64_0(0), FP64_0(0), FP64_0(0) } },
+    /*25*/{ { /*src2     */ { FP64_DENORM_MAX(0), FP64_0(0), FP64_0(0), FP64_0(0) } },
             { /*src1     */ { FP64_0(0),          FP64_0(0), FP64_0(0), FP64_0(0) } },
             { /* =>      */ { FP64_0(0),          FP64_0(0), FP64_0(0), FP64_0(0) } },
@@ -2854 +2853 @@
      * Invalids.
      */
-    /*27*/ BS3CPUINSTR4_PD_INVALIDS
+    /*28*/ BS3CPUINSTR4_PD_INVALIDS
     /** @todo Underflow, Precision; Rounding; FZ etc. */
     };