Changeset 106041 in vbox for trunk/src/VBox

Timestamp:

Sep 13, 2024 8:57:45 AM (3 months ago)

Author:

vboxsync

Message:

ValidationKit/bootsectors: Implement SISD FP testcases for [v]divss (derived from [v]mulss); bugref:10658 [nittier nits]

File:

• trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-4.c32 (modified) (3 diffs)

trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-4.c32

@@ -7186 +7186 @@
             { /*src1     */ { FP32_0(0),    FP32_0(1),       FP32_0(1),       FP32_NORM_V2(0), FP32_NORM_V3(1), FP32_0(0),       FP32_NORM_V6(0), FP32_NORM_V2(0) } },
             { /* =>      */ { FP32_QNAN(1), FP32_0(1),       FP32_0(1),       FP32_NORM_V2(0), FP32_NORM_V3(0), FP32_0(0),       FP32_NORM_V6(0), FP32_NORM_V2(0) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN | X86_MXCSR_IE,
+              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
               /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN | X86_MXCSR_IE,
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
+              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN | X86_MXCSR_IE,
               /*xcpt?    */ false, false },
           { { /*src2     */ { FP32_0(1),    FP32_0(0), FP32_RAND_V6(0), FP32_RAND_V5(1), FP32_RAND_V4(1), FP32_RAND_V3(0), FP32_RAND_V2(1), FP32_RAND_V1(1) } },
@@ -7376 +7376 @@
               /*xcpt?    */ false, false },
           { { /*src2     */ { FP32_DENORM_MIN(0), FP32_1(0),       FP32_DENORM_MAX(0), FP32_DENORM_MAX(1), FP32_RAND_V3(0), FP32_RAND_V0(0), FP32_RAND_V0(0),    FP32_DENORM_MAX(0) } },
-            { /* =>      */ { FP32_0(0),          FP32_RAND_V4(0), FP32_DENORM_MIN(1), FP32_DENORM_MIN(0), FP32_1(0),       FP32_1(0),       FP32_DENORM_MIN(0), FP32_RAND_V4(0)    } },
-            { /*src1     */ { FP32_QNAN(1), FP32_RAND_V4(0), FP32_DENORM_MIN(1), FP32_DENORM_MIN(0), FP32_1(0),       FP32_1(0),       FP32_DENORM_MIN(0), FP32_RAND_V4(0)    } },
+            { /*src1     */ { FP32_0(0),          FP32_RAND_V4(0), FP32_DENORM_MIN(1), FP32_DENORM_MIN(0), FP32_1(0),       FP32_1(0),       FP32_DENORM_MIN(0), FP32_RAND_V4(0)    } },
+            { /* =>      */ { FP32_QNAN(1), FP32_RAND_V4(0), FP32_DENORM_MIN(1), FP32_DENORM_MIN(0), FP32_1(0),       FP32_1(0),       FP32_DENORM_MIN(0), FP32_RAND_V4(0)    } },
               /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
               /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP | X86_MXCSR_IE,
@@ -8506 +8506 @@
         { "[v]mulss",       bs3CpuInstr4_v_mulss,    0 },
         { "[v]mulsd",       bs3CpuInstr4_v_mulsd,    0 },
-        { "[v]divss",       bs3CpuInstr4_v_divss,  0 },
+        { "[v]divss",       bs3CpuInstr4_v_divss,    0 },
         { "[v]addsubps",    bs3CpuInstr4_v_addsubps, 0 },
         { "[v]addsubpd",    bs3CpuInstr4_v_addsubpd, 0 },