Index: trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-4.c32
===================================================================
--- trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-4.c32	(revision 106055)
+++ trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-4.c32	(revision 106056)
@@ -542,6 +542,9 @@
 };
 
-/** Packed single-precision invalid values. */
-#define BS3CPUINSTR4_PS_INVALIDS \
+/**
+ * Table D-1: Packed single-precision floating-point invalid values.
+ * For instructions: addps, subps, mulps, divps, addsubps, haddps, hsubps.
+ **/
+#define FP32_TABLE_D1_PS_INVALIDS \
     /*0 */{ { /*src2     */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V0),       FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V5) } },      \
             { /*src1     */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4) } },      \
@@ -629,6 +632,9 @@
               /*xcpt?    */ true, true },                                                                                                                                                                                                                                          \
 
-/** Packed double-precision floating-point invalid values. */
-#define BS3CPUINSTR4_PD_INVALIDS \
+/**
+ * Table D-1: Packed double-precision floating-point invalid values.
+ * For instructions: addpd, subpd, mulpd, divpd, addsubpd, haddpd, hsubpd.
+ **/
+#define FP64_TABLE_D1_PD_INVALIDS \
     /*0 */{ { /*src2     */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V0),       FP64_QNAN_V(0, FP64_FRAC_V1) } },      \
             { /*src1     */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V2) } },      \
@@ -716,6 +722,9 @@
               /*xcpt?    */ true, true },                                                                                                                  \
 
-/** Scalar single-precision floating-point invalid values. */
-#define BS3CPUINSTR4_SS_INVALIDS \
+/**
+ * Table D-1: Scalar single-precision floating-point invalid values.
+ * For instructions: addss, subss, mulss, divss.
+ **/
+#define FP32_TABLE_D1_SS_INVALIDS \
     /* QNan, QNan (Masked). */                                                                                                                                                                                                                                                                      \
     /*0 */{ { /*src2     */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V0),       FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V5) } },                       \
@@ -928,6 +937,9 @@
               /*xcpt?    */ true, true },                                                                                                                                                                                                                                                           \
 
-/** Scalar double-precision floating-point invalid values. */
-#define BS3CPUINSTR4_SD_INVALIDS \
+/**
+ * Table D-1: Scalar double-precision floating-point invalid values.
+ * For instructions: addsd, subsd, mulsd, divsd.
+ **/
+#define FP64_TABLE_D1_SD_INVALIDS \
     /* QNan, QNan (Masked). */                                                                                                                                              \
     /*0 */{ { /*src2     */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V0),       FP64_QNAN_V(0, FP64_FRAC_V1) } },                       \
@@ -1140,6 +1152,9 @@
               /*xcpt?    */ true, true },                                                                                                                                   \
 
-/** Horizontally packed single-precision floating-point invalid values. */
-#define BS3CPUINSTR4_H_PS_INVALIDS \
+/**
+ * Table D-1: Horizontally packed single-precision floating-point invalid values.
+ * For instructions: haddps, hsubps.
+ **/
+#define FP32_TABLE_D1_H_PS_INVALIDS \
     /*0 */{ { /*src2     */ { FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_V0),       FP32_QNAN_V(0, FP32_FRAC_V1),       FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V5) } }, \
             { /*src1     */ { FP32_QNAN(0),                       FP32_QNAN(0),                       FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4) } }, \
@@ -1227,6 +1242,9 @@
               /*xcpt?    */ true, true },                                                                                                                                                                                                                                                                 \
 
-/** Horizontally packed double-precision floating-point invalid values. */
-#define BS3CPUINSTR4_H_PD_INVALIDS \
+/**
+ * Table D-1: Horizontally packed double-precision floating-point invalid values.
+ * For instructions: haddpd, hsubpd.
+ **/
+#define FP64_TABLE_D1_H_PD_INVALIDS \
     /*0 */{ { /*src2     */ { FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(0, FP64_FRAC_V0),       FP64_QNAN_V(0, FP64_FRAC_V1)       } }, \
             { /*src1     */ { FP64_QNAN(0),                       FP64_QNAN(0),                       FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX) } }, \
@@ -2631,5 +2649,5 @@
      * Invalids.
      */
-    /*34*/ BS3CPUINSTR4_PS_INVALIDS
+    /*34*/ FP32_TABLE_D1_PS_INVALIDS
     /** @todo Underflow, Precision; Rounding; FZ etc. */
     };
@@ -2901,5 +2919,5 @@
      * Invalids.
      */
-    /*27*/ BS3CPUINSTR4_PD_INVALIDS
+    /*27*/ FP64_TABLE_D1_PD_INVALIDS
     /** @todo Underflow, Precision; Rounding; FZ etc. */
     };
@@ -3192,5 +3210,5 @@
      * Invalids.
      */
-    /*30*/ BS3CPUINSTR4_SS_INVALIDS
+    /*30*/ FP32_TABLE_D1_SS_INVALIDS
     /** @todo Underflow; Precision; Rounding; FZ etc. */
     };
@@ -3486,5 +3504,5 @@
      * Invalids.
      */
-    /*32*/ BS3CPUINSTR4_SD_INVALIDS
+    /*32*/ FP64_TABLE_D1_SD_INVALIDS
     /** @todo Underflow, Precision; Rounding; FZ etc. */
     };
@@ -3780,5 +3798,5 @@
      * Invalids.
      */
-    /*32*/ BS3CPUINSTR4_H_PS_INVALIDS
+    /*32*/ FP32_TABLE_D1_H_PS_INVALIDS
     /** @todo Underflow; Precision; Rounding; FZ etc. */
     };
@@ -4077,5 +4095,5 @@
      * Invalids.
      */
-    /*31*/ BS3CPUINSTR4_H_PD_INVALIDS
+    /*31*/ FP64_TABLE_D1_H_PD_INVALIDS
     /** @todo Underflow; Precision; Rounding; FZ etc. */
     };
@@ -4396,5 +4414,5 @@
      * Invalids.
      */
-    /*34*/ BS3CPUINSTR4_PS_INVALIDS
+    /*34*/ FP32_TABLE_D1_PS_INVALIDS
     /** @todo Underflow; Precision; Rounding; FZ etc. */
     };
@@ -4694,5 +4712,5 @@
      * Invalids.
      */
-    /*31*/ BS3CPUINSTR4_PD_INVALIDS
+    /*31*/ FP64_TABLE_D1_PD_INVALIDS
     /** @todo Underflow; Precision; Rounding; FZ etc. */
     };
@@ -5006,5 +5024,5 @@
      * Invalids.
      */
-    /*30*/ BS3CPUINSTR4_SS_INVALIDS
+    /*30*/ FP32_TABLE_D1_SS_INVALIDS
     /** @todo Underflow; Precision; Rounding; FZ etc. */
     };
@@ -5335,5 +5353,5 @@
      * Invalids.
      */
-    /*32*/ BS3CPUINSTR4_SD_INVALIDS
+    /*32*/ FP64_TABLE_D1_SD_INVALIDS
     /** @todo Underflow; Precision; Rounding; FZ etc. */
     };
@@ -5643,5 +5661,5 @@
      * Invalids.
      */
-    /*32*/ BS3CPUINSTR4_H_PS_INVALIDS
+    /*32*/ FP32_TABLE_D1_H_PS_INVALIDS
     /** @todo Underflow; Precision; Rounding; FZ etc. */
     };
@@ -5909,5 +5927,5 @@
      * Invalids.
      */
-    /*27*/ BS3CPUINSTR4_H_PD_INVALIDS
+    /*27*/ FP64_TABLE_D1_H_PD_INVALIDS
     /** @todo Underflow; Precision; Rounding; FZ etc. */
     };
@@ -6272,5 +6290,5 @@
      * Invalids.
      */
-    /*40*/ BS3CPUINSTR4_PS_INVALIDS
+    /*40*/ FP32_TABLE_D1_PS_INVALIDS
     /** @todo Underflow, Precision; Rounding; FZ etc. */
     };
@@ -6584,5 +6602,5 @@
      * Invalids.
      */
-    /*33*/ BS3CPUINSTR4_PD_INVALIDS
+    /*33*/ FP64_TABLE_D1_PD_INVALIDS
     /** @todo Underflow, Precision; Rounding; FZ etc. */
     };
@@ -6859,5 +6877,5 @@
      * Invalids.
      */
-    /*28*/ BS3CPUINSTR4_SS_INVALIDS
+    /*28*/ FP32_TABLE_D1_SS_INVALIDS
     /** @todo Underflow, Precision; Rounding; FZ etc. */
     };
@@ -7156,5 +7174,5 @@
      * Invalids.
      */
-    /*33*/ BS3CPUINSTR4_SD_INVALIDS
+    /*33*/ FP64_TABLE_D1_SD_INVALIDS
     /** @todo Underflow, Precision; Rounding; FZ etc. */
     };
@@ -7434,5 +7452,5 @@
      * Invalids.
      */
-    /*30*/ BS3CPUINSTR4_SS_INVALIDS
+    /*30*/ FP32_TABLE_D1_SS_INVALIDS
     /** @todo Underflow; Precision; Rounding, FZ etc. */
     };
@@ -7809,5 +7827,5 @@
      * Invalids.
      */
-    /*40*/ BS3CPUINSTR4_SD_INVALIDS
+    /*40*/ FP64_TABLE_D1_SD_INVALIDS
     /** @todo Underflow, Precision; Rounding; FZ etc. */
     };
@@ -8156,5 +8174,5 @@
      * Invalids.
      */
-    /*38*/ BS3CPUINSTR4_PS_INVALIDS
+    /*38*/ FP32_TABLE_D1_PS_INVALIDS
     /** @todo Underflow; Precision; Rounding; FZ etc. */
     };
@@ -8630,5 +8648,5 @@
      * Invalids.
      */
-    /*56*/ BS3CPUINSTR4_PD_INVALIDS
+    /*56*/ FP64_TABLE_D1_PD_INVALIDS
     /** @todo Underflow; Precision; Rounding; FZ etc. */
     };
